NO Ultimate: Cannot open display: This is Ultimate 0.1.24-8dc7c08-m [2020-06-22 00:12:55,081 INFO L170 SettingsManager]: Resetting all preferences to default values... [2020-06-22 00:12:55,083 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2020-06-22 00:12:55,094 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2020-06-22 00:12:55,095 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2020-06-22 00:12:55,095 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2020-06-22 00:12:55,097 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2020-06-22 00:12:55,098 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2020-06-22 00:12:55,100 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2020-06-22 00:12:55,101 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2020-06-22 00:12:55,101 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2020-06-22 00:12:55,102 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2020-06-22 00:12:55,102 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2020-06-22 00:12:55,103 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2020-06-22 00:12:55,104 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2020-06-22 00:12:55,105 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2020-06-22 00:12:55,106 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2020-06-22 00:12:55,108 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2020-06-22 00:12:55,110 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2020-06-22 00:12:55,111 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2020-06-22 00:12:55,112 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2020-06-22 00:12:55,113 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2020-06-22 00:12:55,115 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2020-06-22 00:12:55,115 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2020-06-22 00:12:55,116 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2020-06-22 00:12:55,116 INFO L174 SettingsManager]: Resetting IcfgToChc preferences to default values [2020-06-22 00:12:55,117 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2020-06-22 00:12:55,118 INFO L177 SettingsManager]: ReqToTest provides no preferences, ignoring... [2020-06-22 00:12:55,118 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2020-06-22 00:12:55,118 INFO L174 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2020-06-22 00:12:55,119 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2020-06-22 00:12:55,120 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2020-06-22 00:12:55,121 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2020-06-22 00:12:55,121 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2020-06-22 00:12:55,122 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2020-06-22 00:12:55,122 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2020-06-22 00:12:55,122 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2020-06-22 00:12:55,123 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2020-06-22 00:12:55,124 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2020-06-22 00:12:55,124 INFO L98 SettingsManager]: Beginning loading settings from /export/starexec/sandbox/solver/bin/./../termcomp2017.epf [2020-06-22 00:12:55,138 INFO L110 SettingsManager]: Loading preferences was successful [2020-06-22 00:12:55,139 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2020-06-22 00:12:55,140 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2020-06-22 00:12:55,140 INFO L133 SettingsManager]: * Rewrite not-equals=true [2020-06-22 00:12:55,140 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2020-06-22 00:12:55,140 INFO L133 SettingsManager]: * Minimize states using LBE with the strategy=SINGLE [2020-06-22 00:12:55,140 INFO L133 SettingsManager]: * Use SBE=true [2020-06-22 00:12:55,141 INFO L131 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2020-06-22 00:12:55,141 INFO L133 SettingsManager]: * Use old map elimination=false [2020-06-22 00:12:55,141 INFO L133 SettingsManager]: * Use external solver (rank synthesis)=false [2020-06-22 00:12:55,141 INFO L133 SettingsManager]: * Buchi interpolant automaton construction strategy=DANDELION [2020-06-22 00:12:55,141 INFO L133 SettingsManager]: * Use only trivial implications for array writes=true [2020-06-22 00:12:55,142 INFO L133 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2020-06-22 00:12:55,142 INFO L133 SettingsManager]: * Construct termination proof for TermComp=true [2020-06-22 00:12:55,142 INFO L133 SettingsManager]: * Command for external solver (GNTA synthesis)=z3 SMTLIB2_COMPLIANT=true -memory:4560 -smt2 -in -t:12000 [2020-06-22 00:12:55,142 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2020-06-22 00:12:55,142 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2020-06-22 00:12:55,142 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2020-06-22 00:12:55,143 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2020-06-22 00:12:55,143 INFO L133 SettingsManager]: * Assume nondeterminstic values are in range=false [2020-06-22 00:12:55,143 INFO L133 SettingsManager]: * How to treat unsigned ints differently from normal ones=IGNORE [2020-06-22 00:12:55,143 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2020-06-22 00:12:55,143 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2020-06-22 00:12:55,144 INFO L133 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2020-06-22 00:12:55,144 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:4560 -smt2 -in -t:5000 [2020-06-22 00:12:55,144 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2020-06-22 00:12:55,144 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2020-06-22 00:12:55,144 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2020-06-22 00:12:55,144 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2020-06-22 00:12:55,169 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2020-06-22 00:12:55,182 INFO L259 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2020-06-22 00:12:55,186 INFO L215 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2020-06-22 00:12:55,187 INFO L271 PluginConnector]: Initializing CDTParser... [2020-06-22 00:12:55,188 INFO L276 PluginConnector]: CDTParser initialized [2020-06-22 00:12:55,188 INFO L430 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /export/starexec/sandbox/benchmark/theBenchmark.c [2020-06-22 00:12:55,250 INFO L221 CDTParser]: Created temporary CDT project at /export/starexec/sandbox/tmp/455eb6e091434870913c2f07a7db46ed/FLAGa2babddb3 [2020-06-22 00:12:55,629 INFO L307 CDTParser]: Found 1 translation units. [2020-06-22 00:12:55,630 INFO L161 CDTParser]: Scanning /export/starexec/sandbox/benchmark/theBenchmark.c [2020-06-22 00:12:55,641 INFO L355 CDTParser]: About to delete temporary CDT project at /export/starexec/sandbox/tmp/455eb6e091434870913c2f07a7db46ed/FLAGa2babddb3 [2020-06-22 00:12:56,005 INFO L363 CDTParser]: Successfully deleted /export/starexec/sandbox/tmp/455eb6e091434870913c2f07a7db46ed [2020-06-22 00:12:56,017 INFO L297 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2020-06-22 00:12:56,019 INFO L131 ToolchainWalker]: Walking toolchain with 7 elements. [2020-06-22 00:12:56,020 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2020-06-22 00:12:56,020 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2020-06-22 00:12:56,024 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2020-06-22 00:12:56,024 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 22.06 12:12:56" (1/1) ... [2020-06-22 00:12:56,028 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1c3dbf7a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.06 12:12:56, skipping insertion in model container [2020-06-22 00:12:56,028 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 22.06 12:12:56" (1/1) ... [2020-06-22 00:12:56,035 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2020-06-22 00:12:56,076 INFO L176 MainTranslator]: Built tables and reachable declarations [2020-06-22 00:12:56,360 INFO L206 PostProcessor]: Analyzing one entry point: main [2020-06-22 00:12:56,367 INFO L191 MainTranslator]: Completed pre-run [2020-06-22 00:12:56,429 INFO L206 PostProcessor]: Analyzing one entry point: main [2020-06-22 00:12:56,453 INFO L195 MainTranslator]: Completed translation [2020-06-22 00:12:56,454 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.06 12:12:56 WrapperNode [2020-06-22 00:12:56,454 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2020-06-22 00:12:56,455 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2020-06-22 00:12:56,455 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2020-06-22 00:12:56,455 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2020-06-22 00:12:56,465 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.06 12:12:56" (1/1) ... [2020-06-22 00:12:56,475 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.06 12:12:56" (1/1) ... [2020-06-22 00:12:56,537 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2020-06-22 00:12:56,537 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2020-06-22 00:12:56,537 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2020-06-22 00:12:56,537 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2020-06-22 00:12:56,548 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.06 12:12:56" (1/1) ... [2020-06-22 00:12:56,549 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.06 12:12:56" (1/1) ... [2020-06-22 00:12:56,555 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.06 12:12:56" (1/1) ... [2020-06-22 00:12:56,556 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.06 12:12:56" (1/1) ... [2020-06-22 00:12:56,576 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.06 12:12:56" (1/1) ... [2020-06-22 00:12:56,598 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.06 12:12:56" (1/1) ... [2020-06-22 00:12:56,602 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.06 12:12:56" (1/1) ... [2020-06-22 00:12:56,609 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2020-06-22 00:12:56,610 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2020-06-22 00:12:56,610 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2020-06-22 00:12:56,610 INFO L276 PluginConnector]: RCFGBuilder initialized [2020-06-22 00:12:56,611 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.06 12:12:56" (1/1) ... No working directory specified, using /export/starexec/sandbox/solver/bin/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:4560 -smt2 -in -t:5000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:4560 -smt2 -in -t:5000 [2020-06-22 00:12:56,697 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2020-06-22 00:12:56,697 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2020-06-22 00:12:57,960 INFO L281 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2020-06-22 00:12:57,960 INFO L286 CfgBuilder]: Removed 218 assue(true) statements. [2020-06-22 00:12:57,962 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 22.06 12:12:57 BoogieIcfgContainer [2020-06-22 00:12:57,962 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2020-06-22 00:12:57,963 INFO L113 PluginConnector]: ------------------------BlockEncodingV2---------------------------- [2020-06-22 00:12:57,963 INFO L271 PluginConnector]: Initializing BlockEncodingV2... [2020-06-22 00:12:57,965 INFO L276 PluginConnector]: BlockEncodingV2 initialized [2020-06-22 00:12:57,966 INFO L185 PluginConnector]: Executing the observer BlockEncodingObserver from plugin BlockEncodingV2 for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 22.06 12:12:57" (1/1) ... [2020-06-22 00:12:58,008 INFO L313 BlockEncoder]: Initial Icfg 611 locations, 944 edges [2020-06-22 00:12:58,009 INFO L258 BlockEncoder]: Using Remove infeasible edges [2020-06-22 00:12:58,010 INFO L263 BlockEncoder]: Using Maximize final states [2020-06-22 00:12:58,011 INFO L270 BlockEncoder]: Using Minimize states even if more edges are added than removed.=false [2020-06-22 00:12:58,011 INFO L276 BlockEncoder]: Using Minimize states using LBE with the strategy=SINGLE [2020-06-22 00:12:58,013 INFO L296 BlockEncoder]: Using Remove sink states [2020-06-22 00:12:58,014 INFO L171 BlockEncoder]: Using Apply optimizations until nothing changes=true [2020-06-22 00:12:58,014 INFO L179 BlockEncoder]: Using Rewrite not-equals [2020-06-22 00:12:58,100 INFO L185 BlockEncoder]: Using Use SBE [2020-06-22 00:12:58,194 INFO L200 BlockEncoder]: SBE split 314 edges [2020-06-22 00:12:58,203 INFO L70 emoveInfeasibleEdges]: Removed 21 edges and 0 locations because of local infeasibility [2020-06-22 00:12:58,207 INFO L71 MaximizeFinalStates]: 0 new accepting states [2020-06-22 00:12:58,321 INFO L100 BaseMinimizeStates]: Removed 178 edges and 89 locations by large block encoding [2020-06-22 00:12:58,325 INFO L70 RemoveSinkStates]: Removed 4 edges and 3 locations by removing sink states [2020-06-22 00:12:58,328 INFO L70 emoveInfeasibleEdges]: Removed 0 edges and 0 locations because of local infeasibility [2020-06-22 00:12:58,329 INFO L71 MaximizeFinalStates]: 0 new accepting states [2020-06-22 00:12:58,332 INFO L100 BaseMinimizeStates]: Removed 2 edges and 1 locations by large block encoding [2020-06-22 00:12:58,333 INFO L70 RemoveSinkStates]: Removed 0 edges and 0 locations by removing sink states [2020-06-22 00:12:58,335 INFO L70 emoveInfeasibleEdges]: Removed 0 edges and 0 locations because of local infeasibility [2020-06-22 00:12:58,337 INFO L71 MaximizeFinalStates]: 0 new accepting states [2020-06-22 00:12:58,337 INFO L100 BaseMinimizeStates]: Removed 0 edges and 0 locations by large block encoding [2020-06-22 00:12:58,338 INFO L70 RemoveSinkStates]: Removed 0 edges and 0 locations by removing sink states [2020-06-22 00:12:58,341 INFO L313 BlockEncoder]: Encoded RCFG 518 locations, 1143 edges [2020-06-22 00:12:58,341 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.blockencoding CFG 22.06 12:12:58 BasicIcfg [2020-06-22 00:12:58,341 INFO L132 PluginConnector]: ------------------------ END BlockEncodingV2---------------------------- [2020-06-22 00:12:58,342 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2020-06-22 00:12:58,342 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2020-06-22 00:12:58,346 INFO L276 PluginConnector]: TraceAbstraction initialized [2020-06-22 00:12:58,346 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 22.06 12:12:56" (1/4) ... [2020-06-22 00:12:58,347 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@58b3b32 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 22.06 12:12:58, skipping insertion in model container [2020-06-22 00:12:58,348 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.06 12:12:56" (2/4) ... [2020-06-22 00:12:58,348 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@58b3b32 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 22.06 12:12:58, skipping insertion in model container [2020-06-22 00:12:58,348 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 22.06 12:12:57" (3/4) ... [2020-06-22 00:12:58,349 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@58b3b32 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 22.06 12:12:58, skipping insertion in model container [2020-06-22 00:12:58,349 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.blockencoding CFG 22.06 12:12:58" (4/4) ... [2020-06-22 00:12:58,350 INFO L112 eAbstractionObserver]: Analyzing ICFG theBenchmark.c_BEv2 [2020-06-22 00:12:58,360 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:ForwardPredicates Determinization: PREDICATE_ABSTRACTION [2020-06-22 00:12:58,369 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 0 error locations. [2020-06-22 00:12:58,387 INFO L257 AbstractCegarLoop]: Starting to check reachability of 0 error locations. [2020-06-22 00:12:58,419 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2020-06-22 00:12:58,420 INFO L382 AbstractCegarLoop]: Interprodecural is true [2020-06-22 00:12:58,420 INFO L383 AbstractCegarLoop]: Hoare is true [2020-06-22 00:12:58,420 INFO L384 AbstractCegarLoop]: Compute interpolants for ForwardPredicates [2020-06-22 00:12:58,420 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2020-06-22 00:12:58,421 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2020-06-22 00:12:58,421 INFO L387 AbstractCegarLoop]: Difference is false [2020-06-22 00:12:58,421 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2020-06-22 00:12:58,421 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2020-06-22 00:12:58,447 INFO L276 IsEmpty]: Start isEmpty. Operand 518 states. [2020-06-22 00:12:58,463 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2020-06-22 00:12:58,474 INFO L343 DoubleDeckerVisitor]: Before removal of dead ends 518 states. [2020-06-22 00:12:58,679 INFO L451 ceAbstractionStarter]: At program point L531(lines 493 533) the Hoare annotation is: true [2020-06-22 00:12:58,679 INFO L448 ceAbstractionStarter]: For program point L498(lines 498 528) no Hoare annotation was computed. [2020-06-22 00:12:58,680 INFO L451 ceAbstractionStarter]: At program point L531-1(lines 493 533) the Hoare annotation is: true [2020-06-22 00:12:58,680 INFO L448 ceAbstractionStarter]: For program point L498-1(lines 498 528) no Hoare annotation was computed. [2020-06-22 00:12:58,680 INFO L451 ceAbstractionStarter]: At program point L531-2(lines 493 533) the Hoare annotation is: true [2020-06-22 00:12:58,680 INFO L448 ceAbstractionStarter]: For program point L498-2(lines 498 528) no Hoare annotation was computed. [2020-06-22 00:12:58,680 INFO L448 ceAbstractionStarter]: For program point L102(lines 102 110) no Hoare annotation was computed. [2020-06-22 00:12:58,680 INFO L448 ceAbstractionStarter]: For program point L763-1(lines 732 800) no Hoare annotation was computed. [2020-06-22 00:12:58,680 INFO L448 ceAbstractionStarter]: For program point L763-3(lines 732 800) no Hoare annotation was computed. [2020-06-22 00:12:58,681 INFO L451 ceAbstractionStarter]: At program point L565(lines 541 649) the Hoare annotation is: true [2020-06-22 00:12:58,681 INFO L448 ceAbstractionStarter]: For program point L466-1(lines 450 488) no Hoare annotation was computed. [2020-06-22 00:12:58,681 INFO L448 ceAbstractionStarter]: For program point L367(lines 367 376) no Hoare annotation was computed. [2020-06-22 00:12:58,681 INFO L448 ceAbstractionStarter]: For program point L367-2(lines 367 376) no Hoare annotation was computed. [2020-06-22 00:12:58,681 INFO L448 ceAbstractionStarter]: For program point L367-3(lines 367 376) no Hoare annotation was computed. [2020-06-22 00:12:58,681 INFO L448 ceAbstractionStarter]: For program point L367-5(lines 367 376) no Hoare annotation was computed. [2020-06-22 00:12:58,681 INFO L448 ceAbstractionStarter]: For program point L367-6(lines 367 376) no Hoare annotation was computed. [2020-06-22 00:12:58,682 INFO L448 ceAbstractionStarter]: For program point L367-8(lines 367 376) no Hoare annotation was computed. [2020-06-22 00:12:58,682 INFO L448 ceAbstractionStarter]: For program point L367-9(lines 367 376) no Hoare annotation was computed. [2020-06-22 00:12:58,682 INFO L448 ceAbstractionStarter]: For program point L367-11(lines 367 376) no Hoare annotation was computed. [2020-06-22 00:12:58,682 INFO L448 ceAbstractionStarter]: For program point L367-12(lines 367 376) no Hoare annotation was computed. [2020-06-22 00:12:58,682 INFO L451 ceAbstractionStarter]: At program point L995(lines 984 997) the Hoare annotation is: true [2020-06-22 00:12:58,682 INFO L448 ceAbstractionStarter]: For program point L367-14(lines 367 376) no Hoare annotation was computed. [2020-06-22 00:12:58,682 INFO L448 ceAbstractionStarter]: For program point L367-15(lines 367 376) no Hoare annotation was computed. [2020-06-22 00:12:58,682 INFO L448 ceAbstractionStarter]: For program point L863(lines 863 867) no Hoare annotation was computed. [2020-06-22 00:12:58,683 INFO L448 ceAbstractionStarter]: For program point L896-1(lines 895 963) no Hoare annotation was computed. [2020-06-22 00:12:58,683 INFO L448 ceAbstractionStarter]: For program point L367-17(lines 367 376) no Hoare annotation was computed. [2020-06-22 00:12:58,683 INFO L451 ceAbstractionStarter]: At program point L863-2(lines 733 737) the Hoare annotation is: true [2020-06-22 00:12:58,683 INFO L448 ceAbstractionStarter]: For program point L367-18(lines 367 376) no Hoare annotation was computed. [2020-06-22 00:12:58,683 INFO L448 ceAbstractionStarter]: For program point L863-3(lines 863 867) no Hoare annotation was computed. [2020-06-22 00:12:58,683 INFO L448 ceAbstractionStarter]: For program point L367-20(lines 367 376) no Hoare annotation was computed. [2020-06-22 00:12:58,683 INFO L448 ceAbstractionStarter]: For program point L367-21(lines 367 376) no Hoare annotation was computed. [2020-06-22 00:12:58,683 INFO L451 ceAbstractionStarter]: At program point L863-5(lines 1 1069) the Hoare annotation is: true [2020-06-22 00:12:58,684 INFO L448 ceAbstractionStarter]: For program point L863-6(lines 863 867) no Hoare annotation was computed. [2020-06-22 00:12:58,684 INFO L448 ceAbstractionStarter]: For program point L665-1(lines 659 727) no Hoare annotation was computed. [2020-06-22 00:12:58,684 INFO L448 ceAbstractionStarter]: For program point L367-23(lines 367 376) no Hoare annotation was computed. [2020-06-22 00:12:58,684 INFO L451 ceAbstractionStarter]: At program point L863-8(lines 1 1069) the Hoare annotation is: true [2020-06-22 00:12:58,684 INFO L448 ceAbstractionStarter]: For program point L367-24(lines 367 376) no Hoare annotation was computed. [2020-06-22 00:12:58,684 INFO L448 ceAbstractionStarter]: For program point L665-3(lines 659 727) no Hoare annotation was computed. [2020-06-22 00:12:58,684 INFO L448 ceAbstractionStarter]: For program point L863-9(lines 863 867) no Hoare annotation was computed. [2020-06-22 00:12:58,684 INFO L448 ceAbstractionStarter]: For program point L367-26(lines 367 376) no Hoare annotation was computed. [2020-06-22 00:12:58,685 INFO L451 ceAbstractionStarter]: At program point L863-11(lines 1 1069) the Hoare annotation is: true [2020-06-22 00:12:58,685 INFO L448 ceAbstractionStarter]: For program point L863-12(lines 863 867) no Hoare annotation was computed. [2020-06-22 00:12:58,685 INFO L451 ceAbstractionStarter]: At program point L863-14(lines 1 1069) the Hoare annotation is: true [2020-06-22 00:12:58,685 INFO L448 ceAbstractionStarter]: For program point L368(lines 368 373) no Hoare annotation was computed. [2020-06-22 00:12:58,685 INFO L448 ceAbstractionStarter]: For program point L863-15(lines 863 867) no Hoare annotation was computed. [2020-06-22 00:12:58,685 INFO L448 ceAbstractionStarter]: For program point L368-1(lines 368 373) no Hoare annotation was computed. [2020-06-22 00:12:58,685 INFO L448 ceAbstractionStarter]: For program point L368-2(lines 368 373) no Hoare annotation was computed. [2020-06-22 00:12:58,686 INFO L451 ceAbstractionStarter]: At program point L863-17(lines 1 1069) the Hoare annotation is: true [2020-06-22 00:12:58,686 INFO L448 ceAbstractionStarter]: For program point L368-3(lines 368 373) no Hoare annotation was computed. [2020-06-22 00:12:58,686 INFO L448 ceAbstractionStarter]: For program point L863-18(lines 863 867) no Hoare annotation was computed. [2020-06-22 00:12:58,686 INFO L448 ceAbstractionStarter]: For program point L368-4(lines 368 373) no Hoare annotation was computed. [2020-06-22 00:12:58,686 INFO L448 ceAbstractionStarter]: For program point L368-5(lines 368 373) no Hoare annotation was computed. [2020-06-22 00:12:58,686 INFO L451 ceAbstractionStarter]: At program point L863-20(lines 1 1069) the Hoare annotation is: true [2020-06-22 00:12:58,686 INFO L448 ceAbstractionStarter]: For program point L368-6(lines 368 373) no Hoare annotation was computed. [2020-06-22 00:12:58,686 INFO L448 ceAbstractionStarter]: For program point L863-21(lines 863 867) no Hoare annotation was computed. [2020-06-22 00:12:58,687 INFO L448 ceAbstractionStarter]: For program point L137(lines 137 145) no Hoare annotation was computed. [2020-06-22 00:12:58,687 INFO L448 ceAbstractionStarter]: For program point L368-7(lines 368 373) no Hoare annotation was computed. [2020-06-22 00:12:58,687 INFO L451 ceAbstractionStarter]: At program point L863-23(lines 733 737) the Hoare annotation is: true [2020-06-22 00:12:58,687 INFO L448 ceAbstractionStarter]: For program point L368-8(lines 368 373) no Hoare annotation was computed. [2020-06-22 00:12:58,687 INFO L448 ceAbstractionStarter]: For program point L863-24(lines 863 867) no Hoare annotation was computed. [2020-06-22 00:12:58,687 INFO L451 ceAbstractionStarter]: At program point L863-26(lines 896 900) the Hoare annotation is: true [2020-06-22 00:12:58,687 INFO L448 ceAbstractionStarter]: For program point L831(lines 831 835) no Hoare annotation was computed. [2020-06-22 00:12:58,688 INFO L448 ceAbstractionStarter]: For program point L831-2(lines 831 835) no Hoare annotation was computed. [2020-06-22 00:12:58,688 INFO L448 ceAbstractionStarter]: For program point L831-3(lines 831 835) no Hoare annotation was computed. [2020-06-22 00:12:58,688 INFO L448 ceAbstractionStarter]: For program point L831-5(lines 831 835) no Hoare annotation was computed. [2020-06-22 00:12:58,688 INFO L448 ceAbstractionStarter]: For program point L831-6(lines 831 835) no Hoare annotation was computed. [2020-06-22 00:12:58,688 INFO L448 ceAbstractionStarter]: For program point L831-8(lines 831 835) no Hoare annotation was computed. [2020-06-22 00:12:58,688 INFO L448 ceAbstractionStarter]: For program point L831-9(lines 831 835) no Hoare annotation was computed. [2020-06-22 00:12:58,688 INFO L448 ceAbstractionStarter]: For program point L831-11(lines 831 835) no Hoare annotation was computed. [2020-06-22 00:12:58,688 INFO L451 ceAbstractionStarter]: At program point L435(lines 423 437) the Hoare annotation is: true [2020-06-22 00:12:58,689 INFO L448 ceAbstractionStarter]: For program point L831-12(lines 831 835) no Hoare annotation was computed. [2020-06-22 00:12:58,689 INFO L451 ceAbstractionStarter]: At program point L435-1(lines 423 437) the Hoare annotation is: true [2020-06-22 00:12:58,689 INFO L448 ceAbstractionStarter]: For program point L831-14(lines 831 835) no Hoare annotation was computed. [2020-06-22 00:12:58,689 INFO L451 ceAbstractionStarter]: At program point L435-2(lines 423 437) the Hoare annotation is: true [2020-06-22 00:12:58,689 INFO L448 ceAbstractionStarter]: For program point L831-15(lines 831 835) no Hoare annotation was computed. [2020-06-22 00:12:58,689 INFO L451 ceAbstractionStarter]: At program point L435-3(lines 423 437) the Hoare annotation is: true [2020-06-22 00:12:58,689 INFO L451 ceAbstractionStarter]: At program point L435-4(lines 423 437) the Hoare annotation is: true [2020-06-22 00:12:58,690 INFO L448 ceAbstractionStarter]: For program point L831-17(lines 831 835) no Hoare annotation was computed. [2020-06-22 00:12:58,690 INFO L451 ceAbstractionStarter]: At program point L435-5(lines 423 437) the Hoare annotation is: true [2020-06-22 00:12:58,690 INFO L448 ceAbstractionStarter]: For program point L831-18(lines 831 835) no Hoare annotation was computed. [2020-06-22 00:12:58,690 INFO L451 ceAbstractionStarter]: At program point L435-6(lines 423 437) the Hoare annotation is: true [2020-06-22 00:12:58,690 INFO L451 ceAbstractionStarter]: At program point L435-7(lines 423 437) the Hoare annotation is: true [2020-06-22 00:12:58,690 INFO L448 ceAbstractionStarter]: For program point L831-20(lines 831 835) no Hoare annotation was computed. [2020-06-22 00:12:58,690 INFO L451 ceAbstractionStarter]: At program point L435-8(lines 423 437) the Hoare annotation is: true [2020-06-22 00:12:58,690 INFO L448 ceAbstractionStarter]: For program point L831-21(lines 831 835) no Hoare annotation was computed. [2020-06-22 00:12:58,691 INFO L451 ceAbstractionStarter]: At program point L105(lines 105 109) the Hoare annotation is: true [2020-06-22 00:12:58,691 INFO L448 ceAbstractionStarter]: For program point L831-23(lines 831 835) no Hoare annotation was computed. [2020-06-22 00:12:58,691 INFO L448 ceAbstractionStarter]: For program point L831-24(lines 831 835) no Hoare annotation was computed. [2020-06-22 00:12:58,691 INFO L448 ceAbstractionStarter]: For program point L831-26(lines 831 835) no Hoare annotation was computed. [2020-06-22 00:12:58,691 INFO L448 ceAbstractionStarter]: For program point L931-1(lines 895 963) no Hoare annotation was computed. [2020-06-22 00:12:58,691 INFO L448 ceAbstractionStarter]: For program point L733-1(lines 732 800) no Hoare annotation was computed. [2020-06-22 00:12:58,691 INFO L448 ceAbstractionStarter]: For program point L700-1(lines 659 727) no Hoare annotation was computed. [2020-06-22 00:12:58,692 INFO L448 ceAbstractionStarter]: For program point L733-3(lines 732 800) no Hoare annotation was computed. [2020-06-22 00:12:58,692 INFO L448 ceAbstractionStarter]: For program point L700-3(lines 659 727) no Hoare annotation was computed. [2020-06-22 00:12:58,692 INFO L448 ceAbstractionStarter]: For program point L568(lines 568 575) no Hoare annotation was computed. [2020-06-22 00:12:58,692 INFO L448 ceAbstractionStarter]: For program point L502(lines 502 527) no Hoare annotation was computed. [2020-06-22 00:12:58,692 INFO L448 ceAbstractionStarter]: For program point L502-1(lines 502 527) no Hoare annotation was computed. [2020-06-22 00:12:58,692 INFO L448 ceAbstractionStarter]: For program point L502-2(lines 502 527) no Hoare annotation was computed. [2020-06-22 00:12:58,692 INFO L448 ceAbstractionStarter]: For program point L172(lines 172 180) no Hoare annotation was computed. [2020-06-22 00:12:58,692 INFO L451 ceAbstractionStarter]: At program point L635(lines 541 649) the Hoare annotation is: true [2020-06-22 00:12:58,693 INFO L451 ceAbstractionStarter]: At program point L140(lines 140 144) the Hoare annotation is: true [2020-06-22 00:12:58,693 INFO L448 ceAbstractionStarter]: For program point L768-1(lines 732 800) no Hoare annotation was computed. [2020-06-22 00:12:58,693 INFO L448 ceAbstractionStarter]: For program point L768-3(lines 732 800) no Hoare annotation was computed. [2020-06-22 00:12:58,693 INFO L448 ceAbstractionStarter]: For program point L471-1(lines 450 488) no Hoare annotation was computed. [2020-06-22 00:12:58,693 INFO L448 ceAbstractionStarter]: For program point L405(lines 405 414) no Hoare annotation was computed. [2020-06-22 00:12:58,693 INFO L448 ceAbstractionStarter]: For program point L405-2(lines 405 414) no Hoare annotation was computed. [2020-06-22 00:12:58,693 INFO L448 ceAbstractionStarter]: For program point L405-3(lines 405 414) no Hoare annotation was computed. [2020-06-22 00:12:58,693 INFO L448 ceAbstractionStarter]: For program point L405-5(lines 405 414) no Hoare annotation was computed. [2020-06-22 00:12:58,694 INFO L448 ceAbstractionStarter]: For program point L207(lines 207 215) no Hoare annotation was computed. [2020-06-22 00:12:58,694 INFO L448 ceAbstractionStarter]: For program point L405-6(lines 405 414) no Hoare annotation was computed. [2020-06-22 00:12:58,694 INFO L448 ceAbstractionStarter]: For program point L405-8(lines 405 414) no Hoare annotation was computed. [2020-06-22 00:12:58,694 INFO L448 ceAbstractionStarter]: For program point L405-9(lines 405 414) no Hoare annotation was computed. [2020-06-22 00:12:58,694 INFO L448 ceAbstractionStarter]: For program point L405-11(lines 405 414) no Hoare annotation was computed. [2020-06-22 00:12:58,694 INFO L448 ceAbstractionStarter]: For program point L405-12(lines 405 414) no Hoare annotation was computed. [2020-06-22 00:12:58,694 INFO L451 ceAbstractionStarter]: At program point L1033(lines 1033 1042) the Hoare annotation is: true [2020-06-22 00:12:58,694 INFO L451 ceAbstractionStarter]: At program point L1033-1(lines 1033 1042) the Hoare annotation is: true [2020-06-22 00:12:58,694 INFO L448 ceAbstractionStarter]: For program point L405-14(lines 405 414) no Hoare annotation was computed. [2020-06-22 00:12:58,695 INFO L448 ceAbstractionStarter]: For program point L405-15(lines 405 414) no Hoare annotation was computed. [2020-06-22 00:12:58,695 INFO L448 ceAbstractionStarter]: For program point L405-17(lines 405 414) no Hoare annotation was computed. [2020-06-22 00:12:58,695 INFO L448 ceAbstractionStarter]: For program point L901-1(lines 895 963) no Hoare annotation was computed. [2020-06-22 00:12:58,695 INFO L448 ceAbstractionStarter]: For program point L405-18(lines 405 414) no Hoare annotation was computed. [2020-06-22 00:12:58,695 INFO L448 ceAbstractionStarter]: For program point L405-20(lines 405 414) no Hoare annotation was computed. [2020-06-22 00:12:58,695 INFO L448 ceAbstractionStarter]: For program point L405-21(lines 405 414) no Hoare annotation was computed. [2020-06-22 00:12:58,695 INFO L448 ceAbstractionStarter]: For program point L405-23(lines 405 414) no Hoare annotation was computed. [2020-06-22 00:12:58,695 INFO L448 ceAbstractionStarter]: For program point L670-1(lines 659 727) no Hoare annotation was computed. [2020-06-22 00:12:58,696 INFO L448 ceAbstractionStarter]: For program point L405-24(lines 405 414) no Hoare annotation was computed. [2020-06-22 00:12:58,696 INFO L448 ceAbstractionStarter]: For program point L670-3(lines 659 727) no Hoare annotation was computed. [2020-06-22 00:12:58,696 INFO L448 ceAbstractionStarter]: For program point L405-26(lines 405 414) no Hoare annotation was computed. [2020-06-22 00:12:58,696 INFO L448 ceAbstractionStarter]: For program point L406(lines 406 411) no Hoare annotation was computed. [2020-06-22 00:12:58,696 INFO L448 ceAbstractionStarter]: For program point L406-1(lines 406 411) no Hoare annotation was computed. [2020-06-22 00:12:58,696 INFO L451 ceAbstractionStarter]: At program point L340(lines 328 342) the Hoare annotation is: true [2020-06-22 00:12:58,696 INFO L448 ceAbstractionStarter]: For program point L406-2(lines 406 411) no Hoare annotation was computed. [2020-06-22 00:12:58,696 INFO L451 ceAbstractionStarter]: At program point L340-1(lines 328 342) the Hoare annotation is: true [2020-06-22 00:12:58,697 INFO L448 ceAbstractionStarter]: For program point L406-3(lines 406 411) no Hoare annotation was computed. [2020-06-22 00:12:58,697 INFO L451 ceAbstractionStarter]: At program point L340-2(lines 328 342) the Hoare annotation is: true [2020-06-22 00:12:58,697 INFO L448 ceAbstractionStarter]: For program point L406-4(lines 406 411) no Hoare annotation was computed. [2020-06-22 00:12:58,697 INFO L451 ceAbstractionStarter]: At program point L340-3(lines 328 342) the Hoare annotation is: true [2020-06-22 00:12:58,697 INFO L448 ceAbstractionStarter]: For program point L406-5(lines 406 411) no Hoare annotation was computed. [2020-06-22 00:12:58,697 INFO L451 ceAbstractionStarter]: At program point L340-4(lines 328 342) the Hoare annotation is: true [2020-06-22 00:12:58,697 INFO L448 ceAbstractionStarter]: For program point L406-6(lines 406 411) no Hoare annotation was computed. [2020-06-22 00:12:58,697 INFO L451 ceAbstractionStarter]: At program point L175(lines 175 179) the Hoare annotation is: true [2020-06-22 00:12:58,698 INFO L451 ceAbstractionStarter]: At program point L340-5(lines 328 342) the Hoare annotation is: true [2020-06-22 00:12:58,698 INFO L448 ceAbstractionStarter]: For program point L406-7(lines 406 411) no Hoare annotation was computed. [2020-06-22 00:12:58,698 INFO L451 ceAbstractionStarter]: At program point L340-6(lines 328 342) the Hoare annotation is: true [2020-06-22 00:12:58,698 INFO L448 ceAbstractionStarter]: For program point L406-8(lines 406 411) no Hoare annotation was computed. [2020-06-22 00:12:58,698 INFO L451 ceAbstractionStarter]: At program point L340-7(lines 328 342) the Hoare annotation is: true [2020-06-22 00:12:58,698 INFO L451 ceAbstractionStarter]: At program point L340-8(lines 328 342) the Hoare annotation is: true [2020-06-22 00:12:58,698 INFO L448 ceAbstractionStarter]: For program point L638(lines 638 645) no Hoare annotation was computed. [2020-06-22 00:12:58,698 INFO L448 ceAbstractionStarter]: For program point L506(lines 506 526) no Hoare annotation was computed. [2020-06-22 00:12:58,699 INFO L448 ceAbstractionStarter]: For program point L506-1(lines 506 526) no Hoare annotation was computed. [2020-06-22 00:12:58,699 INFO L448 ceAbstractionStarter]: For program point L506-2(lines 506 526) no Hoare annotation was computed. [2020-06-22 00:12:58,699 INFO L448 ceAbstractionStarter]: For program point L242(lines 242 250) no Hoare annotation was computed. [2020-06-22 00:12:58,699 INFO L448 ceAbstractionStarter]: For program point L936-1(lines 895 963) no Hoare annotation was computed. [2020-06-22 00:12:58,699 INFO L448 ceAbstractionStarter]: For program point L738-1(lines 732 800) no Hoare annotation was computed. [2020-06-22 00:12:58,699 INFO L448 ceAbstractionStarter]: For program point L705-1(lines 659 727) no Hoare annotation was computed. [2020-06-22 00:12:58,699 INFO L448 ceAbstractionStarter]: For program point L738-3(lines 732 800) no Hoare annotation was computed. [2020-06-22 00:12:58,699 INFO L448 ceAbstractionStarter]: For program point L705-3(lines 659 727) no Hoare annotation was computed. [2020-06-22 00:12:58,700 INFO L451 ceAbstractionStarter]: At program point L210(lines 210 214) the Hoare annotation is: true [2020-06-22 00:12:58,700 INFO L451 ceAbstractionStarter]: At program point L12(lines 1 1069) the Hoare annotation is: true [2020-06-22 00:12:58,700 INFO L451 ceAbstractionStarter]: At program point L607(lines 541 649) the Hoare annotation is: true [2020-06-22 00:12:58,700 INFO L448 ceAbstractionStarter]: For program point L310(lines 310 319) no Hoare annotation was computed. [2020-06-22 00:12:58,700 INFO L448 ceAbstractionStarter]: For program point L277(lines 277 285) no Hoare annotation was computed. [2020-06-22 00:12:58,700 INFO L448 ceAbstractionStarter]: For program point L310-2(lines 310 319) no Hoare annotation was computed. [2020-06-22 00:12:58,700 INFO L448 ceAbstractionStarter]: For program point L310-3(lines 310 319) no Hoare annotation was computed. [2020-06-22 00:12:58,700 INFO L448 ceAbstractionStarter]: For program point L310-5(lines 310 319) no Hoare annotation was computed. [2020-06-22 00:12:58,701 INFO L448 ceAbstractionStarter]: For program point L310-6(lines 310 319) no Hoare annotation was computed. [2020-06-22 00:12:58,701 INFO L448 ceAbstractionStarter]: For program point L310-8(lines 310 319) no Hoare annotation was computed. [2020-06-22 00:12:58,701 INFO L448 ceAbstractionStarter]: For program point L310-9(lines 310 319) no Hoare annotation was computed. [2020-06-22 00:12:58,701 INFO L448 ceAbstractionStarter]: For program point L310-11(lines 310 319) no Hoare annotation was computed. [2020-06-22 00:12:58,701 INFO L448 ceAbstractionStarter]: For program point L310-12(lines 310 319) no Hoare annotation was computed. [2020-06-22 00:12:58,701 INFO L448 ceAbstractionStarter]: For program point L310-14(lines 310 319) no Hoare annotation was computed. [2020-06-22 00:12:58,701 INFO L448 ceAbstractionStarter]: For program point L839(lines 839 843) no Hoare annotation was computed. [2020-06-22 00:12:58,701 INFO L448 ceAbstractionStarter]: For program point L310-15(lines 310 319) no Hoare annotation was computed. [2020-06-22 00:12:58,702 INFO L448 ceAbstractionStarter]: For program point L839-2(lines 839 843) no Hoare annotation was computed. [2020-06-22 00:12:58,702 INFO L448 ceAbstractionStarter]: For program point L310-17(lines 310 319) no Hoare annotation was computed. [2020-06-22 00:12:58,702 INFO L448 ceAbstractionStarter]: For program point L773-1(lines 732 800) no Hoare annotation was computed. [2020-06-22 00:12:58,702 INFO L448 ceAbstractionStarter]: For program point L310-18(lines 310 319) no Hoare annotation was computed. [2020-06-22 00:12:58,702 INFO L448 ceAbstractionStarter]: For program point L839-3(lines 839 843) no Hoare annotation was computed. [2020-06-22 00:12:58,702 INFO L448 ceAbstractionStarter]: For program point L310-20(lines 310 319) no Hoare annotation was computed. [2020-06-22 00:12:58,702 INFO L448 ceAbstractionStarter]: For program point L839-5(lines 839 843) no Hoare annotation was computed. [2020-06-22 00:12:58,702 INFO L448 ceAbstractionStarter]: For program point L773-3(lines 732 800) no Hoare annotation was computed. [2020-06-22 00:12:58,702 INFO L448 ceAbstractionStarter]: For program point L310-21(lines 310 319) no Hoare annotation was computed. [2020-06-22 00:12:58,703 INFO L448 ceAbstractionStarter]: For program point L839-6(lines 839 843) no Hoare annotation was computed. [2020-06-22 00:12:58,703 INFO L448 ceAbstractionStarter]: For program point L310-23(lines 310 319) no Hoare annotation was computed. [2020-06-22 00:12:58,703 INFO L448 ceAbstractionStarter]: For program point L839-8(lines 839 843) no Hoare annotation was computed. [2020-06-22 00:12:58,703 INFO L448 ceAbstractionStarter]: For program point L839-9(lines 839 843) no Hoare annotation was computed. [2020-06-22 00:12:58,703 INFO L448 ceAbstractionStarter]: For program point L310-24(lines 310 319) no Hoare annotation was computed. [2020-06-22 00:12:58,703 INFO L448 ceAbstractionStarter]: For program point L839-11(lines 839 843) no Hoare annotation was computed. [2020-06-22 00:12:58,703 INFO L448 ceAbstractionStarter]: For program point L310-26(lines 310 319) no Hoare annotation was computed. [2020-06-22 00:12:58,703 INFO L448 ceAbstractionStarter]: For program point L476-1(lines 450 488) no Hoare annotation was computed. [2020-06-22 00:12:58,703 INFO L448 ceAbstractionStarter]: For program point L839-12(lines 839 843) no Hoare annotation was computed. [2020-06-22 00:12:58,704 INFO L448 ceAbstractionStarter]: For program point L839-14(lines 839 843) no Hoare annotation was computed. [2020-06-22 00:12:58,704 INFO L448 ceAbstractionStarter]: For program point L839-15(lines 839 843) no Hoare annotation was computed. [2020-06-22 00:12:58,704 INFO L448 ceAbstractionStarter]: For program point L311(lines 311 316) no Hoare annotation was computed. [2020-06-22 00:12:58,704 INFO L448 ceAbstractionStarter]: For program point L311-1(lines 311 316) no Hoare annotation was computed. [2020-06-22 00:12:58,704 INFO L448 ceAbstractionStarter]: For program point L839-17(lines 839 843) no Hoare annotation was computed. [2020-06-22 00:12:58,704 INFO L448 ceAbstractionStarter]: For program point L311-2(lines 311 316) no Hoare annotation was computed. [2020-06-22 00:12:58,704 INFO L451 ceAbstractionStarter]: At program point L245(lines 245 249) the Hoare annotation is: true [2020-06-22 00:12:58,704 INFO L448 ceAbstractionStarter]: For program point L839-18(lines 839 843) no Hoare annotation was computed. [2020-06-22 00:12:58,704 INFO L448 ceAbstractionStarter]: For program point L311-3(lines 311 316) no Hoare annotation was computed. [2020-06-22 00:12:58,705 INFO L448 ceAbstractionStarter]: For program point L311-4(lines 311 316) no Hoare annotation was computed. [2020-06-22 00:12:58,705 INFO L448 ceAbstractionStarter]: For program point L839-20(lines 839 843) no Hoare annotation was computed. [2020-06-22 00:12:58,705 INFO L448 ceAbstractionStarter]: For program point L311-5(lines 311 316) no Hoare annotation was computed. [2020-06-22 00:12:58,705 INFO L448 ceAbstractionStarter]: For program point L839-21(lines 839 843) no Hoare annotation was computed. [2020-06-22 00:12:58,705 INFO L448 ceAbstractionStarter]: For program point L311-6(lines 311 316) no Hoare annotation was computed. [2020-06-22 00:12:58,705 INFO L451 ceAbstractionStarter]: At program point L113-1(lines 101 131) the Hoare annotation is: true [2020-06-22 00:12:58,705 INFO L448 ceAbstractionStarter]: For program point L311-7(lines 311 316) no Hoare annotation was computed. [2020-06-22 00:12:58,705 INFO L448 ceAbstractionStarter]: For program point L839-23(lines 839 843) no Hoare annotation was computed. [2020-06-22 00:12:58,706 INFO L448 ceAbstractionStarter]: For program point L311-8(lines 311 316) no Hoare annotation was computed. [2020-06-22 00:12:58,706 INFO L448 ceAbstractionStarter]: For program point L839-24(lines 839 843) no Hoare annotation was computed. [2020-06-22 00:12:58,706 INFO L448 ceAbstractionStarter]: For program point L839-26(lines 839 843) no Hoare annotation was computed. [2020-06-22 00:12:58,706 INFO L448 ceAbstractionStarter]: For program point L906-1(lines 895 963) no Hoare annotation was computed. [2020-06-22 00:12:58,706 INFO L448 ceAbstractionStarter]: For program point L675-1(lines 659 727) no Hoare annotation was computed. [2020-06-22 00:12:58,706 INFO L448 ceAbstractionStarter]: For program point L675-3(lines 659 727) no Hoare annotation was computed. [2020-06-22 00:12:58,706 INFO L448 ceAbstractionStarter]: For program point L510(lines 510 525) no Hoare annotation was computed. [2020-06-22 00:12:58,706 INFO L448 ceAbstractionStarter]: For program point L510-1(lines 510 525) no Hoare annotation was computed. [2020-06-22 00:12:58,707 INFO L451 ceAbstractionStarter]: At program point L444(lines 451 455) the Hoare annotation is: true [2020-06-22 00:12:58,707 INFO L448 ceAbstractionStarter]: For program point L510-2(lines 510 525) no Hoare annotation was computed. [2020-06-22 00:12:58,707 INFO L451 ceAbstractionStarter]: At program point L378(lines 366 380) the Hoare annotation is: true [2020-06-22 00:12:58,707 INFO L451 ceAbstractionStarter]: At program point L378-1(lines 366 380) the Hoare annotation is: true [2020-06-22 00:12:58,707 INFO L451 ceAbstractionStarter]: At program point L378-2(lines 366 380) the Hoare annotation is: true [2020-06-22 00:12:58,707 INFO L451 ceAbstractionStarter]: At program point L378-3(lines 366 380) the Hoare annotation is: true [2020-06-22 00:12:58,707 INFO L451 ceAbstractionStarter]: At program point L378-4(lines 366 380) the Hoare annotation is: true [2020-06-22 00:12:58,707 INFO L451 ceAbstractionStarter]: At program point L378-5(lines 366 380) the Hoare annotation is: true [2020-06-22 00:12:58,708 INFO L451 ceAbstractionStarter]: At program point L378-6(lines 366 380) the Hoare annotation is: true [2020-06-22 00:12:58,708 INFO L451 ceAbstractionStarter]: At program point L378-7(lines 366 380) the Hoare annotation is: true [2020-06-22 00:12:58,708 INFO L451 ceAbstractionStarter]: At program point L378-8(lines 366 380) the Hoare annotation is: true [2020-06-22 00:12:58,708 INFO L448 ceAbstractionStarter]: For program point L610(lines 610 617) no Hoare annotation was computed. [2020-06-22 00:12:58,708 INFO L448 ceAbstractionStarter]: For program point L280(lines 280 284) no Hoare annotation was computed. [2020-06-22 00:12:58,708 INFO L451 ceAbstractionStarter]: At program point L148-1(lines 136 166) the Hoare annotation is: true [2020-06-22 00:12:58,708 INFO L448 ceAbstractionStarter]: For program point L941-1(lines 895 963) no Hoare annotation was computed. [2020-06-22 00:12:58,708 INFO L448 ceAbstractionStarter]: For program point L743-1(lines 732 800) no Hoare annotation was computed. [2020-06-22 00:12:58,709 INFO L448 ceAbstractionStarter]: For program point L710-1(lines 659 727) no Hoare annotation was computed. [2020-06-22 00:12:58,709 INFO L448 ceAbstractionStarter]: For program point L743-3(lines 732 800) no Hoare annotation was computed. [2020-06-22 00:12:58,709 INFO L448 ceAbstractionStarter]: For program point L710-3(lines 659 727) no Hoare annotation was computed. [2020-06-22 00:12:58,709 INFO L451 ceAbstractionStarter]: At program point L579(lines 541 649) the Hoare annotation is: true [2020-06-22 00:12:58,709 INFO L451 ceAbstractionStarter]: At program point L546(lines 546 550) the Hoare annotation is: true [2020-06-22 00:12:58,709 INFO L448 ceAbstractionStarter]: For program point L546-1(lines 541 649) no Hoare annotation was computed. [2020-06-22 00:12:58,709 INFO L448 ceAbstractionStarter]: For program point L348(lines 348 357) no Hoare annotation was computed. [2020-06-22 00:12:58,709 INFO L448 ceAbstractionStarter]: For program point L348-2(lines 348 357) no Hoare annotation was computed. [2020-06-22 00:12:58,710 INFO L448 ceAbstractionStarter]: For program point L348-3(lines 348 357) no Hoare annotation was computed. [2020-06-22 00:12:58,710 INFO L448 ceAbstractionStarter]: For program point L348-5(lines 348 357) no Hoare annotation was computed. [2020-06-22 00:12:58,710 INFO L451 ceAbstractionStarter]: At program point L183-1(lines 171 201) the Hoare annotation is: true [2020-06-22 00:12:58,710 INFO L448 ceAbstractionStarter]: For program point L348-6(lines 348 357) no Hoare annotation was computed. [2020-06-22 00:12:58,710 INFO L448 ceAbstractionStarter]: For program point L348-8(lines 348 357) no Hoare annotation was computed. [2020-06-22 00:12:58,710 INFO L448 ceAbstractionStarter]: For program point L348-9(lines 348 357) no Hoare annotation was computed. [2020-06-22 00:12:58,710 INFO L448 ceAbstractionStarter]: For program point L348-11(lines 348 357) no Hoare annotation was computed. [2020-06-22 00:12:58,710 INFO L448 ceAbstractionStarter]: For program point L348-12(lines 348 357) no Hoare annotation was computed. [2020-06-22 00:12:58,710 INFO L448 ceAbstractionStarter]: For program point L348-14(lines 348 357) no Hoare annotation was computed. [2020-06-22 00:12:58,711 INFO L448 ceAbstractionStarter]: For program point L348-15(lines 348 357) no Hoare annotation was computed. [2020-06-22 00:12:58,711 INFO L448 ceAbstractionStarter]: For program point L348-17(lines 348 357) no Hoare annotation was computed. [2020-06-22 00:12:58,711 INFO L448 ceAbstractionStarter]: For program point L348-18(lines 348 357) no Hoare annotation was computed. [2020-06-22 00:12:58,711 INFO L448 ceAbstractionStarter]: For program point L778-1(lines 732 800) no Hoare annotation was computed. [2020-06-22 00:12:58,711 INFO L448 ceAbstractionStarter]: For program point L348-20(lines 348 357) no Hoare annotation was computed. [2020-06-22 00:12:58,711 INFO L448 ceAbstractionStarter]: For program point L348-21(lines 348 357) no Hoare annotation was computed. [2020-06-22 00:12:58,711 INFO L448 ceAbstractionStarter]: For program point L778-3(lines 732 800) no Hoare annotation was computed. [2020-06-22 00:12:58,711 INFO L448 ceAbstractionStarter]: For program point L348-23(lines 348 357) no Hoare annotation was computed. [2020-06-22 00:12:58,711 INFO L448 ceAbstractionStarter]: For program point L348-24(lines 348 357) no Hoare annotation was computed. [2020-06-22 00:12:58,712 INFO L448 ceAbstractionStarter]: For program point L514(lines 514 524) no Hoare annotation was computed. [2020-06-22 00:12:58,712 INFO L448 ceAbstractionStarter]: For program point L348-26(lines 348 357) no Hoare annotation was computed. [2020-06-22 00:12:58,712 INFO L448 ceAbstractionStarter]: For program point L514-1(lines 514 524) no Hoare annotation was computed. [2020-06-22 00:12:58,712 INFO L451 ceAbstractionStarter]: At program point L481-1(lines 660 664) the Hoare annotation is: true [2020-06-22 00:12:58,712 INFO L448 ceAbstractionStarter]: For program point L514-2(lines 514 524) no Hoare annotation was computed. [2020-06-22 00:12:58,712 INFO L448 ceAbstractionStarter]: For program point L349(lines 349 354) no Hoare annotation was computed. [2020-06-22 00:12:58,712 INFO L448 ceAbstractionStarter]: For program point L349-1(lines 349 354) no Hoare annotation was computed. [2020-06-22 00:12:58,712 INFO L448 ceAbstractionStarter]: For program point L349-2(lines 349 354) no Hoare annotation was computed. [2020-06-22 00:12:58,712 INFO L448 ceAbstractionStarter]: For program point L349-3(lines 349 354) no Hoare annotation was computed. [2020-06-22 00:12:58,713 INFO L448 ceAbstractionStarter]: For program point L349-4(lines 349 354) no Hoare annotation was computed. [2020-06-22 00:12:58,713 INFO L448 ceAbstractionStarter]: For program point L349-5(lines 349 354) no Hoare annotation was computed. [2020-06-22 00:12:58,713 INFO L448 ceAbstractionStarter]: For program point L349-6(lines 349 354) no Hoare annotation was computed. [2020-06-22 00:12:58,713 INFO L448 ceAbstractionStarter]: For program point L349-7(lines 349 354) no Hoare annotation was computed. [2020-06-22 00:12:58,713 INFO L448 ceAbstractionStarter]: For program point L349-8(lines 349 354) no Hoare annotation was computed. [2020-06-22 00:12:58,713 INFO L448 ceAbstractionStarter]: For program point L911-1(lines 895 963) no Hoare annotation was computed. [2020-06-22 00:12:58,713 INFO L448 ceAbstractionStarter]: For program point L680-1(lines 659 727) no Hoare annotation was computed. [2020-06-22 00:12:58,713 INFO L448 ceAbstractionStarter]: For program point L680-3(lines 659 727) no Hoare annotation was computed. [2020-06-22 00:12:58,714 INFO L451 ceAbstractionStarter]: At program point L416(lines 404 418) the Hoare annotation is: true [2020-06-22 00:12:58,714 INFO L451 ceAbstractionStarter]: At program point L416-1(lines 404 418) the Hoare annotation is: true [2020-06-22 00:12:58,714 INFO L451 ceAbstractionStarter]: At program point L416-2(lines 404 418) the Hoare annotation is: true [2020-06-22 00:12:58,714 INFO L451 ceAbstractionStarter]: At program point ULTIMATE.startENTRY(line -1) the Hoare annotation is: true [2020-06-22 00:12:58,714 INFO L451 ceAbstractionStarter]: At program point L416-3(lines 404 418) the Hoare annotation is: true [2020-06-22 00:12:58,714 INFO L451 ceAbstractionStarter]: At program point L416-4(lines 404 418) the Hoare annotation is: true [2020-06-22 00:12:58,714 INFO L451 ceAbstractionStarter]: At program point L416-5(lines 404 418) the Hoare annotation is: true [2020-06-22 00:12:58,715 INFO L451 ceAbstractionStarter]: At program point L416-6(lines 404 418) the Hoare annotation is: true [2020-06-22 00:12:58,715 INFO L451 ceAbstractionStarter]: At program point L218-1(lines 206 236) the Hoare annotation is: true [2020-06-22 00:12:58,715 INFO L451 ceAbstractionStarter]: At program point L416-7(lines 404 418) the Hoare annotation is: true [2020-06-22 00:12:58,715 INFO L451 ceAbstractionStarter]: At program point L416-8(lines 404 418) the Hoare annotation is: true [2020-06-22 00:12:58,715 INFO L448 ceAbstractionStarter]: For program point L582(lines 582 589) no Hoare annotation was computed. [2020-06-22 00:12:58,715 INFO L448 ceAbstractionStarter]: For program point L946-1(lines 895 963) no Hoare annotation was computed. [2020-06-22 00:12:58,715 INFO L448 ceAbstractionStarter]: For program point L847(lines 847 851) no Hoare annotation was computed. [2020-06-22 00:12:58,715 INFO L448 ceAbstractionStarter]: For program point L847-2(lines 847 851) no Hoare annotation was computed. [2020-06-22 00:12:58,715 INFO L448 ceAbstractionStarter]: For program point L847-3(lines 847 851) no Hoare annotation was computed. [2020-06-22 00:12:58,716 INFO L448 ceAbstractionStarter]: For program point L748-1(lines 732 800) no Hoare annotation was computed. [2020-06-22 00:12:58,716 INFO L448 ceAbstractionStarter]: For program point L715-1(lines 659 727) no Hoare annotation was computed. [2020-06-22 00:12:58,716 INFO L448 ceAbstractionStarter]: For program point L847-5(lines 847 851) no Hoare annotation was computed. [2020-06-22 00:12:58,716 INFO L448 ceAbstractionStarter]: For program point L847-6(lines 847 851) no Hoare annotation was computed. [2020-06-22 00:12:58,716 INFO L448 ceAbstractionStarter]: For program point L748-3(lines 732 800) no Hoare annotation was computed. [2020-06-22 00:12:58,716 INFO L448 ceAbstractionStarter]: For program point L715-3(lines 659 727) no Hoare annotation was computed. [2020-06-22 00:12:58,716 INFO L448 ceAbstractionStarter]: For program point L847-8(lines 847 851) no Hoare annotation was computed. [2020-06-22 00:12:58,716 INFO L448 ceAbstractionStarter]: For program point L847-9(lines 847 851) no Hoare annotation was computed. [2020-06-22 00:12:58,716 INFO L448 ceAbstractionStarter]: For program point L847-11(lines 847 851) no Hoare annotation was computed. [2020-06-22 00:12:58,717 INFO L448 ceAbstractionStarter]: For program point L847-12(lines 847 851) no Hoare annotation was computed. [2020-06-22 00:12:58,717 INFO L448 ceAbstractionStarter]: For program point L451-1(lines 450 488) no Hoare annotation was computed. [2020-06-22 00:12:58,717 INFO L448 ceAbstractionStarter]: For program point L847-14(lines 847 851) no Hoare annotation was computed. [2020-06-22 00:12:58,717 INFO L448 ceAbstractionStarter]: For program point L847-15(lines 847 851) no Hoare annotation was computed. [2020-06-22 00:12:58,717 INFO L448 ceAbstractionStarter]: For program point L847-17(lines 847 851) no Hoare annotation was computed. [2020-06-22 00:12:58,717 INFO L448 ceAbstractionStarter]: For program point L847-18(lines 847 851) no Hoare annotation was computed. [2020-06-22 00:12:58,717 INFO L451 ceAbstractionStarter]: At program point L253-1(lines 241 271) the Hoare annotation is: true [2020-06-22 00:12:58,717 INFO L448 ceAbstractionStarter]: For program point L847-20(lines 847 851) no Hoare annotation was computed. [2020-06-22 00:12:58,717 INFO L448 ceAbstractionStarter]: For program point L847-21(lines 847 851) no Hoare annotation was computed. [2020-06-22 00:12:58,718 INFO L451 ceAbstractionStarter]: At program point L88(lines 60 96) the Hoare annotation is: true [2020-06-22 00:12:58,718 INFO L448 ceAbstractionStarter]: For program point L847-23(lines 847 851) no Hoare annotation was computed. [2020-06-22 00:12:58,718 INFO L448 ceAbstractionStarter]: For program point L847-24(lines 847 851) no Hoare annotation was computed. [2020-06-22 00:12:58,718 INFO L448 ceAbstractionStarter]: For program point L847-26(lines 847 851) no Hoare annotation was computed. [2020-06-22 00:12:58,718 INFO L448 ceAbstractionStarter]: For program point L815(lines 815 819) no Hoare annotation was computed. [2020-06-22 00:12:58,718 INFO L448 ceAbstractionStarter]: For program point L815-2(lines 815 819) no Hoare annotation was computed. [2020-06-22 00:12:58,718 INFO L448 ceAbstractionStarter]: For program point L815-3(lines 815 819) no Hoare annotation was computed. [2020-06-22 00:12:58,718 INFO L448 ceAbstractionStarter]: For program point L815-5(lines 815 819) no Hoare annotation was computed. [2020-06-22 00:12:58,718 INFO L448 ceAbstractionStarter]: For program point L815-6(lines 815 819) no Hoare annotation was computed. [2020-06-22 00:12:58,719 INFO L451 ceAbstractionStarter]: At program point L551(lines 541 649) the Hoare annotation is: true [2020-06-22 00:12:58,719 INFO L448 ceAbstractionStarter]: For program point L815-8(lines 815 819) no Hoare annotation was computed. [2020-06-22 00:12:58,719 INFO L448 ceAbstractionStarter]: For program point L518(lines 518 523) no Hoare annotation was computed. [2020-06-22 00:12:58,719 INFO L448 ceAbstractionStarter]: For program point L815-9(lines 815 819) no Hoare annotation was computed. [2020-06-22 00:12:58,719 INFO L448 ceAbstractionStarter]: For program point L518-1(lines 518 523) no Hoare annotation was computed. [2020-06-22 00:12:58,719 INFO L448 ceAbstractionStarter]: For program point L815-11(lines 815 819) no Hoare annotation was computed. [2020-06-22 00:12:58,719 INFO L448 ceAbstractionStarter]: For program point L518-2(lines 518 523) no Hoare annotation was computed. [2020-06-22 00:12:58,719 INFO L448 ceAbstractionStarter]: For program point L815-12(lines 815 819) no Hoare annotation was computed. [2020-06-22 00:12:58,719 INFO L448 ceAbstractionStarter]: For program point L386(lines 386 395) no Hoare annotation was computed. [2020-06-22 00:12:58,720 INFO L448 ceAbstractionStarter]: For program point L815-14(lines 815 819) no Hoare annotation was computed. [2020-06-22 00:12:58,720 INFO L448 ceAbstractionStarter]: For program point L386-2(lines 386 395) no Hoare annotation was computed. [2020-06-22 00:12:58,720 INFO L448 ceAbstractionStarter]: For program point L815-15(lines 815 819) no Hoare annotation was computed. [2020-06-22 00:12:58,720 INFO L448 ceAbstractionStarter]: For program point L386-3(lines 386 395) no Hoare annotation was computed. [2020-06-22 00:12:58,720 INFO L448 ceAbstractionStarter]: For program point L815-17(lines 815 819) no Hoare annotation was computed. [2020-06-22 00:12:58,720 INFO L448 ceAbstractionStarter]: For program point L815-18(lines 815 819) no Hoare annotation was computed. [2020-06-22 00:12:58,720 INFO L448 ceAbstractionStarter]: For program point L386-5(lines 386 395) no Hoare annotation was computed. [2020-06-22 00:12:58,720 INFO L448 ceAbstractionStarter]: For program point L386-6(lines 386 395) no Hoare annotation was computed. [2020-06-22 00:12:58,721 INFO L448 ceAbstractionStarter]: For program point L815-20(lines 815 819) no Hoare annotation was computed. [2020-06-22 00:12:58,721 INFO L448 ceAbstractionStarter]: For program point L815-21(lines 815 819) no Hoare annotation was computed. [2020-06-22 00:12:58,721 INFO L448 ceAbstractionStarter]: For program point L386-8(lines 386 395) no Hoare annotation was computed. [2020-06-22 00:12:58,721 INFO L448 ceAbstractionStarter]: For program point L386-9(lines 386 395) no Hoare annotation was computed. [2020-06-22 00:12:58,721 INFO L448 ceAbstractionStarter]: For program point L815-23(lines 815 819) no Hoare annotation was computed. [2020-06-22 00:12:58,721 INFO L448 ceAbstractionStarter]: For program point L386-11(lines 386 395) no Hoare annotation was computed. [2020-06-22 00:12:58,721 INFO L448 ceAbstractionStarter]: For program point L815-24(lines 815 819) no Hoare annotation was computed. [2020-06-22 00:12:58,721 INFO L448 ceAbstractionStarter]: For program point L386-12(lines 386 395) no Hoare annotation was computed. [2020-06-22 00:12:58,722 INFO L451 ceAbstractionStarter]: At program point L1014-1(lines 729 1051) the Hoare annotation is: true [2020-06-22 00:12:58,722 INFO L448 ceAbstractionStarter]: For program point L815-26(lines 815 819) no Hoare annotation was computed. [2020-06-22 00:12:58,722 INFO L448 ceAbstractionStarter]: For program point L386-14(lines 386 395) no Hoare annotation was computed. [2020-06-22 00:12:58,722 INFO L448 ceAbstractionStarter]: For program point L386-15(lines 386 395) no Hoare annotation was computed. [2020-06-22 00:12:58,722 INFO L448 ceAbstractionStarter]: For program point L386-17(lines 386 395) no Hoare annotation was computed. [2020-06-22 00:12:58,722 INFO L448 ceAbstractionStarter]: For program point L386-18(lines 386 395) no Hoare annotation was computed. [2020-06-22 00:12:58,722 INFO L448 ceAbstractionStarter]: For program point L783-1(lines 732 800) no Hoare annotation was computed. [2020-06-22 00:12:58,722 INFO L448 ceAbstractionStarter]: For program point L386-20(lines 386 395) no Hoare annotation was computed. [2020-06-22 00:12:58,723 INFO L448 ceAbstractionStarter]: For program point L386-21(lines 386 395) no Hoare annotation was computed. [2020-06-22 00:12:58,723 INFO L448 ceAbstractionStarter]: For program point L783-3(lines 732 800) no Hoare annotation was computed. [2020-06-22 00:12:58,723 INFO L448 ceAbstractionStarter]: For program point L386-23(lines 386 395) no Hoare annotation was computed. [2020-06-22 00:12:58,723 INFO L448 ceAbstractionStarter]: For program point L386-24(lines 386 395) no Hoare annotation was computed. [2020-06-22 00:12:58,723 INFO L448 ceAbstractionStarter]: For program point L386-26(lines 386 395) no Hoare annotation was computed. [2020-06-22 00:12:58,723 INFO L448 ceAbstractionStarter]: For program point L387(lines 387 392) no Hoare annotation was computed. [2020-06-22 00:12:58,723 INFO L448 ceAbstractionStarter]: For program point L387-1(lines 387 392) no Hoare annotation was computed. [2020-06-22 00:12:58,723 INFO L451 ceAbstractionStarter]: At program point L321(lines 309 323) the Hoare annotation is: true [2020-06-22 00:12:58,723 INFO L448 ceAbstractionStarter]: For program point L387-2(lines 387 392) no Hoare annotation was computed. [2020-06-22 00:12:58,724 INFO L451 ceAbstractionStarter]: At program point L321-1(lines 309 323) the Hoare annotation is: true [2020-06-22 00:12:58,724 INFO L448 ceAbstractionStarter]: For program point L387-3(lines 387 392) no Hoare annotation was computed. [2020-06-22 00:12:58,724 INFO L451 ceAbstractionStarter]: At program point L321-2(lines 309 323) the Hoare annotation is: true [2020-06-22 00:12:58,724 INFO L448 ceAbstractionStarter]: For program point L387-4(lines 387 392) no Hoare annotation was computed. [2020-06-22 00:12:58,724 INFO L451 ceAbstractionStarter]: At program point L321-3(lines 309 323) the Hoare annotation is: true [2020-06-22 00:12:58,724 INFO L448 ceAbstractionStarter]: For program point L387-5(lines 387 392) no Hoare annotation was computed. [2020-06-22 00:12:58,724 INFO L451 ceAbstractionStarter]: At program point L321-4(lines 309 323) the Hoare annotation is: true [2020-06-22 00:12:58,724 INFO L448 ceAbstractionStarter]: For program point L387-6(lines 387 392) no Hoare annotation was computed. [2020-06-22 00:12:58,724 INFO L451 ceAbstractionStarter]: At program point L321-5(lines 309 323) the Hoare annotation is: true [2020-06-22 00:12:58,725 INFO L448 ceAbstractionStarter]: For program point L387-7(lines 387 392) no Hoare annotation was computed. [2020-06-22 00:12:58,725 INFO L451 ceAbstractionStarter]: At program point L321-6(lines 309 323) the Hoare annotation is: true [2020-06-22 00:12:58,725 INFO L448 ceAbstractionStarter]: For program point L387-8(lines 387 392) no Hoare annotation was computed. [2020-06-22 00:12:58,725 INFO L451 ceAbstractionStarter]: At program point L321-7(lines 309 323) the Hoare annotation is: true [2020-06-22 00:12:58,725 INFO L451 ceAbstractionStarter]: At program point L321-8(lines 309 323) the Hoare annotation is: true [2020-06-22 00:12:58,725 INFO L448 ceAbstractionStarter]: For program point L916-1(lines 895 963) no Hoare annotation was computed. [2020-06-22 00:12:58,725 INFO L448 ceAbstractionStarter]: For program point L685-1(lines 659 727) no Hoare annotation was computed. [2020-06-22 00:12:58,725 INFO L448 ceAbstractionStarter]: For program point L685-3(lines 659 727) no Hoare annotation was computed. [2020-06-22 00:12:58,726 INFO L448 ceAbstractionStarter]: For program point L554(lines 554 561) no Hoare annotation was computed. [2020-06-22 00:12:58,726 INFO L448 ceAbstractionStarter]: For program point L951-1(lines 895 963) no Hoare annotation was computed. [2020-06-22 00:12:58,726 INFO L448 ceAbstractionStarter]: For program point L753-1(lines 732 800) no Hoare annotation was computed. [2020-06-22 00:12:58,726 INFO L451 ceAbstractionStarter]: At program point L720-1(lines 656 728) the Hoare annotation is: true [2020-06-22 00:12:58,726 INFO L448 ceAbstractionStarter]: For program point L753-3(lines 732 800) no Hoare annotation was computed. [2020-06-22 00:12:58,726 INFO L451 ceAbstractionStarter]: At program point L621(lines 541 649) the Hoare annotation is: true [2020-06-22 00:12:58,726 INFO L451 ceAbstractionStarter]: At program point L720-3(lines 656 728) the Hoare annotation is: true [2020-06-22 00:12:58,726 INFO L448 ceAbstractionStarter]: For program point L456-1(lines 450 488) no Hoare annotation was computed. [2020-06-22 00:12:58,726 INFO L448 ceAbstractionStarter]: For program point L424(lines 424 433) no Hoare annotation was computed. [2020-06-22 00:12:58,727 INFO L448 ceAbstractionStarter]: For program point L424-2(lines 424 433) no Hoare annotation was computed. [2020-06-22 00:12:58,727 INFO L448 ceAbstractionStarter]: For program point L424-3(lines 424 433) no Hoare annotation was computed. [2020-06-22 00:12:58,727 INFO L448 ceAbstractionStarter]: For program point L424-5(lines 424 433) no Hoare annotation was computed. [2020-06-22 00:12:58,727 INFO L448 ceAbstractionStarter]: For program point L424-6(lines 424 433) no Hoare annotation was computed. [2020-06-22 00:12:58,727 INFO L448 ceAbstractionStarter]: For program point L424-8(lines 424 433) no Hoare annotation was computed. [2020-06-22 00:12:58,727 INFO L448 ceAbstractionStarter]: For program point L424-9(lines 424 433) no Hoare annotation was computed. [2020-06-22 00:12:58,727 INFO L448 ceAbstractionStarter]: For program point L61(lines 61 69) no Hoare annotation was computed. [2020-06-22 00:12:58,727 INFO L448 ceAbstractionStarter]: For program point L424-11(lines 424 433) no Hoare annotation was computed. [2020-06-22 00:12:58,727 INFO L448 ceAbstractionStarter]: For program point L424-12(lines 424 433) no Hoare annotation was computed. [2020-06-22 00:12:58,728 INFO L448 ceAbstractionStarter]: For program point L424-14(lines 424 433) no Hoare annotation was computed. [2020-06-22 00:12:58,728 INFO L448 ceAbstractionStarter]: For program point L424-15(lines 424 433) no Hoare annotation was computed. [2020-06-22 00:12:58,728 INFO L448 ceAbstractionStarter]: For program point L424-17(lines 424 433) no Hoare annotation was computed. [2020-06-22 00:12:58,728 INFO L448 ceAbstractionStarter]: For program point L424-18(lines 424 433) no Hoare annotation was computed. [2020-06-22 00:12:58,728 INFO L448 ceAbstractionStarter]: For program point L424-20(lines 424 433) no Hoare annotation was computed. [2020-06-22 00:12:58,728 INFO L448 ceAbstractionStarter]: For program point L788-1(lines 732 800) no Hoare annotation was computed. [2020-06-22 00:12:58,728 INFO L448 ceAbstractionStarter]: For program point L424-21(lines 424 433) no Hoare annotation was computed. [2020-06-22 00:12:58,728 INFO L448 ceAbstractionStarter]: For program point L424-23(lines 424 433) no Hoare annotation was computed. [2020-06-22 00:12:58,728 INFO L448 ceAbstractionStarter]: For program point L788-3(lines 732 800) no Hoare annotation was computed. [2020-06-22 00:12:58,729 INFO L448 ceAbstractionStarter]: For program point L424-24(lines 424 433) no Hoare annotation was computed. [2020-06-22 00:12:58,729 INFO L448 ceAbstractionStarter]: For program point L424-26(lines 424 433) no Hoare annotation was computed. [2020-06-22 00:12:58,729 INFO L448 ceAbstractionStarter]: For program point L425(lines 425 430) no Hoare annotation was computed. [2020-06-22 00:12:58,729 INFO L448 ceAbstractionStarter]: For program point L425-1(lines 425 430) no Hoare annotation was computed. [2020-06-22 00:12:58,729 INFO L451 ceAbstractionStarter]: At program point L359(lines 347 361) the Hoare annotation is: true [2020-06-22 00:12:58,729 INFO L448 ceAbstractionStarter]: For program point L425-2(lines 425 430) no Hoare annotation was computed. [2020-06-22 00:12:58,729 INFO L451 ceAbstractionStarter]: At program point L359-1(lines 347 361) the Hoare annotation is: true [2020-06-22 00:12:58,729 INFO L448 ceAbstractionStarter]: For program point L425-3(lines 425 430) no Hoare annotation was computed. [2020-06-22 00:12:58,730 INFO L451 ceAbstractionStarter]: At program point L359-2(lines 347 361) the Hoare annotation is: true [2020-06-22 00:12:58,730 INFO L448 ceAbstractionStarter]: For program point L425-4(lines 425 430) no Hoare annotation was computed. [2020-06-22 00:12:58,730 INFO L451 ceAbstractionStarter]: At program point L359-3(lines 347 361) the Hoare annotation is: true [2020-06-22 00:12:58,730 INFO L448 ceAbstractionStarter]: For program point L425-5(lines 425 430) no Hoare annotation was computed. [2020-06-22 00:12:58,730 INFO L451 ceAbstractionStarter]: At program point L359-4(lines 347 361) the Hoare annotation is: true [2020-06-22 00:12:58,730 INFO L448 ceAbstractionStarter]: For program point L425-6(lines 425 430) no Hoare annotation was computed. [2020-06-22 00:12:58,730 INFO L451 ceAbstractionStarter]: At program point L359-5(lines 347 361) the Hoare annotation is: true [2020-06-22 00:12:58,730 INFO L448 ceAbstractionStarter]: For program point L425-7(lines 425 430) no Hoare annotation was computed. [2020-06-22 00:12:58,730 INFO L451 ceAbstractionStarter]: At program point L359-6(lines 347 361) the Hoare annotation is: true [2020-06-22 00:12:58,731 INFO L448 ceAbstractionStarter]: For program point L425-8(lines 425 430) no Hoare annotation was computed. [2020-06-22 00:12:58,731 INFO L451 ceAbstractionStarter]: At program point L359-7(lines 347 361) the Hoare annotation is: true [2020-06-22 00:12:58,731 INFO L451 ceAbstractionStarter]: At program point L359-8(lines 347 361) the Hoare annotation is: true [2020-06-22 00:12:58,731 INFO L448 ceAbstractionStarter]: For program point L921-1(lines 895 963) no Hoare annotation was computed. [2020-06-22 00:12:58,731 INFO L448 ceAbstractionStarter]: For program point L855(lines 855 859) no Hoare annotation was computed. [2020-06-22 00:12:58,731 INFO L448 ceAbstractionStarter]: For program point L855-2(lines 855 859) no Hoare annotation was computed. [2020-06-22 00:12:58,731 INFO L448 ceAbstractionStarter]: For program point L855-3(lines 855 859) no Hoare annotation was computed. [2020-06-22 00:12:58,731 INFO L448 ceAbstractionStarter]: For program point L855-5(lines 855 859) no Hoare annotation was computed. [2020-06-22 00:12:58,731 INFO L448 ceAbstractionStarter]: For program point L690-1(lines 659 727) no Hoare annotation was computed. [2020-06-22 00:12:58,732 INFO L448 ceAbstractionStarter]: For program point L855-6(lines 855 859) no Hoare annotation was computed. [2020-06-22 00:12:58,732 INFO L448 ceAbstractionStarter]: For program point L624(lines 624 631) no Hoare annotation was computed. [2020-06-22 00:12:58,732 INFO L448 ceAbstractionStarter]: For program point L690-3(lines 659 727) no Hoare annotation was computed. [2020-06-22 00:12:58,732 INFO L448 ceAbstractionStarter]: For program point L855-8(lines 855 859) no Hoare annotation was computed. [2020-06-22 00:12:58,732 INFO L448 ceAbstractionStarter]: For program point L855-9(lines 855 859) no Hoare annotation was computed. [2020-06-22 00:12:58,732 INFO L448 ceAbstractionStarter]: For program point L855-11(lines 855 859) no Hoare annotation was computed. [2020-06-22 00:12:58,732 INFO L448 ceAbstractionStarter]: For program point L855-12(lines 855 859) no Hoare annotation was computed. [2020-06-22 00:12:58,732 INFO L448 ceAbstractionStarter]: For program point L855-14(lines 855 859) no Hoare annotation was computed. [2020-06-22 00:12:58,732 INFO L448 ceAbstractionStarter]: For program point L855-15(lines 855 859) no Hoare annotation was computed. [2020-06-22 00:12:58,732 INFO L448 ceAbstractionStarter]: For program point L855-17(lines 855 859) no Hoare annotation was computed. [2020-06-22 00:12:58,733 INFO L448 ceAbstractionStarter]: For program point L855-18(lines 855 859) no Hoare annotation was computed. [2020-06-22 00:12:58,733 INFO L448 ceAbstractionStarter]: For program point L855-20(lines 855 859) no Hoare annotation was computed. [2020-06-22 00:12:58,733 INFO L448 ceAbstractionStarter]: For program point L855-21(lines 855 859) no Hoare annotation was computed. [2020-06-22 00:12:58,733 INFO L448 ceAbstractionStarter]: For program point L855-23(lines 855 859) no Hoare annotation was computed. [2020-06-22 00:12:58,733 INFO L448 ceAbstractionStarter]: For program point L855-24(lines 855 859) no Hoare annotation was computed. [2020-06-22 00:12:58,733 INFO L448 ceAbstractionStarter]: For program point L855-26(lines 855 859) no Hoare annotation was computed. [2020-06-22 00:12:58,733 INFO L448 ceAbstractionStarter]: For program point L988(lines 988 993) no Hoare annotation was computed. [2020-06-22 00:12:58,733 INFO L448 ceAbstractionStarter]: For program point L823(lines 823 827) no Hoare annotation was computed. [2020-06-22 00:12:58,733 INFO L448 ceAbstractionStarter]: For program point L823-2(lines 823 827) no Hoare annotation was computed. [2020-06-22 00:12:58,734 INFO L448 ceAbstractionStarter]: For program point L823-3(lines 823 827) no Hoare annotation was computed. [2020-06-22 00:12:58,734 INFO L448 ceAbstractionStarter]: For program point L823-5(lines 823 827) no Hoare annotation was computed. [2020-06-22 00:12:58,734 INFO L448 ceAbstractionStarter]: For program point L823-6(lines 823 827) no Hoare annotation was computed. [2020-06-22 00:12:58,734 INFO L448 ceAbstractionStarter]: For program point L823-8(lines 823 827) no Hoare annotation was computed. [2020-06-22 00:12:58,734 INFO L448 ceAbstractionStarter]: For program point L823-9(lines 823 827) no Hoare annotation was computed. [2020-06-22 00:12:58,734 INFO L448 ceAbstractionStarter]: For program point L823-11(lines 823 827) no Hoare annotation was computed. [2020-06-22 00:12:58,734 INFO L448 ceAbstractionStarter]: For program point L823-12(lines 823 827) no Hoare annotation was computed. [2020-06-22 00:12:58,734 INFO L448 ceAbstractionStarter]: For program point L823-14(lines 823 827) no Hoare annotation was computed. [2020-06-22 00:12:58,734 INFO L448 ceAbstractionStarter]: For program point L823-15(lines 823 827) no Hoare annotation was computed. [2020-06-22 00:12:58,734 INFO L448 ceAbstractionStarter]: For program point L823-17(lines 823 827) no Hoare annotation was computed. [2020-06-22 00:12:58,735 INFO L448 ceAbstractionStarter]: For program point L823-18(lines 823 827) no Hoare annotation was computed. [2020-06-22 00:12:58,735 INFO L448 ceAbstractionStarter]: For program point L823-20(lines 823 827) no Hoare annotation was computed. [2020-06-22 00:12:58,735 INFO L448 ceAbstractionStarter]: For program point L823-21(lines 823 827) no Hoare annotation was computed. [2020-06-22 00:12:58,735 INFO L448 ceAbstractionStarter]: For program point L64(lines 64 68) no Hoare annotation was computed. [2020-06-22 00:12:58,735 INFO L448 ceAbstractionStarter]: For program point L823-23(lines 823 827) no Hoare annotation was computed. [2020-06-22 00:12:58,735 INFO L448 ceAbstractionStarter]: For program point L823-24(lines 823 827) no Hoare annotation was computed. [2020-06-22 00:12:58,735 INFO L448 ceAbstractionStarter]: For program point L823-26(lines 823 827) no Hoare annotation was computed. [2020-06-22 00:12:58,735 INFO L448 ceAbstractionStarter]: For program point L758-1(lines 732 800) no Hoare annotation was computed. [2020-06-22 00:12:58,735 INFO L448 ceAbstractionStarter]: For program point L758-3(lines 732 800) no Hoare annotation was computed. [2020-06-22 00:12:58,736 INFO L451 ceAbstractionStarter]: At program point L593(lines 541 649) the Hoare annotation is: true [2020-06-22 00:12:58,736 INFO L448 ceAbstractionStarter]: For program point L494(lines 494 529) no Hoare annotation was computed. [2020-06-22 00:12:58,736 INFO L448 ceAbstractionStarter]: For program point L494-1(lines 494 529) no Hoare annotation was computed. [2020-06-22 00:12:58,736 INFO L448 ceAbstractionStarter]: For program point L461-1(lines 450 488) no Hoare annotation was computed. [2020-06-22 00:12:58,736 INFO L448 ceAbstractionStarter]: For program point L494-2(lines 494 529) no Hoare annotation was computed. [2020-06-22 00:12:58,736 INFO L448 ceAbstractionStarter]: For program point L329(lines 329 338) no Hoare annotation was computed. [2020-06-22 00:12:58,736 INFO L448 ceAbstractionStarter]: For program point L329-2(lines 329 338) no Hoare annotation was computed. [2020-06-22 00:12:58,736 INFO L448 ceAbstractionStarter]: For program point L329-3(lines 329 338) no Hoare annotation was computed. [2020-06-22 00:12:58,736 INFO L448 ceAbstractionStarter]: For program point L329-5(lines 329 338) no Hoare annotation was computed. [2020-06-22 00:12:58,737 INFO L448 ceAbstractionStarter]: For program point L329-6(lines 329 338) no Hoare annotation was computed. [2020-06-22 00:12:58,737 INFO L451 ceAbstractionStarter]: At program point L65(lines 60 96) the Hoare annotation is: true [2020-06-22 00:12:58,737 INFO L448 ceAbstractionStarter]: For program point L329-8(lines 329 338) no Hoare annotation was computed. [2020-06-22 00:12:58,737 INFO L448 ceAbstractionStarter]: For program point L329-9(lines 329 338) no Hoare annotation was computed. [2020-06-22 00:12:58,737 INFO L448 ceAbstractionStarter]: For program point L329-11(lines 329 338) no Hoare annotation was computed. [2020-06-22 00:12:58,737 INFO L448 ceAbstractionStarter]: For program point L329-12(lines 329 338) no Hoare annotation was computed. [2020-06-22 00:12:58,737 INFO L448 ceAbstractionStarter]: For program point L329-14(lines 329 338) no Hoare annotation was computed. [2020-06-22 00:12:58,737 INFO L448 ceAbstractionStarter]: For program point L329-15(lines 329 338) no Hoare annotation was computed. [2020-06-22 00:12:58,737 INFO L448 ceAbstractionStarter]: For program point L329-17(lines 329 338) no Hoare annotation was computed. [2020-06-22 00:12:58,738 INFO L448 ceAbstractionStarter]: For program point L329-18(lines 329 338) no Hoare annotation was computed. [2020-06-22 00:12:58,738 INFO L448 ceAbstractionStarter]: For program point L329-20(lines 329 338) no Hoare annotation was computed. [2020-06-22 00:12:58,738 INFO L448 ceAbstractionStarter]: For program point L329-21(lines 329 338) no Hoare annotation was computed. [2020-06-22 00:12:58,738 INFO L448 ceAbstractionStarter]: For program point L660-1(lines 659 727) no Hoare annotation was computed. [2020-06-22 00:12:58,738 INFO L448 ceAbstractionStarter]: For program point L660-2(lines 660 664) no Hoare annotation was computed. [2020-06-22 00:12:58,738 INFO L448 ceAbstractionStarter]: For program point L329-23(lines 329 338) no Hoare annotation was computed. [2020-06-22 00:12:58,738 INFO L448 ceAbstractionStarter]: For program point L329-24(lines 329 338) no Hoare annotation was computed. [2020-06-22 00:12:58,738 INFO L448 ceAbstractionStarter]: For program point L660-4(lines 659 727) no Hoare annotation was computed. [2020-06-22 00:12:58,738 INFO L448 ceAbstractionStarter]: For program point L329-26(lines 329 338) no Hoare annotation was computed. [2020-06-22 00:12:58,738 INFO L448 ceAbstractionStarter]: For program point L330(lines 330 335) no Hoare annotation was computed. [2020-06-22 00:12:58,739 INFO L448 ceAbstractionStarter]: For program point L330-1(lines 330 335) no Hoare annotation was computed. [2020-06-22 00:12:58,739 INFO L448 ceAbstractionStarter]: For program point L330-2(lines 330 335) no Hoare annotation was computed. [2020-06-22 00:12:58,739 INFO L448 ceAbstractionStarter]: For program point L330-3(lines 330 335) no Hoare annotation was computed. [2020-06-22 00:12:58,739 INFO L448 ceAbstractionStarter]: For program point L330-4(lines 330 335) no Hoare annotation was computed. [2020-06-22 00:12:58,739 INFO L448 ceAbstractionStarter]: For program point L330-5(lines 330 335) no Hoare annotation was computed. [2020-06-22 00:12:58,739 INFO L448 ceAbstractionStarter]: For program point L330-6(lines 330 335) no Hoare annotation was computed. [2020-06-22 00:12:58,739 INFO L448 ceAbstractionStarter]: For program point L330-7(lines 330 335) no Hoare annotation was computed. [2020-06-22 00:12:58,739 INFO L448 ceAbstractionStarter]: For program point L330-8(lines 330 335) no Hoare annotation was computed. [2020-06-22 00:12:58,739 INFO L451 ceAbstractionStarter]: At program point L793-3(lines 729 801) the Hoare annotation is: true [2020-06-22 00:12:58,740 INFO L451 ceAbstractionStarter]: At program point L397(lines 385 399) the Hoare annotation is: true [2020-06-22 00:12:58,740 INFO L451 ceAbstractionStarter]: At program point L397-1(lines 385 399) the Hoare annotation is: true [2020-06-22 00:12:58,740 INFO L451 ceAbstractionStarter]: At program point L397-2(lines 385 399) the Hoare annotation is: true [2020-06-22 00:12:58,740 INFO L451 ceAbstractionStarter]: At program point L397-3(lines 385 399) the Hoare annotation is: true [2020-06-22 00:12:58,740 INFO L451 ceAbstractionStarter]: At program point L397-4(lines 385 399) the Hoare annotation is: true [2020-06-22 00:12:58,740 INFO L451 ceAbstractionStarter]: At program point L397-5(lines 385 399) the Hoare annotation is: true [2020-06-22 00:12:58,740 INFO L451 ceAbstractionStarter]: At program point L397-6(lines 385 399) the Hoare annotation is: true [2020-06-22 00:12:58,740 INFO L451 ceAbstractionStarter]: At program point L397-7(lines 385 399) the Hoare annotation is: true [2020-06-22 00:12:58,740 INFO L451 ceAbstractionStarter]: At program point L397-8(lines 385 399) the Hoare annotation is: true [2020-06-22 00:12:58,741 INFO L448 ceAbstractionStarter]: For program point L926-1(lines 895 963) no Hoare annotation was computed. [2020-06-22 00:12:58,741 INFO L448 ceAbstractionStarter]: For program point L695-1(lines 659 727) no Hoare annotation was computed. [2020-06-22 00:12:58,741 INFO L448 ceAbstractionStarter]: For program point L596(lines 596 603) no Hoare annotation was computed. [2020-06-22 00:12:58,741 INFO L448 ceAbstractionStarter]: For program point L695-3(lines 659 727) no Hoare annotation was computed. [2020-06-22 00:12:58,753 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 22.06 12:12:58 BasicIcfg [2020-06-22 00:12:58,754 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2020-06-22 00:12:58,754 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2020-06-22 00:12:58,754 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2020-06-22 00:12:58,758 INFO L276 PluginConnector]: BuchiAutomizer initialized [2020-06-22 00:12:58,758 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2020-06-22 00:12:58,759 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 22.06 12:12:56" (1/5) ... [2020-06-22 00:12:58,759 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1e882726 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 22.06 12:12:58, skipping insertion in model container [2020-06-22 00:12:58,759 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2020-06-22 00:12:58,759 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.06 12:12:56" (2/5) ... [2020-06-22 00:12:58,760 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1e882726 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 22.06 12:12:58, skipping insertion in model container [2020-06-22 00:12:58,760 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2020-06-22 00:12:58,760 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 22.06 12:12:57" (3/5) ... [2020-06-22 00:12:58,760 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1e882726 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 22.06 12:12:58, skipping insertion in model container [2020-06-22 00:12:58,760 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2020-06-22 00:12:58,761 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.blockencoding CFG 22.06 12:12:58" (4/5) ... [2020-06-22 00:12:58,761 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1e882726 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 22.06 12:12:58, skipping insertion in model container [2020-06-22 00:12:58,761 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2020-06-22 00:12:58,761 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 22.06 12:12:58" (5/5) ... [2020-06-22 00:12:58,762 INFO L375 chiAutomizerObserver]: Analyzing ICFG theBenchmark.c_BEv2 [2020-06-22 00:12:58,786 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2020-06-22 00:12:58,786 INFO L374 BuchiCegarLoop]: Interprodecural is true [2020-06-22 00:12:58,786 INFO L375 BuchiCegarLoop]: Hoare is true [2020-06-22 00:12:58,786 INFO L376 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2020-06-22 00:12:58,786 INFO L377 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2020-06-22 00:12:58,786 INFO L378 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2020-06-22 00:12:58,786 INFO L379 BuchiCegarLoop]: Difference is false [2020-06-22 00:12:58,786 INFO L380 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2020-06-22 00:12:58,787 INFO L383 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2020-06-22 00:12:58,795 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 518 states. [2020-06-22 00:12:58,835 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 442 [2020-06-22 00:12:58,836 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-06-22 00:12:58,836 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-06-22 00:12:58,848 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:12:58,848 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:12:58,848 INFO L442 BuchiCegarLoop]: ======== Iteration 1============ [2020-06-22 00:12:58,848 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 518 states. [2020-06-22 00:12:58,857 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 442 [2020-06-22 00:12:58,857 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-06-22 00:12:58,857 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-06-22 00:12:58,861 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:12:58,862 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:12:58,870 INFO L794 eck$LassoCheckResult]: Stem: 350#ULTIMATE.startENTRYtrue [4266] ULTIMATE.startENTRY-->L444: Formula: (and (= 1 v_~t6_i~0_7) (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~M_E~0_37 2) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 0 v_~t6_pc~0_26) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_6~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= v_~T6_E~0_18 2) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~t6_st~0_24) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t6_pc~0=v_~t6_pc~0_26, ~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~T6_E~0=v_~T6_E~0_18, ~M_E~0=v_~M_E~0_37, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ~T4_E~0=v_~T4_E~0_18, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_4|, ~t6_i~0=v_~t6_i~0_7, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ULTIMATE.start_main_~__retres1~8=v_ULTIMATE.start_main_~__retres1~8_6, ~T2_E~0=v_~T2_E~0_18, ~t6_st~0=v_~t6_st~0_24, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_6~0=v_~E_6~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t6_pc~0, ~t5_i~0, ~t1_pc~0, ~t5_st~0, ~T6_E~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ~T4_E~0, ULTIMATE.start_start_simulation_#t~ret17, ~t6_i~0, ~t2_st~0, ~t2_pc~0, ULTIMATE.start_main_~__retres1~8, ~T2_E~0, ~t6_st~0, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_6~0, ULTIMATE.start_main_#res, ~E_2~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 48#L444true [3638] L444-->L451-1: Formula: (and (> v_~m_i~0_4 1) (= v_~m_st~0_3 2)) InVars {~m_i~0=v_~m_i~0_4} OutVars{~m_st~0=v_~m_st~0_3, ~m_i~0=v_~m_i~0_4} AuxVars[] AssignedVars[~m_st~0] 363#L451-1true [3640] L451-1-->L456-1: Formula: (and (> 1 v_~t1_i~0_4) (= v_~t1_st~0_3 2)) InVars {~t1_i~0=v_~t1_i~0_4} OutVars{~t1_st~0=v_~t1_st~0_3, ~t1_i~0=v_~t1_i~0_4} AuxVars[] AssignedVars[~t1_st~0] 114#L456-1true [2574] L456-1-->L461-1: Formula: (and (= v_~t2_st~0_2 0) (= 1 v_~t2_i~0_3)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_2} AuxVars[] AssignedVars[~t2_st~0] 282#L461-1true [3644] L461-1-->L466-1: Formula: (and (< v_~t3_i~0_4 1) (= v_~t3_st~0_4 2)) InVars {~t3_i~0=v_~t3_i~0_4} OutVars{~t3_st~0=v_~t3_st~0_4, ~t3_i~0=v_~t3_i~0_4} AuxVars[] AssignedVars[~t3_st~0] 50#L466-1true [3646] L466-1-->L471-1: Formula: (and (< v_~t4_i~0_4 1) (= v_~t4_st~0_5 2)) InVars {~t4_i~0=v_~t4_i~0_4} OutVars{~t4_i~0=v_~t4_i~0_4, ~t4_st~0=v_~t4_st~0_5} AuxVars[] AssignedVars[~t4_st~0] 463#L471-1true [3647] L471-1-->L476-1: Formula: (and (= v_~t5_st~0_5 2) (< v_~t5_i~0_4 1)) InVars {~t5_i~0=v_~t5_i~0_4} OutVars{~t5_i~0=v_~t5_i~0_4, ~t5_st~0=v_~t5_st~0_5} AuxVars[] AssignedVars[~t5_st~0] 216#L476-1true [2761] L476-1-->L481-1: Formula: (and (= 1 v_~t6_i~0_3) (= v_~t6_st~0_4 0)) InVars {~t6_i~0=v_~t6_i~0_3} OutVars{~t6_st~0=v_~t6_st~0_4, ~t6_i~0=v_~t6_i~0_3} AuxVars[] AssignedVars[~t6_st~0] 506#L481-1true [3652] L481-1-->L660-1: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 371#L660-1true [3654] L660-1-->L665-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 5#L665-1true [2383] L665-1-->L670-1: Formula: (and (= 0 v_~T2_E~0_3) (= v_~T2_E~0_2 1)) InVars {~T2_E~0=v_~T2_E~0_3} OutVars{~T2_E~0=v_~T2_E~0_2} AuxVars[] AssignedVars[~T2_E~0] 288#L670-1true [2894] L670-1-->L675-1: Formula: (and (= v_~T3_E~0_2 1) (= v_~T3_E~0_3 0)) InVars {~T3_E~0=v_~T3_E~0_3} OutVars{~T3_E~0=v_~T3_E~0_2} AuxVars[] AssignedVars[~T3_E~0] 54#L675-1true [3660] L675-1-->L680-1: Formula: (< v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 471#L680-1true [3662] L680-1-->L685-1: Formula: (< v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 225#L685-1true [3663] L685-1-->L690-1: Formula: (< 0 v_~T6_E~0_4) InVars {~T6_E~0=v_~T6_E~0_4} OutVars{~T6_E~0=v_~T6_E~0_4} AuxVars[] AssignedVars[] 514#L690-1true [3310] L690-1-->L695-1: Formula: (and (= v_~E_1~0_5 0) (= v_~E_1~0_4 1)) InVars {~E_1~0=v_~E_1~0_5} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[~E_1~0] 137#L695-1true [2621] L695-1-->L700-1: Formula: (and (= v_~E_2~0_4 1) (= v_~E_2~0_5 0)) InVars {~E_2~0=v_~E_2~0_5} OutVars{~E_2~0=v_~E_2~0_4} AuxVars[] AssignedVars[~E_2~0] 446#L700-1true [3180] L700-1-->L705-1: Formula: (and (= v_~E_3~0_5 0) (= v_~E_3~0_4 1)) InVars {~E_3~0=v_~E_3~0_5} OutVars{~E_3~0=v_~E_3~0_4} AuxVars[] AssignedVars[~E_3~0] 335#L705-1true [3672] L705-1-->L710-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 92#L710-1true [2525] L710-1-->L715-1: Formula: (and (= v_~E_5~0_3 0) (= v_~E_5~0_2 1)) InVars {~E_5~0=v_~E_5~0_3} OutVars{~E_5~0=v_~E_5~0_2} AuxVars[] AssignedVars[~E_5~0] 387#L715-1true [3676] L715-1-->L720-1: Formula: (< v_~E_6~0_4 0) InVars {~E_6~0=v_~E_6~0_4} OutVars{~E_6~0=v_~E_6~0_4} AuxVars[] AssignedVars[] 23#L720-1true [2412] L720-1-->L310: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_7, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_4|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_4|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_7, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_4, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_4, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_2|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_2|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_4|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_4|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_7, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_2|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_4} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 124#L310true [2597] L310-->L311: Formula: (= v_~m_pc~0_4 1) InVars {~m_pc~0=v_~m_pc~0_4} OutVars{~m_pc~0=v_~m_pc~0_4} AuxVars[] AssignedVars[] 201#L311true [2732] L311-->L321: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_10 1) (= 1 v_~M_E~0_8)) InVars {~M_E~0=v_~M_E~0_8} OutVars{~M_E~0=v_~M_E~0_8, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_10} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 122#L321true [4267] L321-->L815: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 339#L815true [3682] L815-->L815-2: Formula: (and (= v_~m_st~0_5 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_11)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} OutVars{~m_st~0=v_~m_st~0_5, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} AuxVars[] AssignedVars[~m_st~0] 331#L815-2true [2961] L815-2-->L329: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 266#L329true [2848] L329-->L330: Formula: (= v_~t1_pc~0_4 1) InVars {~t1_pc~0=v_~t1_pc~0_4} OutVars{~t1_pc~0=v_~t1_pc~0_4} AuxVars[] AssignedVars[] 366#L330true [3036] L330-->L340: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_10 1) (= v_~E_1~0_7 1)) InVars {~E_1~0=v_~E_1~0_7} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_10, ~E_1~0=v_~E_1~0_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 264#L340true [4268] L340-->L823: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 476#L823true [3688] L823-->L823-2: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___0~0_11 0) (= v_~t1_st~0_5 0)) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_11} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_11, ~t1_st~0=v_~t1_st~0_5} AuxVars[] AssignedVars[~t1_st~0] 477#L823-2true [3235] L823-2-->L348: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_4|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 426#L348true [3143] L348-->L349: Formula: (= v_~t2_pc~0_4 1) InVars {~t2_pc~0=v_~t2_pc~0_4} OutVars{~t2_pc~0=v_~t2_pc~0_4} AuxVars[] AssignedVars[] 492#L349true [3267] L349-->L359: Formula: (and (= v_~E_2~0_7 1) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_10 1)) InVars {~E_2~0=v_~E_2~0_7} OutVars{~E_2~0=v_~E_2~0_7, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_10} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 423#L359true [4269] L359-->L831: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 97#L831true [3694] L831-->L831-2: Formula: (and (= v_~t2_st~0_5 0) (> v_ULTIMATE.start_activate_threads_~tmp___1~0_11 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_11} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_11, ~t2_st~0=v_~t2_st~0_5} AuxVars[] AssignedVars[~t2_st~0] 89#L831-2true [2520] L831-2-->L367: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_4|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 52#L367true [3695] L367-->L367-2: Formula: (> 1 v_~t3_pc~0_5) InVars {~t3_pc~0=v_~t3_pc~0_5} OutVars{~t3_pc~0=v_~t3_pc~0_5} AuxVars[] AssignedVars[] 40#L367-2true [2438] L367-2-->L378: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 51#L378true [4270] L378-->L839: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 233#L839true [2791] L839-->L839-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} AuxVars[] AssignedVars[] 235#L839-2true [2794] L839-2-->L386: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_7, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 171#L386true [2675] L386-->L387: Formula: (= v_~t4_pc~0_4 1) InVars {~t4_pc~0=v_~t4_pc~0_4} OutVars{~t4_pc~0=v_~t4_pc~0_4} AuxVars[] AssignedVars[] 120#L387true [2588] L387-->L397: Formula: (and (= v_~E_4~0_7 1) (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_10 1)) InVars {~E_4~0=v_~E_4~0_7} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_10, ~E_4~0=v_~E_4~0_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 170#L397true [4271] L397-->L847: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 394#L847true [3084] L847-->L847-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} AuxVars[] AssignedVars[] 382#L847-2true [3064] L847-2-->L405: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_4|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 466#L405true [3708] L405-->L405-2: Formula: (> 1 v_~t5_pc~0_5) InVars {~t5_pc~0=v_~t5_pc~0_5} OutVars{~t5_pc~0=v_~t5_pc~0_5} AuxVars[] AssignedVars[] 318#L405-2true [2940] L405-2-->L416: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 465#L416true [4272] L416-->L855: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 398#L855true [3711] L855-->L855-2: Formula: (and (> v_ULTIMATE.start_activate_threads_~tmp___4~0_11 0) (= v_~t5_st~0_7 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_11} OutVars{~t5_st~0=v_~t5_st~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_11} AuxVars[] AssignedVars[~t5_st~0] 400#L855-2true [3093] L855-2-->L424: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_4|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 75#L424true [3714] L424-->L424-2: Formula: (> v_~t6_pc~0_5 1) InVars {~t6_pc~0=v_~t6_pc~0_5} OutVars{~t6_pc~0=v_~t6_pc~0_5} AuxVars[] AssignedVars[] 79#L424-2true [2503] L424-2-->L435: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 73#L435true [4273] L435-->L863: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___5~0_49 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_28|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_28|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 30#L863true [2425] L863-->L863-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___5~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} AuxVars[] AssignedVars[] 16#L863-2true [3720] L863-2-->L733-1: Formula: (< v_~M_E~0_15 1) InVars {~M_E~0=v_~M_E~0_15} OutVars{~M_E~0=v_~M_E~0_15} AuxVars[] AssignedVars[] 443#L733-1true [3722] L733-1-->L738-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 333#L738-1true [3724] L738-1-->L743-1: Formula: (> 1 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 91#L743-1true [3726] L743-1-->L748-1: Formula: (< 1 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 385#L748-1true [3727] L748-1-->L753-1: Formula: (< v_~T4_E~0_10 1) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 20#L753-1true [2407] L753-1-->L758-1: Formula: (and (= v_~T5_E~0_8 2) (= v_~T5_E~0_9 1)) InVars {~T5_E~0=v_~T5_E~0_9} OutVars{~T5_E~0=v_~T5_E~0_8} AuxVars[] AssignedVars[~T5_E~0] 299#L758-1true [3732] L758-1-->L763-1: Formula: (< v_~T6_E~0_10 1) InVars {~T6_E~0=v_~T6_E~0_10} OutVars{~T6_E~0=v_~T6_E~0_10} AuxVars[] AssignedVars[] 59#L763-1true [2475] L763-1-->L768-1: Formula: (and (= v_~E_1~0_12 2) (= 1 v_~E_1~0_13)) InVars {~E_1~0=v_~E_1~0_13} OutVars{~E_1~0=v_~E_1~0_12} AuxVars[] AssignedVars[~E_1~0] 478#L768-1true [3736] L768-1-->L773-1: Formula: (< 1 v_~E_2~0_14) InVars {~E_2~0=v_~E_2~0_14} OutVars{~E_2~0=v_~E_2~0_14} AuxVars[] AssignedVars[] 219#L773-1true [2767] L773-1-->L778-1: Formula: (and (= 1 v_~E_3~0_13) (= v_~E_3~0_12 2)) InVars {~E_3~0=v_~E_3~0_13} OutVars{~E_3~0=v_~E_3~0_12} AuxVars[] AssignedVars[~E_3~0] 509#L778-1true [3740] L778-1-->L783-1: Formula: (< 1 v_~E_4~0_14) InVars {~E_4~0=v_~E_4~0_14} OutVars{~E_4~0=v_~E_4~0_14} AuxVars[] AssignedVars[] 133#L783-1true [3742] L783-1-->L788-1: Formula: (> 1 v_~E_5~0_14) InVars {~E_5~0=v_~E_5~0_14} OutVars{~E_5~0=v_~E_5~0_14} AuxVars[] AssignedVars[] 441#L788-1true [3743] L788-1-->L1014-1: Formula: (> 1 v_~E_6~0_14) InVars {~E_6~0=v_~E_6~0_14} OutVars{~E_6~0=v_~E_6~0_14} AuxVars[] AssignedVars[] 152#L1014-1true [2020-06-22 00:12:58,873 INFO L796 eck$LassoCheckResult]: Loop: 152#L1014-1true [4274] L1014-1-->L635: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp_ndt_7~0=v_ULTIMATE.start_eval_~tmp_ndt_7~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp_ndt_7~0] 516#L635true [4275] L635-->L494: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_37} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 280#L494true [2876] L494-->L531: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21 1) (= v_~m_st~0_8 0)) InVars {~m_st~0=v_~m_st~0_8} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21, ~m_st~0=v_~m_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 209#L531true [4276] L531-->L546: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 436#L546true [4278] L546-->L660-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 373#L660-2true [3747] L660-2-->L660-4: Formula: (> v_~M_E~0_30 0) InVars {~M_E~0=v_~M_E~0_30} OutVars{~M_E~0=v_~M_E~0_30} AuxVars[] AssignedVars[] 378#L660-4true [3058] L660-4-->L665-3: Formula: (and (= v_~T1_E~0_11 1) (= v_~T1_E~0_12 0)) InVars {~T1_E~0=v_~T1_E~0_12} OutVars{~T1_E~0=v_~T1_E~0_11} AuxVars[] AssignedVars[~T1_E~0] 12#L665-3true [2394] L665-3-->L670-3: Formula: (and (= 0 v_~T2_E~0_12) (= v_~T2_E~0_11 1)) InVars {~T2_E~0=v_~T2_E~0_12} OutVars{~T2_E~0=v_~T2_E~0_11} AuxVars[] AssignedVars[~T2_E~0] 292#L670-3true [3761] L670-3-->L675-3: Formula: (> 0 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 55#L675-3true [2467] L675-3-->L680-3: Formula: (and (= v_~T4_E~0_11 1) (= v_~T4_E~0_12 0)) InVars {~T4_E~0=v_~T4_E~0_12} OutVars{~T4_E~0=v_~T4_E~0_11} AuxVars[] AssignedVars[~T4_E~0] 473#L680-3true [3776] L680-3-->L685-3: Formula: (< 0 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 228#L685-3true [3785] L685-3-->L690-3: Formula: (> v_~T6_E~0_13 0) InVars {~T6_E~0=v_~T6_E~0_13} OutVars{~T6_E~0=v_~T6_E~0_13} AuxVars[] AssignedVars[] 519#L690-3true [3795] L690-3-->L695-3: Formula: (< 0 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 130#L695-3true [2609] L695-3-->L700-3: Formula: (and (= 0 v_~E_2~0_30) (= v_~E_2~0_29 1)) InVars {~E_2~0=v_~E_2~0_30} OutVars{~E_2~0=v_~E_2~0_29} AuxVars[] AssignedVars[~E_2~0] 432#L700-3true [3155] L700-3-->L705-3: Formula: (and (= v_~E_3~0_29 1) (= 0 v_~E_3~0_30)) InVars {~E_3~0=v_~E_3~0_30} OutVars{~E_3~0=v_~E_3~0_29} AuxVars[] AssignedVars[~E_3~0] 180#L705-3true [2688] L705-3-->L710-3: Formula: (and (= v_~E_4~0_29 1) (= 0 v_~E_4~0_30)) InVars {~E_4~0=v_~E_4~0_30} OutVars{~E_4~0=v_~E_4~0_29} AuxVars[] AssignedVars[~E_4~0] 86#L710-3true [2515] L710-3-->L715-3: Formula: (and (= 0 v_~E_5~0_30) (= v_~E_5~0_29 1)) InVars {~E_5~0=v_~E_5~0_30} OutVars{~E_5~0=v_~E_5~0_29} AuxVars[] AssignedVars[~E_5~0] 372#L715-3true [3048] L715-3-->L720-3: Formula: (and (= v_~E_6~0_29 1) (= 0 v_~E_6~0_30)) InVars {~E_6~0=v_~E_6~0_30} OutVars{~E_6~0=v_~E_6~0_29} AuxVars[] AssignedVars[~E_6~0] 8#L720-3true [2388] L720-3-->L310-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_43, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_43, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_25|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_25|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_25|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_43, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_43, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_43, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_25|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_25|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_25|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_25|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_43, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_25|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_43, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_43} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 226#L310-21true [2779] L310-21-->L311-7: Formula: (= v_~m_pc~0_23 1) InVars {~m_pc~0=v_~m_pc~0_23} OutVars{~m_pc~0=v_~m_pc~0_23} AuxVars[] AssignedVars[] 195#L311-7true [2720] L311-7-->L321-7: Formula: (and (= v_~M_E~0_31 1) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_46 1)) InVars {~M_E~0=v_~M_E~0_31} OutVars{~M_E~0=v_~M_E~0_31, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_46} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 254#L321-7true [4303] L321-7-->L815-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 165#L815-21true [3897] L815-21-->L815-23: Formula: (and (> 0 v_ULTIMATE.start_activate_threads_~tmp~1_47) (= v_~m_st~0_20 0)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_47} OutVars{~m_st~0=v_~m_st~0_20, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_47} AuxVars[] AssignedVars[~m_st~0] 147#L815-23true [2638] L815-23-->L329-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 367#L329-21true [3038] L329-21-->L330-7: Formula: (= v_~t1_pc~0_23 1) InVars {~t1_pc~0=v_~t1_pc~0_23} OutVars{~t1_pc~0=v_~t1_pc~0_23} AuxVars[] AssignedVars[] 341#L330-7true [2981] L330-7-->L340-7: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_52 1) (= 1 v_~E_1~0_32)) InVars {~E_1~0=v_~E_1~0_32} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_52, ~E_1~0=v_~E_1~0_32} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 260#L340-7true [4310] L340-7-->L823-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 311#L823-21true [2931] L823-21-->L823-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} AuxVars[] AssignedVars[] 313#L823-23true [2934] L823-23-->L348-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_25|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 512#L348-21true [3953] L348-21-->L348-23: Formula: (> 1 v_~t2_pc~0_24) InVars {~t2_pc~0=v_~t2_pc~0_24} OutVars{~t2_pc~0=v_~t2_pc~0_24} AuxVars[] AssignedVars[] 518#L348-23true [3319] L348-23-->L359-7: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 417#L359-7true [4317] L359-7-->L831-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 70#L831-21true [2490] L831-21-->L831-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} AuxVars[] AssignedVars[] 455#L831-23true [3197] L831-23-->L367-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_25|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 21#L367-21true [2409] L367-21-->L368-7: Formula: (= v_~t3_pc~0_23 1) InVars {~t3_pc~0=v_~t3_pc~0_23} OutVars{~t3_pc~0=v_~t3_pc~0_23} AuxVars[] AssignedVars[] 98#L368-7true [2539] L368-7-->L378-7: Formula: (and (= 1 v_~E_3~0_32) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_52 1)) InVars {~E_3~0=v_~E_3~0_32} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_52, ~E_3~0=v_~E_3~0_32} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 34#L378-7true [4324] L378-7-->L839-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 193#L839-21true [4023] L839-21-->L839-23: Formula: (and (= v_~t3_st~0_21 0) (> v_ULTIMATE.start_activate_threads_~tmp___2~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} OutVars{~t3_st~0=v_~t3_st~0_21, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} AuxVars[] AssignedVars[~t3_st~0] 196#L839-23true [2722] L839-23-->L386-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_49, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 135#L386-21true [2617] L386-21-->L387-7: Formula: (= 1 v_~t4_pc~0_23) InVars {~t4_pc~0=v_~t4_pc~0_23} OutVars{~t4_pc~0=v_~t4_pc~0_23} AuxVars[] AssignedVars[] 249#L387-7true [2818] L387-7-->L397-7: Formula: (and (= 1 v_~E_4~0_32) (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_52 1)) InVars {~E_4~0=v_~E_4~0_32} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_52, ~E_4~0=v_~E_4~0_32} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 162#L397-7true [4331] L397-7-->L847-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 358#L847-21true [4065] L847-21-->L847-23: Formula: (and (= v_~t4_st~0_22 0) (< v_ULTIMATE.start_activate_threads_~tmp___3~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47, ~t4_st~0=v_~t4_st~0_22} AuxVars[] AssignedVars[~t4_st~0] 342#L847-23true [2983] L847-23-->L405-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_25|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 298#L405-21true [2911] L405-21-->L406-7: Formula: (= v_~t5_pc~0_23 1) InVars {~t5_pc~0=v_~t5_pc~0_23} OutVars{~t5_pc~0=v_~t5_pc~0_23} AuxVars[] AssignedVars[] 279#L406-7true [2874] L406-7-->L416-7: Formula: (and (= 1 v_~E_5~0_32) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_52 1)) InVars {~E_5~0=v_~E_5~0_32} OutVars{~E_5~0=v_~E_5~0_32, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_52} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 307#L416-7true [4338] L416-7-->L855-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 484#L855-21true [3251] L855-21-->L855-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} AuxVars[] AssignedVars[] 487#L855-23true [3257] L855-23-->L424-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_25|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 442#L424-21true [3173] L424-21-->L425-7: Formula: (= 1 v_~t6_pc~0_23) InVars {~t6_pc~0=v_~t6_pc~0_23} OutVars{~t6_pc~0=v_~t6_pc~0_23} AuxVars[] AssignedVars[] 412#L425-7true [3114] L425-7-->L435-7: Formula: (and (= 1 v_~E_6~0_32) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_52 1)) InVars {~E_6~0=v_~E_6~0_32} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_52, ~E_6~0=v_~E_6~0_32} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 66#L435-7true [4340] L435-7-->L863-21: Formula: (and (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___5~0_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_35|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_41|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 111#L863-21true [4135] L863-21-->L863-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___5~0_47 0) (= v_~t6_st~0_22 0)) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} OutVars{~t6_st~0=v_~t6_st~0_22, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} AuxVars[] AssignedVars[~t6_st~0] 99#L863-23true [4137] L863-23-->L733-3: Formula: (< v_~M_E~0_35 1) InVars {~M_E~0=v_~M_E~0_35} OutVars{~M_E~0=v_~M_E~0_35} AuxVars[] AssignedVars[] 448#L733-3true [3184] L733-3-->L738-3: Formula: (and (= v_~T1_E~0_15 1) (= v_~T1_E~0_14 2)) InVars {~T1_E~0=v_~T1_E~0_15} OutVars{~T1_E~0=v_~T1_E~0_14} AuxVars[] AssignedVars[~T1_E~0] 337#L738-3true [2971] L738-3-->L743-3: Formula: (and (= v_~T2_E~0_14 2) (= 1 v_~T2_E~0_15)) InVars {~T2_E~0=v_~T2_E~0_15} OutVars{~T2_E~0=v_~T2_E~0_14} AuxVars[] AssignedVars[~T2_E~0] 84#L743-3true [4144] L743-3-->L748-3: Formula: (> 1 v_~T3_E~0_16) InVars {~T3_E~0=v_~T3_E~0_16} OutVars{~T3_E~0=v_~T3_E~0_16} AuxVars[] AssignedVars[] 369#L748-3true [4145] L748-3-->L753-3: Formula: (> v_~T4_E~0_16 1) InVars {~T4_E~0=v_~T4_E~0_16} OutVars{~T4_E~0=v_~T4_E~0_16} AuxVars[] AssignedVars[] 4#L753-3true [4147] L753-3-->L758-3: Formula: (> 1 v_~T5_E~0_16) InVars {~T5_E~0=v_~T5_E~0_16} OutVars{~T5_E~0=v_~T5_E~0_16} AuxVars[] AssignedVars[] 287#L758-3true [4149] L758-3-->L763-3: Formula: (> v_~T6_E~0_16 1) InVars {~T6_E~0=v_~T6_E~0_16} OutVars{~T6_E~0=v_~T6_E~0_16} AuxVars[] AssignedVars[] 53#L763-3true [4151] L763-3-->L768-3: Formula: (< 1 v_~E_1~0_36) InVars {~E_1~0=v_~E_1~0_36} OutVars{~E_1~0=v_~E_1~0_36} AuxVars[] AssignedVars[] 469#L768-3true [3219] L768-3-->L773-3: Formula: (and (= 1 v_~E_2~0_35) (= v_~E_2~0_34 2)) InVars {~E_2~0=v_~E_2~0_35} OutVars{~E_2~0=v_~E_2~0_34} AuxVars[] AssignedVars[~E_2~0] 224#L773-3true [2775] L773-3-->L778-3: Formula: (and (= 1 v_~E_3~0_35) (= v_~E_3~0_34 2)) InVars {~E_3~0=v_~E_3~0_35} OutVars{~E_3~0=v_~E_3~0_34} AuxVars[] AssignedVars[~E_3~0] 513#L778-3true [3308] L778-3-->L783-3: Formula: (and (= 1 v_~E_4~0_35) (= v_~E_4~0_34 2)) InVars {~E_4~0=v_~E_4~0_35} OutVars{~E_4~0=v_~E_4~0_34} AuxVars[] AssignedVars[~E_4~0] 136#L783-3true [4160] L783-3-->L788-3: Formula: (< 1 v_~E_5~0_36) InVars {~E_5~0=v_~E_5~0_36} OutVars{~E_5~0=v_~E_5~0_36} AuxVars[] AssignedVars[] 445#L788-3true [4161] L788-3-->L793-3: Formula: (> 1 v_~E_6~0_36) InVars {~E_6~0=v_~E_6~0_36} OutVars{~E_6~0=v_~E_6~0_36} AuxVars[] AssignedVars[] 334#L793-3true [2966] L793-3-->L494-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_30} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 281#L494-1true [2878] L494-1-->L531-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33 1) (= 0 v_~m_st~0_21)) InVars {~m_st~0=v_~m_st~0_21} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33, ~m_st~0=v_~m_st~0_21} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 211#L531-1true [4341] L531-1-->L1033: Formula: (and (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp~3] 300#L1033true [4169] L1033-->L1033-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_6) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} AuxVars[] AssignedVars[] 302#L1033-1true [2919] L1033-1-->L494-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_3|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_6, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_exists_runnable_thread_~__retres1~7, ULTIMATE.start_stop_simulation_#res] 283#L494-2true [2882] L494-2-->L531-2: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9 1) (= v_~m_st~0_6 0)) InVars {~m_st~0=v_~m_st~0_6} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9, ~m_st~0=v_~m_st~0_6} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 215#L531-2true [4343] L531-2-->L988: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 480#L988true [3240] L988-->L995: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 26#L995true [4354] L995-->L1014-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_6|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_#t~ret17, ULTIMATE.start_stop_simulation_#res] 152#L1014-1true [2020-06-22 00:12:58,880 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:12:58,880 INFO L82 PathProgramCache]: Analyzing trace with hash -1898114906, now seen corresponding path program 1 times [2020-06-22 00:12:58,882 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:12:58,883 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:12:58,903 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:12:58,903 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:12:58,903 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:12:58,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:12:59,005 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:12:59,007 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:12:59,008 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-06-22 00:12:59,012 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-06-22 00:12:59,013 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:12:59,013 INFO L82 PathProgramCache]: Analyzing trace with hash 138716110, now seen corresponding path program 1 times [2020-06-22 00:12:59,013 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:12:59,013 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:12:59,014 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:12:59,014 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:12:59,015 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:12:59,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:12:59,070 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:12:59,070 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:12:59,071 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2020-06-22 00:12:59,073 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-06-22 00:12:59,087 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-06-22 00:12:59,088 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-06-22 00:12:59,089 INFO L87 Difference]: Start difference. First operand 518 states. Second operand 3 states. [2020-06-22 00:12:59,781 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-06-22 00:12:59,781 INFO L93 Difference]: Finished difference Result 518 states and 1142 transitions. [2020-06-22 00:12:59,781 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-06-22 00:12:59,785 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 518 states and 1142 transitions. [2020-06-22 00:12:59,792 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 442 [2020-06-22 00:12:59,803 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 518 states to 518 states and 1142 transitions. [2020-06-22 00:12:59,804 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 518 [2020-06-22 00:12:59,805 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 518 [2020-06-22 00:12:59,806 INFO L73 IsDeterministic]: Start isDeterministic. Operand 518 states and 1142 transitions. [2020-06-22 00:12:59,810 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-06-22 00:12:59,811 INFO L706 BuchiCegarLoop]: Abstraction has 518 states and 1142 transitions. [2020-06-22 00:12:59,831 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 518 states and 1142 transitions. [2020-06-22 00:12:59,865 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 518 to 518. [2020-06-22 00:12:59,866 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 518 states. [2020-06-22 00:12:59,868 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 518 states to 518 states and 1142 transitions. [2020-06-22 00:12:59,870 INFO L729 BuchiCegarLoop]: Abstraction has 518 states and 1142 transitions. [2020-06-22 00:12:59,870 INFO L609 BuchiCegarLoop]: Abstraction has 518 states and 1142 transitions. [2020-06-22 00:12:59,870 INFO L442 BuchiCegarLoop]: ======== Iteration 2============ [2020-06-22 00:12:59,870 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 518 states and 1142 transitions. [2020-06-22 00:12:59,874 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 442 [2020-06-22 00:12:59,874 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-06-22 00:12:59,874 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-06-22 00:12:59,877 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:12:59,877 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:12:59,879 INFO L794 eck$LassoCheckResult]: Stem: 1483#ULTIMATE.startENTRY [4266] ULTIMATE.startENTRY-->L444: Formula: (and (= 1 v_~t6_i~0_7) (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~M_E~0_37 2) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 0 v_~t6_pc~0_26) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_6~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= v_~T6_E~0_18 2) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~t6_st~0_24) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t6_pc~0=v_~t6_pc~0_26, ~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~T6_E~0=v_~T6_E~0_18, ~M_E~0=v_~M_E~0_37, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ~T4_E~0=v_~T4_E~0_18, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_4|, ~t6_i~0=v_~t6_i~0_7, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ULTIMATE.start_main_~__retres1~8=v_ULTIMATE.start_main_~__retres1~8_6, ~T2_E~0=v_~T2_E~0_18, ~t6_st~0=v_~t6_st~0_24, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_6~0=v_~E_6~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t6_pc~0, ~t5_i~0, ~t1_pc~0, ~t5_st~0, ~T6_E~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ~T4_E~0, ULTIMATE.start_start_simulation_#t~ret17, ~t6_i~0, ~t2_st~0, ~t2_pc~0, ULTIMATE.start_main_~__retres1~8, ~T2_E~0, ~t6_st~0, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_6~0, ULTIMATE.start_main_#res, ~E_2~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 1130#L444 [3637] L444-->L451-1: Formula: (and (= v_~m_st~0_3 2) (< v_~m_i~0_4 1)) InVars {~m_i~0=v_~m_i~0_4} OutVars{~m_st~0=v_~m_st~0_3, ~m_i~0=v_~m_i~0_4} AuxVars[] AssignedVars[~m_st~0] 1131#L451-1 [3640] L451-1-->L456-1: Formula: (and (> 1 v_~t1_i~0_4) (= v_~t1_st~0_3 2)) InVars {~t1_i~0=v_~t1_i~0_4} OutVars{~t1_st~0=v_~t1_st~0_3, ~t1_i~0=v_~t1_i~0_4} AuxVars[] AssignedVars[~t1_st~0] 1219#L456-1 [2574] L456-1-->L461-1: Formula: (and (= v_~t2_st~0_2 0) (= 1 v_~t2_i~0_3)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_2} AuxVars[] AssignedVars[~t2_st~0] 1220#L461-1 [3644] L461-1-->L466-1: Formula: (and (< v_~t3_i~0_4 1) (= v_~t3_st~0_4 2)) InVars {~t3_i~0=v_~t3_i~0_4} OutVars{~t3_st~0=v_~t3_st~0_4, ~t3_i~0=v_~t3_i~0_4} AuxVars[] AssignedVars[~t3_st~0] 1135#L466-1 [3646] L466-1-->L471-1: Formula: (and (< v_~t4_i~0_4 1) (= v_~t4_st~0_5 2)) InVars {~t4_i~0=v_~t4_i~0_4} OutVars{~t4_i~0=v_~t4_i~0_4, ~t4_st~0=v_~t4_st~0_5} AuxVars[] AssignedVars[~t4_st~0] 1136#L471-1 [3647] L471-1-->L476-1: Formula: (and (= v_~t5_st~0_5 2) (< v_~t5_i~0_4 1)) InVars {~t5_i~0=v_~t5_i~0_4} OutVars{~t5_i~0=v_~t5_i~0_4, ~t5_st~0=v_~t5_st~0_5} AuxVars[] AssignedVars[~t5_st~0] 1359#L476-1 [2761] L476-1-->L481-1: Formula: (and (= 1 v_~t6_i~0_3) (= v_~t6_st~0_4 0)) InVars {~t6_i~0=v_~t6_i~0_3} OutVars{~t6_st~0=v_~t6_st~0_4, ~t6_i~0=v_~t6_i~0_3} AuxVars[] AssignedVars[~t6_st~0] 1360#L481-1 [3652] L481-1-->L660-1: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 1494#L660-1 [3654] L660-1-->L665-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 1051#L665-1 [2383] L665-1-->L670-1: Formula: (and (= 0 v_~T2_E~0_3) (= v_~T2_E~0_2 1)) InVars {~T2_E~0=v_~T2_E~0_3} OutVars{~T2_E~0=v_~T2_E~0_2} AuxVars[] AssignedVars[~T2_E~0] 1052#L670-1 [2894] L670-1-->L675-1: Formula: (and (= v_~T3_E~0_2 1) (= v_~T3_E~0_3 0)) InVars {~T3_E~0=v_~T3_E~0_3} OutVars{~T3_E~0=v_~T3_E~0_2} AuxVars[] AssignedVars[~T3_E~0] 1142#L675-1 [3660] L675-1-->L680-1: Formula: (< v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 1143#L680-1 [3662] L680-1-->L685-1: Formula: (< v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 1368#L685-1 [3663] L685-1-->L690-1: Formula: (< 0 v_~T6_E~0_4) InVars {~T6_E~0=v_~T6_E~0_4} OutVars{~T6_E~0=v_~T6_E~0_4} AuxVars[] AssignedVars[] 1369#L690-1 [3310] L690-1-->L695-1: Formula: (and (= v_~E_1~0_5 0) (= v_~E_1~0_4 1)) InVars {~E_1~0=v_~E_1~0_5} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[~E_1~0] 1264#L695-1 [2621] L695-1-->L700-1: Formula: (and (= v_~E_2~0_4 1) (= v_~E_2~0_5 0)) InVars {~E_2~0=v_~E_2~0_5} OutVars{~E_2~0=v_~E_2~0_4} AuxVars[] AssignedVars[~E_2~0] 1265#L700-1 [3180] L700-1-->L705-1: Formula: (and (= v_~E_3~0_5 0) (= v_~E_3~0_4 1)) InVars {~E_3~0=v_~E_3~0_5} OutVars{~E_3~0=v_~E_3~0_4} AuxVars[] AssignedVars[~E_3~0] 1470#L705-1 [3672] L705-1-->L710-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 1203#L710-1 [2525] L710-1-->L715-1: Formula: (and (= v_~E_5~0_3 0) (= v_~E_5~0_2 1)) InVars {~E_5~0=v_~E_5~0_3} OutVars{~E_5~0=v_~E_5~0_2} AuxVars[] AssignedVars[~E_5~0] 1204#L715-1 [3676] L715-1-->L720-1: Formula: (< v_~E_6~0_4 0) InVars {~E_6~0=v_~E_6~0_4} OutVars{~E_6~0=v_~E_6~0_4} AuxVars[] AssignedVars[] 1087#L720-1 [2412] L720-1-->L310: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_7, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_4|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_4|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_7, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_4, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_4, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_2|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_2|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_4|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_4|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_7, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_2|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_4} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 1088#L310 [2597] L310-->L311: Formula: (= v_~m_pc~0_4 1) InVars {~m_pc~0=v_~m_pc~0_4} OutVars{~m_pc~0=v_~m_pc~0_4} AuxVars[] AssignedVars[] 1235#L311 [2732] L311-->L321: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_10 1) (= 1 v_~M_E~0_8)) InVars {~M_E~0=v_~M_E~0_8} OutVars{~M_E~0=v_~M_E~0_8, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_10} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 1230#L321 [4267] L321-->L815: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 1231#L815 [3682] L815-->L815-2: Formula: (and (= v_~m_st~0_5 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_11)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} OutVars{~m_st~0=v_~m_st~0_5, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} AuxVars[] AssignedVars[~m_st~0] 1466#L815-2 [2961] L815-2-->L329: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 1402#L329 [2848] L329-->L330: Formula: (= v_~t1_pc~0_4 1) InVars {~t1_pc~0=v_~t1_pc~0_4} OutVars{~t1_pc~0=v_~t1_pc~0_4} AuxVars[] AssignedVars[] 1403#L330 [3036] L330-->L340: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_10 1) (= v_~E_1~0_7 1)) InVars {~E_1~0=v_~E_1~0_7} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_10, ~E_1~0=v_~E_1~0_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 1397#L340 [4268] L340-->L823: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 1398#L823 [3688] L823-->L823-2: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___0~0_11 0) (= v_~t1_st~0_5 0)) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_11} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_11, ~t1_st~0=v_~t1_st~0_5} AuxVars[] AssignedVars[~t1_st~0] 1552#L823-2 [3235] L823-2-->L348: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_4|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 1536#L348 [3143] L348-->L349: Formula: (= v_~t2_pc~0_4 1) InVars {~t2_pc~0=v_~t2_pc~0_4} OutVars{~t2_pc~0=v_~t2_pc~0_4} AuxVars[] AssignedVars[] 1537#L349 [3267] L349-->L359: Formula: (and (= v_~E_2~0_7 1) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_10 1)) InVars {~E_2~0=v_~E_2~0_7} OutVars{~E_2~0=v_~E_2~0_7, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_10} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 1535#L359 [4269] L359-->L831: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 1210#L831 [3694] L831-->L831-2: Formula: (and (= v_~t2_st~0_5 0) (> v_ULTIMATE.start_activate_threads_~tmp___1~0_11 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_11} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_11, ~t2_st~0=v_~t2_st~0_5} AuxVars[] AssignedVars[~t2_st~0] 1198#L831-2 [2520] L831-2-->L367: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_4|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 1138#L367 [3695] L367-->L367-2: Formula: (> 1 v_~t3_pc~0_5) InVars {~t3_pc~0=v_~t3_pc~0_5} OutVars{~t3_pc~0=v_~t3_pc~0_5} AuxVars[] AssignedVars[] 1116#L367-2 [2438] L367-2-->L378: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 1117#L378 [4270] L378-->L839: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 1137#L839 [2791] L839-->L839-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} AuxVars[] AssignedVars[] 1375#L839-2 [2794] L839-2-->L386: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_7, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 1305#L386 [2675] L386-->L387: Formula: (= v_~t4_pc~0_4 1) InVars {~t4_pc~0=v_~t4_pc~0_4} OutVars{~t4_pc~0=v_~t4_pc~0_4} AuxVars[] AssignedVars[] 1224#L387 [2588] L387-->L397: Formula: (and (= v_~E_4~0_7 1) (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_10 1)) InVars {~E_4~0=v_~E_4~0_7} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_10, ~E_4~0=v_~E_4~0_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 1226#L397 [4271] L397-->L847: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 1304#L847 [3084] L847-->L847-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} AuxVars[] AssignedVars[] 1498#L847-2 [3064] L847-2-->L405: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_4|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 1499#L405 [3708] L405-->L405-2: Formula: (> 1 v_~t5_pc~0_5) InVars {~t5_pc~0=v_~t5_pc~0_5} OutVars{~t5_pc~0=v_~t5_pc~0_5} AuxVars[] AssignedVars[] 1435#L405-2 [2940] L405-2-->L416: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 1434#L416 [4272] L416-->L855: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 1505#L855 [3711] L855-->L855-2: Formula: (and (> v_ULTIMATE.start_activate_threads_~tmp___4~0_11 0) (= v_~t5_st~0_7 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_11} OutVars{~t5_st~0=v_~t5_st~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_11} AuxVars[] AssignedVars[~t5_st~0] 1506#L855-2 [3093] L855-2-->L424: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_4|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 1182#L424 [3714] L424-->L424-2: Formula: (> v_~t6_pc~0_5 1) InVars {~t6_pc~0=v_~t6_pc~0_5} OutVars{~t6_pc~0=v_~t6_pc~0_5} AuxVars[] AssignedVars[] 1183#L424-2 [2503] L424-2-->L435: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 1179#L435 [4273] L435-->L863: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___5~0_49 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_28|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_28|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 1103#L863 [2425] L863-->L863-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___5~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} AuxVars[] AssignedVars[] 1074#L863-2 [3720] L863-2-->L733-1: Formula: (< v_~M_E~0_15 1) InVars {~M_E~0=v_~M_E~0_15} OutVars{~M_E~0=v_~M_E~0_15} AuxVars[] AssignedVars[] 1075#L733-1 [3722] L733-1-->L738-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 1468#L738-1 [3724] L738-1-->L743-1: Formula: (> 1 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 1201#L743-1 [3726] L743-1-->L748-1: Formula: (< 1 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 1202#L748-1 [3727] L748-1-->L753-1: Formula: (< v_~T4_E~0_10 1) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 1082#L753-1 [2407] L753-1-->L758-1: Formula: (and (= v_~T5_E~0_8 2) (= v_~T5_E~0_9 1)) InVars {~T5_E~0=v_~T5_E~0_9} OutVars{~T5_E~0=v_~T5_E~0_8} AuxVars[] AssignedVars[~T5_E~0] 1083#L758-1 [3732] L758-1-->L763-1: Formula: (< v_~T6_E~0_10 1) InVars {~T6_E~0=v_~T6_E~0_10} OutVars{~T6_E~0=v_~T6_E~0_10} AuxVars[] AssignedVars[] 1154#L763-1 [2475] L763-1-->L768-1: Formula: (and (= v_~E_1~0_12 2) (= 1 v_~E_1~0_13)) InVars {~E_1~0=v_~E_1~0_13} OutVars{~E_1~0=v_~E_1~0_12} AuxVars[] AssignedVars[~E_1~0] 1155#L768-1 [3736] L768-1-->L773-1: Formula: (< 1 v_~E_2~0_14) InVars {~E_2~0=v_~E_2~0_14} OutVars{~E_2~0=v_~E_2~0_14} AuxVars[] AssignedVars[] 1363#L773-1 [2767] L773-1-->L778-1: Formula: (and (= 1 v_~E_3~0_13) (= v_~E_3~0_12 2)) InVars {~E_3~0=v_~E_3~0_13} OutVars{~E_3~0=v_~E_3~0_12} AuxVars[] AssignedVars[~E_3~0] 1364#L778-1 [3740] L778-1-->L783-1: Formula: (< 1 v_~E_4~0_14) InVars {~E_4~0=v_~E_4~0_14} OutVars{~E_4~0=v_~E_4~0_14} AuxVars[] AssignedVars[] 1255#L783-1 [3742] L783-1-->L788-1: Formula: (> 1 v_~E_5~0_14) InVars {~E_5~0=v_~E_5~0_14} OutVars{~E_5~0=v_~E_5~0_14} AuxVars[] AssignedVars[] 1256#L788-1 [3743] L788-1-->L1014-1: Formula: (> 1 v_~E_6~0_14) InVars {~E_6~0=v_~E_6~0_14} OutVars{~E_6~0=v_~E_6~0_14} AuxVars[] AssignedVars[] 1095#L1014-1 [2020-06-22 00:12:59,881 INFO L796 eck$LassoCheckResult]: Loop: 1095#L1014-1 [4274] L1014-1-->L635: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp_ndt_7~0=v_ULTIMATE.start_eval_~tmp_ndt_7~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp_ndt_7~0] 1057#L635 [4275] L635-->L494: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_37} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 1430#L494 [2876] L494-->L531: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21 1) (= v_~m_st~0_8 0)) InVars {~m_st~0=v_~m_st~0_8} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21, ~m_st~0=v_~m_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 1126#L531 [4276] L531-->L546: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 1352#L546 [4278] L546-->L660-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 1495#L660-2 [3747] L660-2-->L660-4: Formula: (> v_~M_E~0_30 0) InVars {~M_E~0=v_~M_E~0_30} OutVars{~M_E~0=v_~M_E~0_30} AuxVars[] AssignedVars[] 1496#L660-4 [3058] L660-4-->L665-3: Formula: (and (= v_~T1_E~0_11 1) (= v_~T1_E~0_12 0)) InVars {~T1_E~0=v_~T1_E~0_12} OutVars{~T1_E~0=v_~T1_E~0_11} AuxVars[] AssignedVars[~T1_E~0] 1067#L665-3 [2394] L665-3-->L670-3: Formula: (and (= 0 v_~T2_E~0_12) (= v_~T2_E~0_11 1)) InVars {~T2_E~0=v_~T2_E~0_12} OutVars{~T2_E~0=v_~T2_E~0_11} AuxVars[] AssignedVars[~T2_E~0] 1068#L670-3 [3761] L670-3-->L675-3: Formula: (> 0 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 1144#L675-3 [2467] L675-3-->L680-3: Formula: (and (= v_~T4_E~0_11 1) (= v_~T4_E~0_12 0)) InVars {~T4_E~0=v_~T4_E~0_12} OutVars{~T4_E~0=v_~T4_E~0_11} AuxVars[] AssignedVars[~T4_E~0] 1145#L680-3 [3776] L680-3-->L685-3: Formula: (< 0 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 1371#L685-3 [3785] L685-3-->L690-3: Formula: (> v_~T6_E~0_13 0) InVars {~T6_E~0=v_~T6_E~0_13} OutVars{~T6_E~0=v_~T6_E~0_13} AuxVars[] AssignedVars[] 1372#L690-3 [3795] L690-3-->L695-3: Formula: (< 0 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 1250#L695-3 [2609] L695-3-->L700-3: Formula: (and (= 0 v_~E_2~0_30) (= v_~E_2~0_29 1)) InVars {~E_2~0=v_~E_2~0_30} OutVars{~E_2~0=v_~E_2~0_29} AuxVars[] AssignedVars[~E_2~0] 1251#L700-3 [3155] L700-3-->L705-3: Formula: (and (= v_~E_3~0_29 1) (= 0 v_~E_3~0_30)) InVars {~E_3~0=v_~E_3~0_30} OutVars{~E_3~0=v_~E_3~0_29} AuxVars[] AssignedVars[~E_3~0] 1313#L705-3 [2688] L705-3-->L710-3: Formula: (and (= v_~E_4~0_29 1) (= 0 v_~E_4~0_30)) InVars {~E_4~0=v_~E_4~0_30} OutVars{~E_4~0=v_~E_4~0_29} AuxVars[] AssignedVars[~E_4~0] 1195#L710-3 [2515] L710-3-->L715-3: Formula: (and (= 0 v_~E_5~0_30) (= v_~E_5~0_29 1)) InVars {~E_5~0=v_~E_5~0_30} OutVars{~E_5~0=v_~E_5~0_29} AuxVars[] AssignedVars[~E_5~0] 1196#L715-3 [3048] L715-3-->L720-3: Formula: (and (= v_~E_6~0_29 1) (= 0 v_~E_6~0_30)) InVars {~E_6~0=v_~E_6~0_30} OutVars{~E_6~0=v_~E_6~0_29} AuxVars[] AssignedVars[~E_6~0] 1058#L720-3 [2388] L720-3-->L310-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_43, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_43, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_25|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_25|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_25|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_43, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_43, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_43, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_25|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_25|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_25|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_25|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_43, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_25|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_43, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_43} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 1059#L310-21 [2779] L310-21-->L311-7: Formula: (= v_~m_pc~0_23 1) InVars {~m_pc~0=v_~m_pc~0_23} OutVars{~m_pc~0=v_~m_pc~0_23} AuxVars[] AssignedVars[] 1336#L311-7 [2720] L311-7-->L321-7: Formula: (and (= v_~M_E~0_31 1) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_46 1)) InVars {~M_E~0=v_~M_E~0_31} OutVars{~M_E~0=v_~M_E~0_31, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_46} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 1337#L321-7 [4303] L321-7-->L815-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 1298#L815-21 [3897] L815-21-->L815-23: Formula: (and (> 0 v_ULTIMATE.start_activate_threads_~tmp~1_47) (= v_~m_st~0_20 0)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_47} OutVars{~m_st~0=v_~m_st~0_20, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_47} AuxVars[] AssignedVars[~m_st~0] 1279#L815-23 [2638] L815-23-->L329-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 1280#L329-21 [3038] L329-21-->L330-7: Formula: (= v_~t1_pc~0_23 1) InVars {~t1_pc~0=v_~t1_pc~0_23} OutVars{~t1_pc~0=v_~t1_pc~0_23} AuxVars[] AssignedVars[] 1475#L330-7 [2981] L330-7-->L340-7: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_52 1) (= 1 v_~E_1~0_32)) InVars {~E_1~0=v_~E_1~0_32} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_52, ~E_1~0=v_~E_1~0_32} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 1390#L340-7 [4310] L340-7-->L823-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 1391#L823-21 [2931] L823-21-->L823-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} AuxVars[] AssignedVars[] 1450#L823-23 [2934] L823-23-->L348-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_25|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 1452#L348-21 [3306] L348-21-->L349-7: Formula: (= 1 v_~t2_pc~0_23) InVars {~t2_pc~0=v_~t2_pc~0_23} OutVars{~t2_pc~0=v_~t2_pc~0_23} AuxVars[] AssignedVars[] 1556#L349-7 [3255] L349-7-->L359-7: Formula: (and (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_52 1) (= 1 v_~E_2~0_32)) InVars {~E_2~0=v_~E_2~0_32} OutVars{~E_2~0=v_~E_2~0_32, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_52} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 1532#L359-7 [4317] L359-7-->L831-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 1173#L831-21 [2490] L831-21-->L831-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} AuxVars[] AssignedVars[] 1174#L831-23 [3197] L831-23-->L367-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_25|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 1084#L367-21 [2409] L367-21-->L368-7: Formula: (= v_~t3_pc~0_23 1) InVars {~t3_pc~0=v_~t3_pc~0_23} OutVars{~t3_pc~0=v_~t3_pc~0_23} AuxVars[] AssignedVars[] 1085#L368-7 [2539] L368-7-->L378-7: Formula: (and (= 1 v_~E_3~0_32) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_52 1)) InVars {~E_3~0=v_~E_3~0_32} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_52, ~E_3~0=v_~E_3~0_32} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 1054#L378-7 [4324] L378-7-->L839-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 1108#L839-21 [4023] L839-21-->L839-23: Formula: (and (= v_~t3_st~0_21 0) (> v_ULTIMATE.start_activate_threads_~tmp___2~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} OutVars{~t3_st~0=v_~t3_st~0_21, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} AuxVars[] AssignedVars[~t3_st~0] 1332#L839-23 [2722] L839-23-->L386-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_49, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 1259#L386-21 [4037] L386-21-->L386-23: Formula: (< 1 v_~t4_pc~0_24) InVars {~t4_pc~0=v_~t4_pc~0_24} OutVars{~t4_pc~0=v_~t4_pc~0_24} AuxVars[] AssignedVars[] 1260#L386-23 [2623] L386-23-->L397-7: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 1266#L397-7 [4331] L397-7-->L847-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 1295#L847-21 [4065] L847-21-->L847-23: Formula: (and (= v_~t4_st~0_22 0) (< v_ULTIMATE.start_activate_threads_~tmp___3~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47, ~t4_st~0=v_~t4_st~0_22} AuxVars[] AssignedVars[~t4_st~0] 1477#L847-23 [2983] L847-23-->L405-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_25|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 1441#L405-21 [2911] L405-21-->L406-7: Formula: (= v_~t5_pc~0_23 1) InVars {~t5_pc~0=v_~t5_pc~0_23} OutVars{~t5_pc~0=v_~t5_pc~0_23} AuxVars[] AssignedVars[] 1427#L406-7 [2874] L406-7-->L416-7: Formula: (and (= 1 v_~E_5~0_32) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_52 1)) InVars {~E_5~0=v_~E_5~0_32} OutVars{~E_5~0=v_~E_5~0_32, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_52} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 1429#L416-7 [4338] L416-7-->L855-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 1446#L855-21 [3251] L855-21-->L855-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} AuxVars[] AssignedVars[] 1555#L855-23 [3257] L855-23-->L424-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_25|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 1542#L424-21 [3173] L424-21-->L425-7: Formula: (= 1 v_~t6_pc~0_23) InVars {~t6_pc~0=v_~t6_pc~0_23} OutVars{~t6_pc~0=v_~t6_pc~0_23} AuxVars[] AssignedVars[] 1524#L425-7 [3114] L425-7-->L435-7: Formula: (and (= 1 v_~E_6~0_32) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_52 1)) InVars {~E_6~0=v_~E_6~0_32} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_52, ~E_6~0=v_~E_6~0_32} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 1168#L435-7 [4340] L435-7-->L863-21: Formula: (and (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___5~0_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_35|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_41|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 1169#L863-21 [4135] L863-21-->L863-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___5~0_47 0) (= v_~t6_st~0_22 0)) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} OutVars{~t6_st~0=v_~t6_st~0_22, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} AuxVars[] AssignedVars[~t6_st~0] 1211#L863-23 [4137] L863-23-->L733-3: Formula: (< v_~M_E~0_35 1) InVars {~M_E~0=v_~M_E~0_35} OutVars{~M_E~0=v_~M_E~0_35} AuxVars[] AssignedVars[] 1212#L733-3 [3184] L733-3-->L738-3: Formula: (and (= v_~T1_E~0_15 1) (= v_~T1_E~0_14 2)) InVars {~T1_E~0=v_~T1_E~0_15} OutVars{~T1_E~0=v_~T1_E~0_14} AuxVars[] AssignedVars[~T1_E~0] 1471#L738-3 [2971] L738-3-->L743-3: Formula: (and (= v_~T2_E~0_14 2) (= 1 v_~T2_E~0_15)) InVars {~T2_E~0=v_~T2_E~0_15} OutVars{~T2_E~0=v_~T2_E~0_14} AuxVars[] AssignedVars[~T2_E~0] 1191#L743-3 [4144] L743-3-->L748-3: Formula: (> 1 v_~T3_E~0_16) InVars {~T3_E~0=v_~T3_E~0_16} OutVars{~T3_E~0=v_~T3_E~0_16} AuxVars[] AssignedVars[] 1192#L748-3 [4145] L748-3-->L753-3: Formula: (> v_~T4_E~0_16 1) InVars {~T4_E~0=v_~T4_E~0_16} OutVars{~T4_E~0=v_~T4_E~0_16} AuxVars[] AssignedVars[] 1049#L753-3 [4147] L753-3-->L758-3: Formula: (> 1 v_~T5_E~0_16) InVars {~T5_E~0=v_~T5_E~0_16} OutVars{~T5_E~0=v_~T5_E~0_16} AuxVars[] AssignedVars[] 1050#L758-3 [4149] L758-3-->L763-3: Formula: (> v_~T6_E~0_16 1) InVars {~T6_E~0=v_~T6_E~0_16} OutVars{~T6_E~0=v_~T6_E~0_16} AuxVars[] AssignedVars[] 1140#L763-3 [4151] L763-3-->L768-3: Formula: (< 1 v_~E_1~0_36) InVars {~E_1~0=v_~E_1~0_36} OutVars{~E_1~0=v_~E_1~0_36} AuxVars[] AssignedVars[] 1141#L768-3 [3219] L768-3-->L773-3: Formula: (and (= 1 v_~E_2~0_35) (= v_~E_2~0_34 2)) InVars {~E_2~0=v_~E_2~0_35} OutVars{~E_2~0=v_~E_2~0_34} AuxVars[] AssignedVars[~E_2~0] 1366#L773-3 [2775] L773-3-->L778-3: Formula: (and (= 1 v_~E_3~0_35) (= v_~E_3~0_34 2)) InVars {~E_3~0=v_~E_3~0_35} OutVars{~E_3~0=v_~E_3~0_34} AuxVars[] AssignedVars[~E_3~0] 1367#L778-3 [3308] L778-3-->L783-3: Formula: (and (= 1 v_~E_4~0_35) (= v_~E_4~0_34 2)) InVars {~E_4~0=v_~E_4~0_35} OutVars{~E_4~0=v_~E_4~0_34} AuxVars[] AssignedVars[~E_4~0] 1262#L783-3 [4160] L783-3-->L788-3: Formula: (< 1 v_~E_5~0_36) InVars {~E_5~0=v_~E_5~0_36} OutVars{~E_5~0=v_~E_5~0_36} AuxVars[] AssignedVars[] 1263#L788-3 [4161] L788-3-->L793-3: Formula: (> 1 v_~E_6~0_36) InVars {~E_6~0=v_~E_6~0_36} OutVars{~E_6~0=v_~E_6~0_36} AuxVars[] AssignedVars[] 1469#L793-3 [2966] L793-3-->L494-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_30} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 1431#L494-1 [2878] L494-1-->L531-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33 1) (= 0 v_~m_st~0_21)) InVars {~m_st~0=v_~m_st~0_21} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33, ~m_st~0=v_~m_st~0_21} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 1128#L531-1 [4341] L531-1-->L1033: Formula: (and (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp~3] 1355#L1033 [4169] L1033-->L1033-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_6) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} AuxVars[] AssignedVars[] 1098#L1033-1 [2919] L1033-1-->L494-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_3|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_6, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_exists_runnable_thread_~__retres1~7, ULTIMATE.start_stop_simulation_#res] 1432#L494-2 [2882] L494-2-->L531-2: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9 1) (= v_~m_st~0_6 0)) InVars {~m_st~0=v_~m_st~0_6} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9, ~m_st~0=v_~m_st~0_6} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 1134#L531-2 [4343] L531-2-->L988: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 1358#L988 [3240] L988-->L995: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 1094#L995 [4354] L995-->L1014-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_6|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_#t~ret17, ULTIMATE.start_stop_simulation_#res] 1095#L1014-1 [2020-06-22 00:12:59,881 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:12:59,881 INFO L82 PathProgramCache]: Analyzing trace with hash -227601337, now seen corresponding path program 1 times [2020-06-22 00:12:59,881 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:12:59,882 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:12:59,883 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:12:59,883 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:12:59,883 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:12:59,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:12:59,919 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:12:59,920 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:12:59,920 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-06-22 00:12:59,920 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-06-22 00:12:59,921 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:12:59,921 INFO L82 PathProgramCache]: Analyzing trace with hash 444577190, now seen corresponding path program 1 times [2020-06-22 00:12:59,921 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:12:59,921 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:12:59,922 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:12:59,922 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:12:59,922 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:12:59,929 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:12:59,959 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:12:59,959 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:12:59,959 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2020-06-22 00:12:59,960 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-06-22 00:12:59,960 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-06-22 00:12:59,960 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-06-22 00:12:59,961 INFO L87 Difference]: Start difference. First operand 518 states and 1142 transitions. cyclomatic complexity: 625 Second operand 3 states. [2020-06-22 00:13:00,598 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-06-22 00:13:00,598 INFO L93 Difference]: Finished difference Result 518 states and 1141 transitions. [2020-06-22 00:13:00,598 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-06-22 00:13:00,599 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 518 states and 1141 transitions. [2020-06-22 00:13:00,604 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 442 [2020-06-22 00:13:00,608 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 518 states to 518 states and 1141 transitions. [2020-06-22 00:13:00,609 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 518 [2020-06-22 00:13:00,610 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 518 [2020-06-22 00:13:00,610 INFO L73 IsDeterministic]: Start isDeterministic. Operand 518 states and 1141 transitions. [2020-06-22 00:13:00,611 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-06-22 00:13:00,611 INFO L706 BuchiCegarLoop]: Abstraction has 518 states and 1141 transitions. [2020-06-22 00:13:00,612 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 518 states and 1141 transitions. [2020-06-22 00:13:00,626 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 518 to 518. [2020-06-22 00:13:00,627 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 518 states. [2020-06-22 00:13:00,628 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 518 states to 518 states and 1141 transitions. [2020-06-22 00:13:00,629 INFO L729 BuchiCegarLoop]: Abstraction has 518 states and 1141 transitions. [2020-06-22 00:13:00,629 INFO L609 BuchiCegarLoop]: Abstraction has 518 states and 1141 transitions. [2020-06-22 00:13:00,629 INFO L442 BuchiCegarLoop]: ======== Iteration 3============ [2020-06-22 00:13:00,629 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 518 states and 1141 transitions. [2020-06-22 00:13:00,632 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 442 [2020-06-22 00:13:00,632 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-06-22 00:13:00,632 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-06-22 00:13:00,634 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:00,634 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:00,636 INFO L794 eck$LassoCheckResult]: Stem: 2527#ULTIMATE.startENTRY [4266] ULTIMATE.startENTRY-->L444: Formula: (and (= 1 v_~t6_i~0_7) (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~M_E~0_37 2) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 0 v_~t6_pc~0_26) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_6~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= v_~T6_E~0_18 2) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~t6_st~0_24) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t6_pc~0=v_~t6_pc~0_26, ~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~T6_E~0=v_~T6_E~0_18, ~M_E~0=v_~M_E~0_37, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ~T4_E~0=v_~T4_E~0_18, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_4|, ~t6_i~0=v_~t6_i~0_7, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ULTIMATE.start_main_~__retres1~8=v_ULTIMATE.start_main_~__retres1~8_6, ~T2_E~0=v_~T2_E~0_18, ~t6_st~0=v_~t6_st~0_24, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_6~0=v_~E_6~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t6_pc~0, ~t5_i~0, ~t1_pc~0, ~t5_st~0, ~T6_E~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ~T4_E~0, ULTIMATE.start_start_simulation_#t~ret17, ~t6_i~0, ~t2_st~0, ~t2_pc~0, ULTIMATE.start_main_~__retres1~8, ~T2_E~0, ~t6_st~0, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_6~0, ULTIMATE.start_main_#res, ~E_2~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 2174#L444 [2453] L444-->L451-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 2175#L451-1 [3640] L451-1-->L456-1: Formula: (and (> 1 v_~t1_i~0_4) (= v_~t1_st~0_3 2)) InVars {~t1_i~0=v_~t1_i~0_4} OutVars{~t1_st~0=v_~t1_st~0_3, ~t1_i~0=v_~t1_i~0_4} AuxVars[] AssignedVars[~t1_st~0] 2263#L456-1 [2574] L456-1-->L461-1: Formula: (and (= v_~t2_st~0_2 0) (= 1 v_~t2_i~0_3)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_2} AuxVars[] AssignedVars[~t2_st~0] 2264#L461-1 [3644] L461-1-->L466-1: Formula: (and (< v_~t3_i~0_4 1) (= v_~t3_st~0_4 2)) InVars {~t3_i~0=v_~t3_i~0_4} OutVars{~t3_st~0=v_~t3_st~0_4, ~t3_i~0=v_~t3_i~0_4} AuxVars[] AssignedVars[~t3_st~0] 2179#L466-1 [3646] L466-1-->L471-1: Formula: (and (< v_~t4_i~0_4 1) (= v_~t4_st~0_5 2)) InVars {~t4_i~0=v_~t4_i~0_4} OutVars{~t4_i~0=v_~t4_i~0_4, ~t4_st~0=v_~t4_st~0_5} AuxVars[] AssignedVars[~t4_st~0] 2180#L471-1 [3647] L471-1-->L476-1: Formula: (and (= v_~t5_st~0_5 2) (< v_~t5_i~0_4 1)) InVars {~t5_i~0=v_~t5_i~0_4} OutVars{~t5_i~0=v_~t5_i~0_4, ~t5_st~0=v_~t5_st~0_5} AuxVars[] AssignedVars[~t5_st~0] 2403#L476-1 [2761] L476-1-->L481-1: Formula: (and (= 1 v_~t6_i~0_3) (= v_~t6_st~0_4 0)) InVars {~t6_i~0=v_~t6_i~0_3} OutVars{~t6_st~0=v_~t6_st~0_4, ~t6_i~0=v_~t6_i~0_3} AuxVars[] AssignedVars[~t6_st~0] 2404#L481-1 [3652] L481-1-->L660-1: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 2538#L660-1 [3654] L660-1-->L665-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 2095#L665-1 [2383] L665-1-->L670-1: Formula: (and (= 0 v_~T2_E~0_3) (= v_~T2_E~0_2 1)) InVars {~T2_E~0=v_~T2_E~0_3} OutVars{~T2_E~0=v_~T2_E~0_2} AuxVars[] AssignedVars[~T2_E~0] 2096#L670-1 [2894] L670-1-->L675-1: Formula: (and (= v_~T3_E~0_2 1) (= v_~T3_E~0_3 0)) InVars {~T3_E~0=v_~T3_E~0_3} OutVars{~T3_E~0=v_~T3_E~0_2} AuxVars[] AssignedVars[~T3_E~0] 2186#L675-1 [3660] L675-1-->L680-1: Formula: (< v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 2187#L680-1 [3662] L680-1-->L685-1: Formula: (< v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 2412#L685-1 [3663] L685-1-->L690-1: Formula: (< 0 v_~T6_E~0_4) InVars {~T6_E~0=v_~T6_E~0_4} OutVars{~T6_E~0=v_~T6_E~0_4} AuxVars[] AssignedVars[] 2413#L690-1 [3310] L690-1-->L695-1: Formula: (and (= v_~E_1~0_5 0) (= v_~E_1~0_4 1)) InVars {~E_1~0=v_~E_1~0_5} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[~E_1~0] 2308#L695-1 [2621] L695-1-->L700-1: Formula: (and (= v_~E_2~0_4 1) (= v_~E_2~0_5 0)) InVars {~E_2~0=v_~E_2~0_5} OutVars{~E_2~0=v_~E_2~0_4} AuxVars[] AssignedVars[~E_2~0] 2309#L700-1 [3180] L700-1-->L705-1: Formula: (and (= v_~E_3~0_5 0) (= v_~E_3~0_4 1)) InVars {~E_3~0=v_~E_3~0_5} OutVars{~E_3~0=v_~E_3~0_4} AuxVars[] AssignedVars[~E_3~0] 2514#L705-1 [3672] L705-1-->L710-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 2247#L710-1 [2525] L710-1-->L715-1: Formula: (and (= v_~E_5~0_3 0) (= v_~E_5~0_2 1)) InVars {~E_5~0=v_~E_5~0_3} OutVars{~E_5~0=v_~E_5~0_2} AuxVars[] AssignedVars[~E_5~0] 2248#L715-1 [3676] L715-1-->L720-1: Formula: (< v_~E_6~0_4 0) InVars {~E_6~0=v_~E_6~0_4} OutVars{~E_6~0=v_~E_6~0_4} AuxVars[] AssignedVars[] 2131#L720-1 [2412] L720-1-->L310: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_7, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_4|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_4|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_7, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_4, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_4, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_2|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_2|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_4|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_4|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_7, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_2|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_4} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 2132#L310 [2597] L310-->L311: Formula: (= v_~m_pc~0_4 1) InVars {~m_pc~0=v_~m_pc~0_4} OutVars{~m_pc~0=v_~m_pc~0_4} AuxVars[] AssignedVars[] 2279#L311 [2732] L311-->L321: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_10 1) (= 1 v_~M_E~0_8)) InVars {~M_E~0=v_~M_E~0_8} OutVars{~M_E~0=v_~M_E~0_8, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_10} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 2274#L321 [4267] L321-->L815: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 2275#L815 [3682] L815-->L815-2: Formula: (and (= v_~m_st~0_5 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_11)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} OutVars{~m_st~0=v_~m_st~0_5, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} AuxVars[] AssignedVars[~m_st~0] 2510#L815-2 [2961] L815-2-->L329: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 2446#L329 [2848] L329-->L330: Formula: (= v_~t1_pc~0_4 1) InVars {~t1_pc~0=v_~t1_pc~0_4} OutVars{~t1_pc~0=v_~t1_pc~0_4} AuxVars[] AssignedVars[] 2447#L330 [3036] L330-->L340: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_10 1) (= v_~E_1~0_7 1)) InVars {~E_1~0=v_~E_1~0_7} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_10, ~E_1~0=v_~E_1~0_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 2441#L340 [4268] L340-->L823: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 2442#L823 [3688] L823-->L823-2: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___0~0_11 0) (= v_~t1_st~0_5 0)) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_11} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_11, ~t1_st~0=v_~t1_st~0_5} AuxVars[] AssignedVars[~t1_st~0] 2596#L823-2 [3235] L823-2-->L348: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_4|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 2580#L348 [3143] L348-->L349: Formula: (= v_~t2_pc~0_4 1) InVars {~t2_pc~0=v_~t2_pc~0_4} OutVars{~t2_pc~0=v_~t2_pc~0_4} AuxVars[] AssignedVars[] 2581#L349 [3267] L349-->L359: Formula: (and (= v_~E_2~0_7 1) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_10 1)) InVars {~E_2~0=v_~E_2~0_7} OutVars{~E_2~0=v_~E_2~0_7, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_10} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 2579#L359 [4269] L359-->L831: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 2254#L831 [3694] L831-->L831-2: Formula: (and (= v_~t2_st~0_5 0) (> v_ULTIMATE.start_activate_threads_~tmp___1~0_11 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_11} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_11, ~t2_st~0=v_~t2_st~0_5} AuxVars[] AssignedVars[~t2_st~0] 2242#L831-2 [2520] L831-2-->L367: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_4|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 2182#L367 [3695] L367-->L367-2: Formula: (> 1 v_~t3_pc~0_5) InVars {~t3_pc~0=v_~t3_pc~0_5} OutVars{~t3_pc~0=v_~t3_pc~0_5} AuxVars[] AssignedVars[] 2160#L367-2 [2438] L367-2-->L378: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 2161#L378 [4270] L378-->L839: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 2181#L839 [2791] L839-->L839-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} AuxVars[] AssignedVars[] 2419#L839-2 [2794] L839-2-->L386: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_7, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 2349#L386 [2675] L386-->L387: Formula: (= v_~t4_pc~0_4 1) InVars {~t4_pc~0=v_~t4_pc~0_4} OutVars{~t4_pc~0=v_~t4_pc~0_4} AuxVars[] AssignedVars[] 2268#L387 [2588] L387-->L397: Formula: (and (= v_~E_4~0_7 1) (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_10 1)) InVars {~E_4~0=v_~E_4~0_7} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_10, ~E_4~0=v_~E_4~0_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 2270#L397 [4271] L397-->L847: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 2348#L847 [3084] L847-->L847-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} AuxVars[] AssignedVars[] 2542#L847-2 [3064] L847-2-->L405: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_4|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 2543#L405 [3708] L405-->L405-2: Formula: (> 1 v_~t5_pc~0_5) InVars {~t5_pc~0=v_~t5_pc~0_5} OutVars{~t5_pc~0=v_~t5_pc~0_5} AuxVars[] AssignedVars[] 2479#L405-2 [2940] L405-2-->L416: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 2478#L416 [4272] L416-->L855: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 2549#L855 [3711] L855-->L855-2: Formula: (and (> v_ULTIMATE.start_activate_threads_~tmp___4~0_11 0) (= v_~t5_st~0_7 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_11} OutVars{~t5_st~0=v_~t5_st~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_11} AuxVars[] AssignedVars[~t5_st~0] 2550#L855-2 [3093] L855-2-->L424: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_4|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 2226#L424 [3714] L424-->L424-2: Formula: (> v_~t6_pc~0_5 1) InVars {~t6_pc~0=v_~t6_pc~0_5} OutVars{~t6_pc~0=v_~t6_pc~0_5} AuxVars[] AssignedVars[] 2227#L424-2 [2503] L424-2-->L435: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 2223#L435 [4273] L435-->L863: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___5~0_49 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_28|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_28|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 2147#L863 [2425] L863-->L863-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___5~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} AuxVars[] AssignedVars[] 2118#L863-2 [3720] L863-2-->L733-1: Formula: (< v_~M_E~0_15 1) InVars {~M_E~0=v_~M_E~0_15} OutVars{~M_E~0=v_~M_E~0_15} AuxVars[] AssignedVars[] 2119#L733-1 [3722] L733-1-->L738-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 2512#L738-1 [3724] L738-1-->L743-1: Formula: (> 1 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 2245#L743-1 [3726] L743-1-->L748-1: Formula: (< 1 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 2246#L748-1 [3727] L748-1-->L753-1: Formula: (< v_~T4_E~0_10 1) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 2126#L753-1 [2407] L753-1-->L758-1: Formula: (and (= v_~T5_E~0_8 2) (= v_~T5_E~0_9 1)) InVars {~T5_E~0=v_~T5_E~0_9} OutVars{~T5_E~0=v_~T5_E~0_8} AuxVars[] AssignedVars[~T5_E~0] 2127#L758-1 [3732] L758-1-->L763-1: Formula: (< v_~T6_E~0_10 1) InVars {~T6_E~0=v_~T6_E~0_10} OutVars{~T6_E~0=v_~T6_E~0_10} AuxVars[] AssignedVars[] 2198#L763-1 [2475] L763-1-->L768-1: Formula: (and (= v_~E_1~0_12 2) (= 1 v_~E_1~0_13)) InVars {~E_1~0=v_~E_1~0_13} OutVars{~E_1~0=v_~E_1~0_12} AuxVars[] AssignedVars[~E_1~0] 2199#L768-1 [3736] L768-1-->L773-1: Formula: (< 1 v_~E_2~0_14) InVars {~E_2~0=v_~E_2~0_14} OutVars{~E_2~0=v_~E_2~0_14} AuxVars[] AssignedVars[] 2407#L773-1 [2767] L773-1-->L778-1: Formula: (and (= 1 v_~E_3~0_13) (= v_~E_3~0_12 2)) InVars {~E_3~0=v_~E_3~0_13} OutVars{~E_3~0=v_~E_3~0_12} AuxVars[] AssignedVars[~E_3~0] 2408#L778-1 [3740] L778-1-->L783-1: Formula: (< 1 v_~E_4~0_14) InVars {~E_4~0=v_~E_4~0_14} OutVars{~E_4~0=v_~E_4~0_14} AuxVars[] AssignedVars[] 2299#L783-1 [3742] L783-1-->L788-1: Formula: (> 1 v_~E_5~0_14) InVars {~E_5~0=v_~E_5~0_14} OutVars{~E_5~0=v_~E_5~0_14} AuxVars[] AssignedVars[] 2300#L788-1 [3743] L788-1-->L1014-1: Formula: (> 1 v_~E_6~0_14) InVars {~E_6~0=v_~E_6~0_14} OutVars{~E_6~0=v_~E_6~0_14} AuxVars[] AssignedVars[] 2139#L1014-1 [2020-06-22 00:13:00,637 INFO L796 eck$LassoCheckResult]: Loop: 2139#L1014-1 [4274] L1014-1-->L635: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp_ndt_7~0=v_ULTIMATE.start_eval_~tmp_ndt_7~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp_ndt_7~0] 2101#L635 [4275] L635-->L494: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_37} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 2474#L494 [2876] L494-->L531: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21 1) (= v_~m_st~0_8 0)) InVars {~m_st~0=v_~m_st~0_8} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21, ~m_st~0=v_~m_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 2170#L531 [4276] L531-->L546: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 2396#L546 [4278] L546-->L660-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 2539#L660-2 [3747] L660-2-->L660-4: Formula: (> v_~M_E~0_30 0) InVars {~M_E~0=v_~M_E~0_30} OutVars{~M_E~0=v_~M_E~0_30} AuxVars[] AssignedVars[] 2540#L660-4 [3058] L660-4-->L665-3: Formula: (and (= v_~T1_E~0_11 1) (= v_~T1_E~0_12 0)) InVars {~T1_E~0=v_~T1_E~0_12} OutVars{~T1_E~0=v_~T1_E~0_11} AuxVars[] AssignedVars[~T1_E~0] 2111#L665-3 [2394] L665-3-->L670-3: Formula: (and (= 0 v_~T2_E~0_12) (= v_~T2_E~0_11 1)) InVars {~T2_E~0=v_~T2_E~0_12} OutVars{~T2_E~0=v_~T2_E~0_11} AuxVars[] AssignedVars[~T2_E~0] 2112#L670-3 [3761] L670-3-->L675-3: Formula: (> 0 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 2188#L675-3 [2467] L675-3-->L680-3: Formula: (and (= v_~T4_E~0_11 1) (= v_~T4_E~0_12 0)) InVars {~T4_E~0=v_~T4_E~0_12} OutVars{~T4_E~0=v_~T4_E~0_11} AuxVars[] AssignedVars[~T4_E~0] 2189#L680-3 [3776] L680-3-->L685-3: Formula: (< 0 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 2415#L685-3 [3785] L685-3-->L690-3: Formula: (> v_~T6_E~0_13 0) InVars {~T6_E~0=v_~T6_E~0_13} OutVars{~T6_E~0=v_~T6_E~0_13} AuxVars[] AssignedVars[] 2416#L690-3 [3795] L690-3-->L695-3: Formula: (< 0 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 2294#L695-3 [2609] L695-3-->L700-3: Formula: (and (= 0 v_~E_2~0_30) (= v_~E_2~0_29 1)) InVars {~E_2~0=v_~E_2~0_30} OutVars{~E_2~0=v_~E_2~0_29} AuxVars[] AssignedVars[~E_2~0] 2295#L700-3 [3155] L700-3-->L705-3: Formula: (and (= v_~E_3~0_29 1) (= 0 v_~E_3~0_30)) InVars {~E_3~0=v_~E_3~0_30} OutVars{~E_3~0=v_~E_3~0_29} AuxVars[] AssignedVars[~E_3~0] 2357#L705-3 [2688] L705-3-->L710-3: Formula: (and (= v_~E_4~0_29 1) (= 0 v_~E_4~0_30)) InVars {~E_4~0=v_~E_4~0_30} OutVars{~E_4~0=v_~E_4~0_29} AuxVars[] AssignedVars[~E_4~0] 2239#L710-3 [2515] L710-3-->L715-3: Formula: (and (= 0 v_~E_5~0_30) (= v_~E_5~0_29 1)) InVars {~E_5~0=v_~E_5~0_30} OutVars{~E_5~0=v_~E_5~0_29} AuxVars[] AssignedVars[~E_5~0] 2240#L715-3 [3048] L715-3-->L720-3: Formula: (and (= v_~E_6~0_29 1) (= 0 v_~E_6~0_30)) InVars {~E_6~0=v_~E_6~0_30} OutVars{~E_6~0=v_~E_6~0_29} AuxVars[] AssignedVars[~E_6~0] 2102#L720-3 [2388] L720-3-->L310-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_43, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_43, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_25|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_25|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_25|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_43, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_43, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_43, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_25|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_25|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_25|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_25|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_43, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_25|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_43, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_43} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 2103#L310-21 [2779] L310-21-->L311-7: Formula: (= v_~m_pc~0_23 1) InVars {~m_pc~0=v_~m_pc~0_23} OutVars{~m_pc~0=v_~m_pc~0_23} AuxVars[] AssignedVars[] 2380#L311-7 [2720] L311-7-->L321-7: Formula: (and (= v_~M_E~0_31 1) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_46 1)) InVars {~M_E~0=v_~M_E~0_31} OutVars{~M_E~0=v_~M_E~0_31, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_46} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 2381#L321-7 [4303] L321-7-->L815-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 2342#L815-21 [3897] L815-21-->L815-23: Formula: (and (> 0 v_ULTIMATE.start_activate_threads_~tmp~1_47) (= v_~m_st~0_20 0)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_47} OutVars{~m_st~0=v_~m_st~0_20, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_47} AuxVars[] AssignedVars[~m_st~0] 2323#L815-23 [2638] L815-23-->L329-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 2324#L329-21 [3038] L329-21-->L330-7: Formula: (= v_~t1_pc~0_23 1) InVars {~t1_pc~0=v_~t1_pc~0_23} OutVars{~t1_pc~0=v_~t1_pc~0_23} AuxVars[] AssignedVars[] 2519#L330-7 [2981] L330-7-->L340-7: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_52 1) (= 1 v_~E_1~0_32)) InVars {~E_1~0=v_~E_1~0_32} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_52, ~E_1~0=v_~E_1~0_32} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 2434#L340-7 [4310] L340-7-->L823-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 2435#L823-21 [2931] L823-21-->L823-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} AuxVars[] AssignedVars[] 2494#L823-23 [2934] L823-23-->L348-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_25|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 2496#L348-21 [3306] L348-21-->L349-7: Formula: (= 1 v_~t2_pc~0_23) InVars {~t2_pc~0=v_~t2_pc~0_23} OutVars{~t2_pc~0=v_~t2_pc~0_23} AuxVars[] AssignedVars[] 2600#L349-7 [3255] L349-7-->L359-7: Formula: (and (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_52 1) (= 1 v_~E_2~0_32)) InVars {~E_2~0=v_~E_2~0_32} OutVars{~E_2~0=v_~E_2~0_32, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_52} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 2576#L359-7 [4317] L359-7-->L831-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 2217#L831-21 [2490] L831-21-->L831-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} AuxVars[] AssignedVars[] 2218#L831-23 [3197] L831-23-->L367-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_25|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 2128#L367-21 [2409] L367-21-->L368-7: Formula: (= v_~t3_pc~0_23 1) InVars {~t3_pc~0=v_~t3_pc~0_23} OutVars{~t3_pc~0=v_~t3_pc~0_23} AuxVars[] AssignedVars[] 2129#L368-7 [2539] L368-7-->L378-7: Formula: (and (= 1 v_~E_3~0_32) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_52 1)) InVars {~E_3~0=v_~E_3~0_32} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_52, ~E_3~0=v_~E_3~0_32} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 2098#L378-7 [4324] L378-7-->L839-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 2152#L839-21 [4023] L839-21-->L839-23: Formula: (and (= v_~t3_st~0_21 0) (> v_ULTIMATE.start_activate_threads_~tmp___2~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} OutVars{~t3_st~0=v_~t3_st~0_21, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} AuxVars[] AssignedVars[~t3_st~0] 2376#L839-23 [2722] L839-23-->L386-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_49, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 2303#L386-21 [4037] L386-21-->L386-23: Formula: (< 1 v_~t4_pc~0_24) InVars {~t4_pc~0=v_~t4_pc~0_24} OutVars{~t4_pc~0=v_~t4_pc~0_24} AuxVars[] AssignedVars[] 2304#L386-23 [2623] L386-23-->L397-7: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 2310#L397-7 [4331] L397-7-->L847-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 2339#L847-21 [4065] L847-21-->L847-23: Formula: (and (= v_~t4_st~0_22 0) (< v_ULTIMATE.start_activate_threads_~tmp___3~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47, ~t4_st~0=v_~t4_st~0_22} AuxVars[] AssignedVars[~t4_st~0] 2521#L847-23 [2983] L847-23-->L405-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_25|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 2485#L405-21 [2911] L405-21-->L406-7: Formula: (= v_~t5_pc~0_23 1) InVars {~t5_pc~0=v_~t5_pc~0_23} OutVars{~t5_pc~0=v_~t5_pc~0_23} AuxVars[] AssignedVars[] 2471#L406-7 [2874] L406-7-->L416-7: Formula: (and (= 1 v_~E_5~0_32) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_52 1)) InVars {~E_5~0=v_~E_5~0_32} OutVars{~E_5~0=v_~E_5~0_32, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_52} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 2473#L416-7 [4338] L416-7-->L855-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 2490#L855-21 [3251] L855-21-->L855-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} AuxVars[] AssignedVars[] 2599#L855-23 [3257] L855-23-->L424-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_25|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 2586#L424-21 [3173] L424-21-->L425-7: Formula: (= 1 v_~t6_pc~0_23) InVars {~t6_pc~0=v_~t6_pc~0_23} OutVars{~t6_pc~0=v_~t6_pc~0_23} AuxVars[] AssignedVars[] 2568#L425-7 [3114] L425-7-->L435-7: Formula: (and (= 1 v_~E_6~0_32) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_52 1)) InVars {~E_6~0=v_~E_6~0_32} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_52, ~E_6~0=v_~E_6~0_32} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 2212#L435-7 [4340] L435-7-->L863-21: Formula: (and (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___5~0_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_35|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_41|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 2213#L863-21 [4135] L863-21-->L863-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___5~0_47 0) (= v_~t6_st~0_22 0)) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} OutVars{~t6_st~0=v_~t6_st~0_22, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} AuxVars[] AssignedVars[~t6_st~0] 2255#L863-23 [4137] L863-23-->L733-3: Formula: (< v_~M_E~0_35 1) InVars {~M_E~0=v_~M_E~0_35} OutVars{~M_E~0=v_~M_E~0_35} AuxVars[] AssignedVars[] 2256#L733-3 [3184] L733-3-->L738-3: Formula: (and (= v_~T1_E~0_15 1) (= v_~T1_E~0_14 2)) InVars {~T1_E~0=v_~T1_E~0_15} OutVars{~T1_E~0=v_~T1_E~0_14} AuxVars[] AssignedVars[~T1_E~0] 2515#L738-3 [2971] L738-3-->L743-3: Formula: (and (= v_~T2_E~0_14 2) (= 1 v_~T2_E~0_15)) InVars {~T2_E~0=v_~T2_E~0_15} OutVars{~T2_E~0=v_~T2_E~0_14} AuxVars[] AssignedVars[~T2_E~0] 2235#L743-3 [4144] L743-3-->L748-3: Formula: (> 1 v_~T3_E~0_16) InVars {~T3_E~0=v_~T3_E~0_16} OutVars{~T3_E~0=v_~T3_E~0_16} AuxVars[] AssignedVars[] 2236#L748-3 [4145] L748-3-->L753-3: Formula: (> v_~T4_E~0_16 1) InVars {~T4_E~0=v_~T4_E~0_16} OutVars{~T4_E~0=v_~T4_E~0_16} AuxVars[] AssignedVars[] 2093#L753-3 [4147] L753-3-->L758-3: Formula: (> 1 v_~T5_E~0_16) InVars {~T5_E~0=v_~T5_E~0_16} OutVars{~T5_E~0=v_~T5_E~0_16} AuxVars[] AssignedVars[] 2094#L758-3 [4149] L758-3-->L763-3: Formula: (> v_~T6_E~0_16 1) InVars {~T6_E~0=v_~T6_E~0_16} OutVars{~T6_E~0=v_~T6_E~0_16} AuxVars[] AssignedVars[] 2184#L763-3 [4151] L763-3-->L768-3: Formula: (< 1 v_~E_1~0_36) InVars {~E_1~0=v_~E_1~0_36} OutVars{~E_1~0=v_~E_1~0_36} AuxVars[] AssignedVars[] 2185#L768-3 [3219] L768-3-->L773-3: Formula: (and (= 1 v_~E_2~0_35) (= v_~E_2~0_34 2)) InVars {~E_2~0=v_~E_2~0_35} OutVars{~E_2~0=v_~E_2~0_34} AuxVars[] AssignedVars[~E_2~0] 2410#L773-3 [2775] L773-3-->L778-3: Formula: (and (= 1 v_~E_3~0_35) (= v_~E_3~0_34 2)) InVars {~E_3~0=v_~E_3~0_35} OutVars{~E_3~0=v_~E_3~0_34} AuxVars[] AssignedVars[~E_3~0] 2411#L778-3 [3308] L778-3-->L783-3: Formula: (and (= 1 v_~E_4~0_35) (= v_~E_4~0_34 2)) InVars {~E_4~0=v_~E_4~0_35} OutVars{~E_4~0=v_~E_4~0_34} AuxVars[] AssignedVars[~E_4~0] 2306#L783-3 [4160] L783-3-->L788-3: Formula: (< 1 v_~E_5~0_36) InVars {~E_5~0=v_~E_5~0_36} OutVars{~E_5~0=v_~E_5~0_36} AuxVars[] AssignedVars[] 2307#L788-3 [4161] L788-3-->L793-3: Formula: (> 1 v_~E_6~0_36) InVars {~E_6~0=v_~E_6~0_36} OutVars{~E_6~0=v_~E_6~0_36} AuxVars[] AssignedVars[] 2513#L793-3 [2966] L793-3-->L494-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_30} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 2475#L494-1 [2878] L494-1-->L531-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33 1) (= 0 v_~m_st~0_21)) InVars {~m_st~0=v_~m_st~0_21} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33, ~m_st~0=v_~m_st~0_21} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 2172#L531-1 [4341] L531-1-->L1033: Formula: (and (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp~3] 2399#L1033 [4169] L1033-->L1033-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_6) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} AuxVars[] AssignedVars[] 2142#L1033-1 [2919] L1033-1-->L494-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_3|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_6, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_exists_runnable_thread_~__retres1~7, ULTIMATE.start_stop_simulation_#res] 2476#L494-2 [2882] L494-2-->L531-2: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9 1) (= v_~m_st~0_6 0)) InVars {~m_st~0=v_~m_st~0_6} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9, ~m_st~0=v_~m_st~0_6} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 2178#L531-2 [4343] L531-2-->L988: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 2402#L988 [3240] L988-->L995: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 2138#L995 [4354] L995-->L1014-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_6|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_#t~ret17, ULTIMATE.start_stop_simulation_#res] 2139#L1014-1 [2020-06-22 00:13:00,638 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:00,638 INFO L82 PathProgramCache]: Analyzing trace with hash 1975508199, now seen corresponding path program 1 times [2020-06-22 00:13:00,638 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:00,638 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:00,640 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:00,640 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:00,640 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:00,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:00,678 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:00,679 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:00,679 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-06-22 00:13:00,679 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-06-22 00:13:00,680 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:00,680 INFO L82 PathProgramCache]: Analyzing trace with hash 444577190, now seen corresponding path program 2 times [2020-06-22 00:13:00,680 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:00,680 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:00,681 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:00,681 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:00,681 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:00,686 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:00,724 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:00,725 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:00,725 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2020-06-22 00:13:00,725 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-06-22 00:13:00,725 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-06-22 00:13:00,725 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-06-22 00:13:00,726 INFO L87 Difference]: Start difference. First operand 518 states and 1141 transitions. cyclomatic complexity: 624 Second operand 3 states. [2020-06-22 00:13:01,400 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-06-22 00:13:01,400 INFO L93 Difference]: Finished difference Result 518 states and 1140 transitions. [2020-06-22 00:13:01,400 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-06-22 00:13:01,401 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 518 states and 1140 transitions. [2020-06-22 00:13:01,405 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 442 [2020-06-22 00:13:01,409 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 518 states to 518 states and 1140 transitions. [2020-06-22 00:13:01,409 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 518 [2020-06-22 00:13:01,410 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 518 [2020-06-22 00:13:01,410 INFO L73 IsDeterministic]: Start isDeterministic. Operand 518 states and 1140 transitions. [2020-06-22 00:13:01,411 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-06-22 00:13:01,411 INFO L706 BuchiCegarLoop]: Abstraction has 518 states and 1140 transitions. [2020-06-22 00:13:01,412 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 518 states and 1140 transitions. [2020-06-22 00:13:01,421 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 518 to 518. [2020-06-22 00:13:01,421 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 518 states. [2020-06-22 00:13:01,423 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 518 states to 518 states and 1140 transitions. [2020-06-22 00:13:01,423 INFO L729 BuchiCegarLoop]: Abstraction has 518 states and 1140 transitions. [2020-06-22 00:13:01,423 INFO L609 BuchiCegarLoop]: Abstraction has 518 states and 1140 transitions. [2020-06-22 00:13:01,423 INFO L442 BuchiCegarLoop]: ======== Iteration 4============ [2020-06-22 00:13:01,423 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 518 states and 1140 transitions. [2020-06-22 00:13:01,426 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 442 [2020-06-22 00:13:01,426 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-06-22 00:13:01,426 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-06-22 00:13:01,428 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:01,428 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:01,429 INFO L794 eck$LassoCheckResult]: Stem: 3571#ULTIMATE.startENTRY [4266] ULTIMATE.startENTRY-->L444: Formula: (and (= 1 v_~t6_i~0_7) (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~M_E~0_37 2) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 0 v_~t6_pc~0_26) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_6~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= v_~T6_E~0_18 2) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~t6_st~0_24) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t6_pc~0=v_~t6_pc~0_26, ~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~T6_E~0=v_~T6_E~0_18, ~M_E~0=v_~M_E~0_37, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ~T4_E~0=v_~T4_E~0_18, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_4|, ~t6_i~0=v_~t6_i~0_7, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ULTIMATE.start_main_~__retres1~8=v_ULTIMATE.start_main_~__retres1~8_6, ~T2_E~0=v_~T2_E~0_18, ~t6_st~0=v_~t6_st~0_24, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_6~0=v_~E_6~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t6_pc~0, ~t5_i~0, ~t1_pc~0, ~t5_st~0, ~T6_E~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ~T4_E~0, ULTIMATE.start_start_simulation_#t~ret17, ~t6_i~0, ~t2_st~0, ~t2_pc~0, ULTIMATE.start_main_~__retres1~8, ~T2_E~0, ~t6_st~0, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_6~0, ULTIMATE.start_main_#res, ~E_2~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 3221#L444 [2453] L444-->L451-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 3222#L451-1 [3639] L451-1-->L456-1: Formula: (and (< 1 v_~t1_i~0_4) (= v_~t1_st~0_3 2)) InVars {~t1_i~0=v_~t1_i~0_4} OutVars{~t1_st~0=v_~t1_st~0_3, ~t1_i~0=v_~t1_i~0_4} AuxVars[] AssignedVars[~t1_st~0] 3307#L456-1 [2574] L456-1-->L461-1: Formula: (and (= v_~t2_st~0_2 0) (= 1 v_~t2_i~0_3)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_2} AuxVars[] AssignedVars[~t2_st~0] 3308#L461-1 [3644] L461-1-->L466-1: Formula: (and (< v_~t3_i~0_4 1) (= v_~t3_st~0_4 2)) InVars {~t3_i~0=v_~t3_i~0_4} OutVars{~t3_st~0=v_~t3_st~0_4, ~t3_i~0=v_~t3_i~0_4} AuxVars[] AssignedVars[~t3_st~0] 3223#L466-1 [3646] L466-1-->L471-1: Formula: (and (< v_~t4_i~0_4 1) (= v_~t4_st~0_5 2)) InVars {~t4_i~0=v_~t4_i~0_4} OutVars{~t4_i~0=v_~t4_i~0_4, ~t4_st~0=v_~t4_st~0_5} AuxVars[] AssignedVars[~t4_st~0] 3224#L471-1 [3647] L471-1-->L476-1: Formula: (and (= v_~t5_st~0_5 2) (< v_~t5_i~0_4 1)) InVars {~t5_i~0=v_~t5_i~0_4} OutVars{~t5_i~0=v_~t5_i~0_4, ~t5_st~0=v_~t5_st~0_5} AuxVars[] AssignedVars[~t5_st~0] 3447#L476-1 [2761] L476-1-->L481-1: Formula: (and (= 1 v_~t6_i~0_3) (= v_~t6_st~0_4 0)) InVars {~t6_i~0=v_~t6_i~0_3} OutVars{~t6_st~0=v_~t6_st~0_4, ~t6_i~0=v_~t6_i~0_3} AuxVars[] AssignedVars[~t6_st~0] 3448#L481-1 [3652] L481-1-->L660-1: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 3582#L660-1 [3654] L660-1-->L665-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 3139#L665-1 [2383] L665-1-->L670-1: Formula: (and (= 0 v_~T2_E~0_3) (= v_~T2_E~0_2 1)) InVars {~T2_E~0=v_~T2_E~0_3} OutVars{~T2_E~0=v_~T2_E~0_2} AuxVars[] AssignedVars[~T2_E~0] 3140#L670-1 [2894] L670-1-->L675-1: Formula: (and (= v_~T3_E~0_2 1) (= v_~T3_E~0_3 0)) InVars {~T3_E~0=v_~T3_E~0_3} OutVars{~T3_E~0=v_~T3_E~0_2} AuxVars[] AssignedVars[~T3_E~0] 3230#L675-1 [3660] L675-1-->L680-1: Formula: (< v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 3231#L680-1 [3662] L680-1-->L685-1: Formula: (< v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 3456#L685-1 [3663] L685-1-->L690-1: Formula: (< 0 v_~T6_E~0_4) InVars {~T6_E~0=v_~T6_E~0_4} OutVars{~T6_E~0=v_~T6_E~0_4} AuxVars[] AssignedVars[] 3457#L690-1 [3310] L690-1-->L695-1: Formula: (and (= v_~E_1~0_5 0) (= v_~E_1~0_4 1)) InVars {~E_1~0=v_~E_1~0_5} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[~E_1~0] 3352#L695-1 [2621] L695-1-->L700-1: Formula: (and (= v_~E_2~0_4 1) (= v_~E_2~0_5 0)) InVars {~E_2~0=v_~E_2~0_5} OutVars{~E_2~0=v_~E_2~0_4} AuxVars[] AssignedVars[~E_2~0] 3353#L700-1 [3180] L700-1-->L705-1: Formula: (and (= v_~E_3~0_5 0) (= v_~E_3~0_4 1)) InVars {~E_3~0=v_~E_3~0_5} OutVars{~E_3~0=v_~E_3~0_4} AuxVars[] AssignedVars[~E_3~0] 3558#L705-1 [3672] L705-1-->L710-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 3291#L710-1 [2525] L710-1-->L715-1: Formula: (and (= v_~E_5~0_3 0) (= v_~E_5~0_2 1)) InVars {~E_5~0=v_~E_5~0_3} OutVars{~E_5~0=v_~E_5~0_2} AuxVars[] AssignedVars[~E_5~0] 3292#L715-1 [3676] L715-1-->L720-1: Formula: (< v_~E_6~0_4 0) InVars {~E_6~0=v_~E_6~0_4} OutVars{~E_6~0=v_~E_6~0_4} AuxVars[] AssignedVars[] 3175#L720-1 [2412] L720-1-->L310: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_7, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_4|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_4|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_7, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_4, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_4, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_2|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_2|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_4|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_4|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_7, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_2|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_4} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 3176#L310 [2597] L310-->L311: Formula: (= v_~m_pc~0_4 1) InVars {~m_pc~0=v_~m_pc~0_4} OutVars{~m_pc~0=v_~m_pc~0_4} AuxVars[] AssignedVars[] 3323#L311 [2732] L311-->L321: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_10 1) (= 1 v_~M_E~0_8)) InVars {~M_E~0=v_~M_E~0_8} OutVars{~M_E~0=v_~M_E~0_8, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_10} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 3318#L321 [4267] L321-->L815: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 3319#L815 [3682] L815-->L815-2: Formula: (and (= v_~m_st~0_5 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_11)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} OutVars{~m_st~0=v_~m_st~0_5, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} AuxVars[] AssignedVars[~m_st~0] 3554#L815-2 [2961] L815-2-->L329: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 3490#L329 [2848] L329-->L330: Formula: (= v_~t1_pc~0_4 1) InVars {~t1_pc~0=v_~t1_pc~0_4} OutVars{~t1_pc~0=v_~t1_pc~0_4} AuxVars[] AssignedVars[] 3491#L330 [3036] L330-->L340: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_10 1) (= v_~E_1~0_7 1)) InVars {~E_1~0=v_~E_1~0_7} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_10, ~E_1~0=v_~E_1~0_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 3485#L340 [4268] L340-->L823: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 3486#L823 [3688] L823-->L823-2: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___0~0_11 0) (= v_~t1_st~0_5 0)) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_11} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_11, ~t1_st~0=v_~t1_st~0_5} AuxVars[] AssignedVars[~t1_st~0] 3640#L823-2 [3235] L823-2-->L348: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_4|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 3624#L348 [3143] L348-->L349: Formula: (= v_~t2_pc~0_4 1) InVars {~t2_pc~0=v_~t2_pc~0_4} OutVars{~t2_pc~0=v_~t2_pc~0_4} AuxVars[] AssignedVars[] 3625#L349 [3267] L349-->L359: Formula: (and (= v_~E_2~0_7 1) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_10 1)) InVars {~E_2~0=v_~E_2~0_7} OutVars{~E_2~0=v_~E_2~0_7, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_10} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 3623#L359 [4269] L359-->L831: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 3298#L831 [3694] L831-->L831-2: Formula: (and (= v_~t2_st~0_5 0) (> v_ULTIMATE.start_activate_threads_~tmp___1~0_11 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_11} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_11, ~t2_st~0=v_~t2_st~0_5} AuxVars[] AssignedVars[~t2_st~0] 3286#L831-2 [2520] L831-2-->L367: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_4|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 3226#L367 [3695] L367-->L367-2: Formula: (> 1 v_~t3_pc~0_5) InVars {~t3_pc~0=v_~t3_pc~0_5} OutVars{~t3_pc~0=v_~t3_pc~0_5} AuxVars[] AssignedVars[] 3204#L367-2 [2438] L367-2-->L378: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 3205#L378 [4270] L378-->L839: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 3225#L839 [2791] L839-->L839-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} AuxVars[] AssignedVars[] 3463#L839-2 [2794] L839-2-->L386: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_7, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 3393#L386 [2675] L386-->L387: Formula: (= v_~t4_pc~0_4 1) InVars {~t4_pc~0=v_~t4_pc~0_4} OutVars{~t4_pc~0=v_~t4_pc~0_4} AuxVars[] AssignedVars[] 3312#L387 [2588] L387-->L397: Formula: (and (= v_~E_4~0_7 1) (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_10 1)) InVars {~E_4~0=v_~E_4~0_7} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_10, ~E_4~0=v_~E_4~0_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 3314#L397 [4271] L397-->L847: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 3392#L847 [3084] L847-->L847-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} AuxVars[] AssignedVars[] 3586#L847-2 [3064] L847-2-->L405: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_4|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 3587#L405 [3708] L405-->L405-2: Formula: (> 1 v_~t5_pc~0_5) InVars {~t5_pc~0=v_~t5_pc~0_5} OutVars{~t5_pc~0=v_~t5_pc~0_5} AuxVars[] AssignedVars[] 3523#L405-2 [2940] L405-2-->L416: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 3522#L416 [4272] L416-->L855: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 3593#L855 [3711] L855-->L855-2: Formula: (and (> v_ULTIMATE.start_activate_threads_~tmp___4~0_11 0) (= v_~t5_st~0_7 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_11} OutVars{~t5_st~0=v_~t5_st~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_11} AuxVars[] AssignedVars[~t5_st~0] 3594#L855-2 [3093] L855-2-->L424: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_4|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 3270#L424 [3714] L424-->L424-2: Formula: (> v_~t6_pc~0_5 1) InVars {~t6_pc~0=v_~t6_pc~0_5} OutVars{~t6_pc~0=v_~t6_pc~0_5} AuxVars[] AssignedVars[] 3271#L424-2 [2503] L424-2-->L435: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 3267#L435 [4273] L435-->L863: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___5~0_49 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_28|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_28|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 3191#L863 [2425] L863-->L863-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___5~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} AuxVars[] AssignedVars[] 3162#L863-2 [3720] L863-2-->L733-1: Formula: (< v_~M_E~0_15 1) InVars {~M_E~0=v_~M_E~0_15} OutVars{~M_E~0=v_~M_E~0_15} AuxVars[] AssignedVars[] 3163#L733-1 [3722] L733-1-->L738-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 3556#L738-1 [3724] L738-1-->L743-1: Formula: (> 1 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 3289#L743-1 [3726] L743-1-->L748-1: Formula: (< 1 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 3290#L748-1 [3727] L748-1-->L753-1: Formula: (< v_~T4_E~0_10 1) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 3170#L753-1 [2407] L753-1-->L758-1: Formula: (and (= v_~T5_E~0_8 2) (= v_~T5_E~0_9 1)) InVars {~T5_E~0=v_~T5_E~0_9} OutVars{~T5_E~0=v_~T5_E~0_8} AuxVars[] AssignedVars[~T5_E~0] 3171#L758-1 [3732] L758-1-->L763-1: Formula: (< v_~T6_E~0_10 1) InVars {~T6_E~0=v_~T6_E~0_10} OutVars{~T6_E~0=v_~T6_E~0_10} AuxVars[] AssignedVars[] 3242#L763-1 [2475] L763-1-->L768-1: Formula: (and (= v_~E_1~0_12 2) (= 1 v_~E_1~0_13)) InVars {~E_1~0=v_~E_1~0_13} OutVars{~E_1~0=v_~E_1~0_12} AuxVars[] AssignedVars[~E_1~0] 3243#L768-1 [3736] L768-1-->L773-1: Formula: (< 1 v_~E_2~0_14) InVars {~E_2~0=v_~E_2~0_14} OutVars{~E_2~0=v_~E_2~0_14} AuxVars[] AssignedVars[] 3451#L773-1 [2767] L773-1-->L778-1: Formula: (and (= 1 v_~E_3~0_13) (= v_~E_3~0_12 2)) InVars {~E_3~0=v_~E_3~0_13} OutVars{~E_3~0=v_~E_3~0_12} AuxVars[] AssignedVars[~E_3~0] 3452#L778-1 [3740] L778-1-->L783-1: Formula: (< 1 v_~E_4~0_14) InVars {~E_4~0=v_~E_4~0_14} OutVars{~E_4~0=v_~E_4~0_14} AuxVars[] AssignedVars[] 3343#L783-1 [3742] L783-1-->L788-1: Formula: (> 1 v_~E_5~0_14) InVars {~E_5~0=v_~E_5~0_14} OutVars{~E_5~0=v_~E_5~0_14} AuxVars[] AssignedVars[] 3344#L788-1 [3743] L788-1-->L1014-1: Formula: (> 1 v_~E_6~0_14) InVars {~E_6~0=v_~E_6~0_14} OutVars{~E_6~0=v_~E_6~0_14} AuxVars[] AssignedVars[] 3180#L1014-1 [2020-06-22 00:13:01,431 INFO L796 eck$LassoCheckResult]: Loop: 3180#L1014-1 [4274] L1014-1-->L635: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp_ndt_7~0=v_ULTIMATE.start_eval_~tmp_ndt_7~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp_ndt_7~0] 3145#L635 [4275] L635-->L494: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_37} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 3518#L494 [2876] L494-->L531: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21 1) (= v_~m_st~0_8 0)) InVars {~m_st~0=v_~m_st~0_8} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21, ~m_st~0=v_~m_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 3214#L531 [4276] L531-->L546: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 3440#L546 [4278] L546-->L660-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 3583#L660-2 [3747] L660-2-->L660-4: Formula: (> v_~M_E~0_30 0) InVars {~M_E~0=v_~M_E~0_30} OutVars{~M_E~0=v_~M_E~0_30} AuxVars[] AssignedVars[] 3584#L660-4 [3058] L660-4-->L665-3: Formula: (and (= v_~T1_E~0_11 1) (= v_~T1_E~0_12 0)) InVars {~T1_E~0=v_~T1_E~0_12} OutVars{~T1_E~0=v_~T1_E~0_11} AuxVars[] AssignedVars[~T1_E~0] 3155#L665-3 [2394] L665-3-->L670-3: Formula: (and (= 0 v_~T2_E~0_12) (= v_~T2_E~0_11 1)) InVars {~T2_E~0=v_~T2_E~0_12} OutVars{~T2_E~0=v_~T2_E~0_11} AuxVars[] AssignedVars[~T2_E~0] 3156#L670-3 [3761] L670-3-->L675-3: Formula: (> 0 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 3232#L675-3 [2467] L675-3-->L680-3: Formula: (and (= v_~T4_E~0_11 1) (= v_~T4_E~0_12 0)) InVars {~T4_E~0=v_~T4_E~0_12} OutVars{~T4_E~0=v_~T4_E~0_11} AuxVars[] AssignedVars[~T4_E~0] 3233#L680-3 [3776] L680-3-->L685-3: Formula: (< 0 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 3459#L685-3 [3785] L685-3-->L690-3: Formula: (> v_~T6_E~0_13 0) InVars {~T6_E~0=v_~T6_E~0_13} OutVars{~T6_E~0=v_~T6_E~0_13} AuxVars[] AssignedVars[] 3460#L690-3 [3795] L690-3-->L695-3: Formula: (< 0 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 3338#L695-3 [2609] L695-3-->L700-3: Formula: (and (= 0 v_~E_2~0_30) (= v_~E_2~0_29 1)) InVars {~E_2~0=v_~E_2~0_30} OutVars{~E_2~0=v_~E_2~0_29} AuxVars[] AssignedVars[~E_2~0] 3339#L700-3 [3155] L700-3-->L705-3: Formula: (and (= v_~E_3~0_29 1) (= 0 v_~E_3~0_30)) InVars {~E_3~0=v_~E_3~0_30} OutVars{~E_3~0=v_~E_3~0_29} AuxVars[] AssignedVars[~E_3~0] 3401#L705-3 [2688] L705-3-->L710-3: Formula: (and (= v_~E_4~0_29 1) (= 0 v_~E_4~0_30)) InVars {~E_4~0=v_~E_4~0_30} OutVars{~E_4~0=v_~E_4~0_29} AuxVars[] AssignedVars[~E_4~0] 3283#L710-3 [2515] L710-3-->L715-3: Formula: (and (= 0 v_~E_5~0_30) (= v_~E_5~0_29 1)) InVars {~E_5~0=v_~E_5~0_30} OutVars{~E_5~0=v_~E_5~0_29} AuxVars[] AssignedVars[~E_5~0] 3284#L715-3 [3048] L715-3-->L720-3: Formula: (and (= v_~E_6~0_29 1) (= 0 v_~E_6~0_30)) InVars {~E_6~0=v_~E_6~0_30} OutVars{~E_6~0=v_~E_6~0_29} AuxVars[] AssignedVars[~E_6~0] 3146#L720-3 [2388] L720-3-->L310-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_43, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_43, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_25|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_25|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_25|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_43, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_43, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_43, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_25|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_25|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_25|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_25|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_43, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_25|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_43, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_43} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 3147#L310-21 [2779] L310-21-->L311-7: Formula: (= v_~m_pc~0_23 1) InVars {~m_pc~0=v_~m_pc~0_23} OutVars{~m_pc~0=v_~m_pc~0_23} AuxVars[] AssignedVars[] 3424#L311-7 [2720] L311-7-->L321-7: Formula: (and (= v_~M_E~0_31 1) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_46 1)) InVars {~M_E~0=v_~M_E~0_31} OutVars{~M_E~0=v_~M_E~0_31, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_46} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 3425#L321-7 [4303] L321-7-->L815-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 3386#L815-21 [3897] L815-21-->L815-23: Formula: (and (> 0 v_ULTIMATE.start_activate_threads_~tmp~1_47) (= v_~m_st~0_20 0)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_47} OutVars{~m_st~0=v_~m_st~0_20, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_47} AuxVars[] AssignedVars[~m_st~0] 3367#L815-23 [2638] L815-23-->L329-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 3368#L329-21 [3038] L329-21-->L330-7: Formula: (= v_~t1_pc~0_23 1) InVars {~t1_pc~0=v_~t1_pc~0_23} OutVars{~t1_pc~0=v_~t1_pc~0_23} AuxVars[] AssignedVars[] 3563#L330-7 [2981] L330-7-->L340-7: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_52 1) (= 1 v_~E_1~0_32)) InVars {~E_1~0=v_~E_1~0_32} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_52, ~E_1~0=v_~E_1~0_32} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 3478#L340-7 [4310] L340-7-->L823-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 3479#L823-21 [2931] L823-21-->L823-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} AuxVars[] AssignedVars[] 3538#L823-23 [2934] L823-23-->L348-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_25|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 3540#L348-21 [3306] L348-21-->L349-7: Formula: (= 1 v_~t2_pc~0_23) InVars {~t2_pc~0=v_~t2_pc~0_23} OutVars{~t2_pc~0=v_~t2_pc~0_23} AuxVars[] AssignedVars[] 3644#L349-7 [3255] L349-7-->L359-7: Formula: (and (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_52 1) (= 1 v_~E_2~0_32)) InVars {~E_2~0=v_~E_2~0_32} OutVars{~E_2~0=v_~E_2~0_32, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_52} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 3620#L359-7 [4317] L359-7-->L831-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 3261#L831-21 [2490] L831-21-->L831-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} AuxVars[] AssignedVars[] 3262#L831-23 [3197] L831-23-->L367-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_25|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 3172#L367-21 [2409] L367-21-->L368-7: Formula: (= v_~t3_pc~0_23 1) InVars {~t3_pc~0=v_~t3_pc~0_23} OutVars{~t3_pc~0=v_~t3_pc~0_23} AuxVars[] AssignedVars[] 3173#L368-7 [2539] L368-7-->L378-7: Formula: (and (= 1 v_~E_3~0_32) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_52 1)) InVars {~E_3~0=v_~E_3~0_32} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_52, ~E_3~0=v_~E_3~0_32} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 3142#L378-7 [4324] L378-7-->L839-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 3196#L839-21 [4023] L839-21-->L839-23: Formula: (and (= v_~t3_st~0_21 0) (> v_ULTIMATE.start_activate_threads_~tmp___2~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} OutVars{~t3_st~0=v_~t3_st~0_21, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} AuxVars[] AssignedVars[~t3_st~0] 3420#L839-23 [2722] L839-23-->L386-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_49, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 3347#L386-21 [4037] L386-21-->L386-23: Formula: (< 1 v_~t4_pc~0_24) InVars {~t4_pc~0=v_~t4_pc~0_24} OutVars{~t4_pc~0=v_~t4_pc~0_24} AuxVars[] AssignedVars[] 3348#L386-23 [2623] L386-23-->L397-7: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 3354#L397-7 [4331] L397-7-->L847-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 3383#L847-21 [4065] L847-21-->L847-23: Formula: (and (= v_~t4_st~0_22 0) (< v_ULTIMATE.start_activate_threads_~tmp___3~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47, ~t4_st~0=v_~t4_st~0_22} AuxVars[] AssignedVars[~t4_st~0] 3565#L847-23 [2983] L847-23-->L405-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_25|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 3529#L405-21 [2911] L405-21-->L406-7: Formula: (= v_~t5_pc~0_23 1) InVars {~t5_pc~0=v_~t5_pc~0_23} OutVars{~t5_pc~0=v_~t5_pc~0_23} AuxVars[] AssignedVars[] 3515#L406-7 [2874] L406-7-->L416-7: Formula: (and (= 1 v_~E_5~0_32) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_52 1)) InVars {~E_5~0=v_~E_5~0_32} OutVars{~E_5~0=v_~E_5~0_32, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_52} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 3517#L416-7 [4338] L416-7-->L855-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 3534#L855-21 [3251] L855-21-->L855-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} AuxVars[] AssignedVars[] 3643#L855-23 [3257] L855-23-->L424-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_25|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 3630#L424-21 [3173] L424-21-->L425-7: Formula: (= 1 v_~t6_pc~0_23) InVars {~t6_pc~0=v_~t6_pc~0_23} OutVars{~t6_pc~0=v_~t6_pc~0_23} AuxVars[] AssignedVars[] 3612#L425-7 [3114] L425-7-->L435-7: Formula: (and (= 1 v_~E_6~0_32) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_52 1)) InVars {~E_6~0=v_~E_6~0_32} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_52, ~E_6~0=v_~E_6~0_32} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 3256#L435-7 [4340] L435-7-->L863-21: Formula: (and (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___5~0_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_35|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_41|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 3257#L863-21 [4135] L863-21-->L863-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___5~0_47 0) (= v_~t6_st~0_22 0)) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} OutVars{~t6_st~0=v_~t6_st~0_22, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} AuxVars[] AssignedVars[~t6_st~0] 3299#L863-23 [4137] L863-23-->L733-3: Formula: (< v_~M_E~0_35 1) InVars {~M_E~0=v_~M_E~0_35} OutVars{~M_E~0=v_~M_E~0_35} AuxVars[] AssignedVars[] 3300#L733-3 [3184] L733-3-->L738-3: Formula: (and (= v_~T1_E~0_15 1) (= v_~T1_E~0_14 2)) InVars {~T1_E~0=v_~T1_E~0_15} OutVars{~T1_E~0=v_~T1_E~0_14} AuxVars[] AssignedVars[~T1_E~0] 3559#L738-3 [2971] L738-3-->L743-3: Formula: (and (= v_~T2_E~0_14 2) (= 1 v_~T2_E~0_15)) InVars {~T2_E~0=v_~T2_E~0_15} OutVars{~T2_E~0=v_~T2_E~0_14} AuxVars[] AssignedVars[~T2_E~0] 3279#L743-3 [4144] L743-3-->L748-3: Formula: (> 1 v_~T3_E~0_16) InVars {~T3_E~0=v_~T3_E~0_16} OutVars{~T3_E~0=v_~T3_E~0_16} AuxVars[] AssignedVars[] 3280#L748-3 [4145] L748-3-->L753-3: Formula: (> v_~T4_E~0_16 1) InVars {~T4_E~0=v_~T4_E~0_16} OutVars{~T4_E~0=v_~T4_E~0_16} AuxVars[] AssignedVars[] 3137#L753-3 [4147] L753-3-->L758-3: Formula: (> 1 v_~T5_E~0_16) InVars {~T5_E~0=v_~T5_E~0_16} OutVars{~T5_E~0=v_~T5_E~0_16} AuxVars[] AssignedVars[] 3138#L758-3 [4149] L758-3-->L763-3: Formula: (> v_~T6_E~0_16 1) InVars {~T6_E~0=v_~T6_E~0_16} OutVars{~T6_E~0=v_~T6_E~0_16} AuxVars[] AssignedVars[] 3228#L763-3 [4151] L763-3-->L768-3: Formula: (< 1 v_~E_1~0_36) InVars {~E_1~0=v_~E_1~0_36} OutVars{~E_1~0=v_~E_1~0_36} AuxVars[] AssignedVars[] 3229#L768-3 [3219] L768-3-->L773-3: Formula: (and (= 1 v_~E_2~0_35) (= v_~E_2~0_34 2)) InVars {~E_2~0=v_~E_2~0_35} OutVars{~E_2~0=v_~E_2~0_34} AuxVars[] AssignedVars[~E_2~0] 3454#L773-3 [2775] L773-3-->L778-3: Formula: (and (= 1 v_~E_3~0_35) (= v_~E_3~0_34 2)) InVars {~E_3~0=v_~E_3~0_35} OutVars{~E_3~0=v_~E_3~0_34} AuxVars[] AssignedVars[~E_3~0] 3455#L778-3 [3308] L778-3-->L783-3: Formula: (and (= 1 v_~E_4~0_35) (= v_~E_4~0_34 2)) InVars {~E_4~0=v_~E_4~0_35} OutVars{~E_4~0=v_~E_4~0_34} AuxVars[] AssignedVars[~E_4~0] 3350#L783-3 [4160] L783-3-->L788-3: Formula: (< 1 v_~E_5~0_36) InVars {~E_5~0=v_~E_5~0_36} OutVars{~E_5~0=v_~E_5~0_36} AuxVars[] AssignedVars[] 3351#L788-3 [4161] L788-3-->L793-3: Formula: (> 1 v_~E_6~0_36) InVars {~E_6~0=v_~E_6~0_36} OutVars{~E_6~0=v_~E_6~0_36} AuxVars[] AssignedVars[] 3557#L793-3 [2966] L793-3-->L494-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_30} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 3519#L494-1 [2878] L494-1-->L531-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33 1) (= 0 v_~m_st~0_21)) InVars {~m_st~0=v_~m_st~0_21} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33, ~m_st~0=v_~m_st~0_21} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 3216#L531-1 [4341] L531-1-->L1033: Formula: (and (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp~3] 3443#L1033 [4169] L1033-->L1033-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_6) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} AuxVars[] AssignedVars[] 3186#L1033-1 [2919] L1033-1-->L494-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_3|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_6, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_exists_runnable_thread_~__retres1~7, ULTIMATE.start_stop_simulation_#res] 3520#L494-2 [2882] L494-2-->L531-2: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9 1) (= v_~m_st~0_6 0)) InVars {~m_st~0=v_~m_st~0_6} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9, ~m_st~0=v_~m_st~0_6} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 3220#L531-2 [4343] L531-2-->L988: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 3444#L988 [3240] L988-->L995: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 3179#L995 [4354] L995-->L1014-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_6|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_#t~ret17, ULTIMATE.start_stop_simulation_#res] 3180#L1014-1 [2020-06-22 00:13:01,431 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:01,431 INFO L82 PathProgramCache]: Analyzing trace with hash -1711382234, now seen corresponding path program 1 times [2020-06-22 00:13:01,432 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:01,432 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:01,433 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:01,433 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2020-06-22 00:13:01,433 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:01,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:01,461 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:01,461 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:01,461 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-06-22 00:13:01,462 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-06-22 00:13:01,462 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:01,462 INFO L82 PathProgramCache]: Analyzing trace with hash 444577190, now seen corresponding path program 3 times [2020-06-22 00:13:01,462 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:01,463 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:01,463 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:01,464 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:01,464 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:01,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:01,506 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:01,506 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:01,506 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2020-06-22 00:13:01,507 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-06-22 00:13:01,507 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-06-22 00:13:01,507 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-06-22 00:13:01,507 INFO L87 Difference]: Start difference. First operand 518 states and 1140 transitions. cyclomatic complexity: 623 Second operand 3 states. [2020-06-22 00:13:02,106 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-06-22 00:13:02,107 INFO L93 Difference]: Finished difference Result 518 states and 1139 transitions. [2020-06-22 00:13:02,122 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-06-22 00:13:02,122 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 518 states and 1139 transitions. [2020-06-22 00:13:02,126 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 442 [2020-06-22 00:13:02,130 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 518 states to 518 states and 1139 transitions. [2020-06-22 00:13:02,130 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 518 [2020-06-22 00:13:02,130 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 518 [2020-06-22 00:13:02,131 INFO L73 IsDeterministic]: Start isDeterministic. Operand 518 states and 1139 transitions. [2020-06-22 00:13:02,132 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-06-22 00:13:02,132 INFO L706 BuchiCegarLoop]: Abstraction has 518 states and 1139 transitions. [2020-06-22 00:13:02,132 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 518 states and 1139 transitions. [2020-06-22 00:13:02,140 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 518 to 518. [2020-06-22 00:13:02,141 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 518 states. [2020-06-22 00:13:02,142 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 518 states to 518 states and 1139 transitions. [2020-06-22 00:13:02,142 INFO L729 BuchiCegarLoop]: Abstraction has 518 states and 1139 transitions. [2020-06-22 00:13:02,142 INFO L609 BuchiCegarLoop]: Abstraction has 518 states and 1139 transitions. [2020-06-22 00:13:02,143 INFO L442 BuchiCegarLoop]: ======== Iteration 5============ [2020-06-22 00:13:02,143 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 518 states and 1139 transitions. [2020-06-22 00:13:02,145 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 442 [2020-06-22 00:13:02,146 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-06-22 00:13:02,146 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-06-22 00:13:02,147 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:02,147 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:02,149 INFO L794 eck$LassoCheckResult]: Stem: 4615#ULTIMATE.startENTRY [4266] ULTIMATE.startENTRY-->L444: Formula: (and (= 1 v_~t6_i~0_7) (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~M_E~0_37 2) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 0 v_~t6_pc~0_26) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_6~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= v_~T6_E~0_18 2) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~t6_st~0_24) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t6_pc~0=v_~t6_pc~0_26, ~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~T6_E~0=v_~T6_E~0_18, ~M_E~0=v_~M_E~0_37, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ~T4_E~0=v_~T4_E~0_18, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_4|, ~t6_i~0=v_~t6_i~0_7, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ULTIMATE.start_main_~__retres1~8=v_ULTIMATE.start_main_~__retres1~8_6, ~T2_E~0=v_~T2_E~0_18, ~t6_st~0=v_~t6_st~0_24, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_6~0=v_~E_6~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t6_pc~0, ~t5_i~0, ~t1_pc~0, ~t5_st~0, ~T6_E~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ~T4_E~0, ULTIMATE.start_start_simulation_#t~ret17, ~t6_i~0, ~t2_st~0, ~t2_pc~0, ULTIMATE.start_main_~__retres1~8, ~T2_E~0, ~t6_st~0, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_6~0, ULTIMATE.start_main_#res, ~E_2~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 4265#L444 [2453] L444-->L451-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 4266#L451-1 [3030] L451-1-->L456-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 4351#L456-1 [2574] L456-1-->L461-1: Formula: (and (= v_~t2_st~0_2 0) (= 1 v_~t2_i~0_3)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_2} AuxVars[] AssignedVars[~t2_st~0] 4352#L461-1 [3644] L461-1-->L466-1: Formula: (and (< v_~t3_i~0_4 1) (= v_~t3_st~0_4 2)) InVars {~t3_i~0=v_~t3_i~0_4} OutVars{~t3_st~0=v_~t3_st~0_4, ~t3_i~0=v_~t3_i~0_4} AuxVars[] AssignedVars[~t3_st~0] 4267#L466-1 [3646] L466-1-->L471-1: Formula: (and (< v_~t4_i~0_4 1) (= v_~t4_st~0_5 2)) InVars {~t4_i~0=v_~t4_i~0_4} OutVars{~t4_i~0=v_~t4_i~0_4, ~t4_st~0=v_~t4_st~0_5} AuxVars[] AssignedVars[~t4_st~0] 4268#L471-1 [3647] L471-1-->L476-1: Formula: (and (= v_~t5_st~0_5 2) (< v_~t5_i~0_4 1)) InVars {~t5_i~0=v_~t5_i~0_4} OutVars{~t5_i~0=v_~t5_i~0_4, ~t5_st~0=v_~t5_st~0_5} AuxVars[] AssignedVars[~t5_st~0] 4491#L476-1 [2761] L476-1-->L481-1: Formula: (and (= 1 v_~t6_i~0_3) (= v_~t6_st~0_4 0)) InVars {~t6_i~0=v_~t6_i~0_3} OutVars{~t6_st~0=v_~t6_st~0_4, ~t6_i~0=v_~t6_i~0_3} AuxVars[] AssignedVars[~t6_st~0] 4492#L481-1 [3652] L481-1-->L660-1: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 4626#L660-1 [3654] L660-1-->L665-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 4183#L665-1 [2383] L665-1-->L670-1: Formula: (and (= 0 v_~T2_E~0_3) (= v_~T2_E~0_2 1)) InVars {~T2_E~0=v_~T2_E~0_3} OutVars{~T2_E~0=v_~T2_E~0_2} AuxVars[] AssignedVars[~T2_E~0] 4184#L670-1 [2894] L670-1-->L675-1: Formula: (and (= v_~T3_E~0_2 1) (= v_~T3_E~0_3 0)) InVars {~T3_E~0=v_~T3_E~0_3} OutVars{~T3_E~0=v_~T3_E~0_2} AuxVars[] AssignedVars[~T3_E~0] 4274#L675-1 [3660] L675-1-->L680-1: Formula: (< v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 4275#L680-1 [3662] L680-1-->L685-1: Formula: (< v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 4500#L685-1 [3663] L685-1-->L690-1: Formula: (< 0 v_~T6_E~0_4) InVars {~T6_E~0=v_~T6_E~0_4} OutVars{~T6_E~0=v_~T6_E~0_4} AuxVars[] AssignedVars[] 4501#L690-1 [3310] L690-1-->L695-1: Formula: (and (= v_~E_1~0_5 0) (= v_~E_1~0_4 1)) InVars {~E_1~0=v_~E_1~0_5} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[~E_1~0] 4396#L695-1 [2621] L695-1-->L700-1: Formula: (and (= v_~E_2~0_4 1) (= v_~E_2~0_5 0)) InVars {~E_2~0=v_~E_2~0_5} OutVars{~E_2~0=v_~E_2~0_4} AuxVars[] AssignedVars[~E_2~0] 4397#L700-1 [3180] L700-1-->L705-1: Formula: (and (= v_~E_3~0_5 0) (= v_~E_3~0_4 1)) InVars {~E_3~0=v_~E_3~0_5} OutVars{~E_3~0=v_~E_3~0_4} AuxVars[] AssignedVars[~E_3~0] 4602#L705-1 [3672] L705-1-->L710-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 4335#L710-1 [2525] L710-1-->L715-1: Formula: (and (= v_~E_5~0_3 0) (= v_~E_5~0_2 1)) InVars {~E_5~0=v_~E_5~0_3} OutVars{~E_5~0=v_~E_5~0_2} AuxVars[] AssignedVars[~E_5~0] 4336#L715-1 [3676] L715-1-->L720-1: Formula: (< v_~E_6~0_4 0) InVars {~E_6~0=v_~E_6~0_4} OutVars{~E_6~0=v_~E_6~0_4} AuxVars[] AssignedVars[] 4219#L720-1 [2412] L720-1-->L310: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_7, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_4|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_4|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_7, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_4, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_4, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_2|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_2|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_4|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_4|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_7, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_2|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_4} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 4220#L310 [2597] L310-->L311: Formula: (= v_~m_pc~0_4 1) InVars {~m_pc~0=v_~m_pc~0_4} OutVars{~m_pc~0=v_~m_pc~0_4} AuxVars[] AssignedVars[] 4367#L311 [2732] L311-->L321: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_10 1) (= 1 v_~M_E~0_8)) InVars {~M_E~0=v_~M_E~0_8} OutVars{~M_E~0=v_~M_E~0_8, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_10} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 4362#L321 [4267] L321-->L815: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 4363#L815 [3682] L815-->L815-2: Formula: (and (= v_~m_st~0_5 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_11)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} OutVars{~m_st~0=v_~m_st~0_5, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} AuxVars[] AssignedVars[~m_st~0] 4598#L815-2 [2961] L815-2-->L329: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 4534#L329 [2848] L329-->L330: Formula: (= v_~t1_pc~0_4 1) InVars {~t1_pc~0=v_~t1_pc~0_4} OutVars{~t1_pc~0=v_~t1_pc~0_4} AuxVars[] AssignedVars[] 4535#L330 [3036] L330-->L340: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_10 1) (= v_~E_1~0_7 1)) InVars {~E_1~0=v_~E_1~0_7} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_10, ~E_1~0=v_~E_1~0_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 4529#L340 [4268] L340-->L823: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 4530#L823 [3688] L823-->L823-2: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___0~0_11 0) (= v_~t1_st~0_5 0)) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_11} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_11, ~t1_st~0=v_~t1_st~0_5} AuxVars[] AssignedVars[~t1_st~0] 4684#L823-2 [3235] L823-2-->L348: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_4|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 4668#L348 [3143] L348-->L349: Formula: (= v_~t2_pc~0_4 1) InVars {~t2_pc~0=v_~t2_pc~0_4} OutVars{~t2_pc~0=v_~t2_pc~0_4} AuxVars[] AssignedVars[] 4669#L349 [3267] L349-->L359: Formula: (and (= v_~E_2~0_7 1) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_10 1)) InVars {~E_2~0=v_~E_2~0_7} OutVars{~E_2~0=v_~E_2~0_7, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_10} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 4667#L359 [4269] L359-->L831: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 4342#L831 [3694] L831-->L831-2: Formula: (and (= v_~t2_st~0_5 0) (> v_ULTIMATE.start_activate_threads_~tmp___1~0_11 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_11} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_11, ~t2_st~0=v_~t2_st~0_5} AuxVars[] AssignedVars[~t2_st~0] 4330#L831-2 [2520] L831-2-->L367: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_4|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 4270#L367 [3695] L367-->L367-2: Formula: (> 1 v_~t3_pc~0_5) InVars {~t3_pc~0=v_~t3_pc~0_5} OutVars{~t3_pc~0=v_~t3_pc~0_5} AuxVars[] AssignedVars[] 4248#L367-2 [2438] L367-2-->L378: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 4249#L378 [4270] L378-->L839: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 4269#L839 [2791] L839-->L839-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} AuxVars[] AssignedVars[] 4507#L839-2 [2794] L839-2-->L386: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_7, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 4437#L386 [2675] L386-->L387: Formula: (= v_~t4_pc~0_4 1) InVars {~t4_pc~0=v_~t4_pc~0_4} OutVars{~t4_pc~0=v_~t4_pc~0_4} AuxVars[] AssignedVars[] 4356#L387 [2588] L387-->L397: Formula: (and (= v_~E_4~0_7 1) (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_10 1)) InVars {~E_4~0=v_~E_4~0_7} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_10, ~E_4~0=v_~E_4~0_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 4358#L397 [4271] L397-->L847: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 4436#L847 [3084] L847-->L847-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} AuxVars[] AssignedVars[] 4630#L847-2 [3064] L847-2-->L405: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_4|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 4631#L405 [3708] L405-->L405-2: Formula: (> 1 v_~t5_pc~0_5) InVars {~t5_pc~0=v_~t5_pc~0_5} OutVars{~t5_pc~0=v_~t5_pc~0_5} AuxVars[] AssignedVars[] 4567#L405-2 [2940] L405-2-->L416: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 4566#L416 [4272] L416-->L855: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 4637#L855 [3711] L855-->L855-2: Formula: (and (> v_ULTIMATE.start_activate_threads_~tmp___4~0_11 0) (= v_~t5_st~0_7 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_11} OutVars{~t5_st~0=v_~t5_st~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_11} AuxVars[] AssignedVars[~t5_st~0] 4638#L855-2 [3093] L855-2-->L424: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_4|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 4314#L424 [3714] L424-->L424-2: Formula: (> v_~t6_pc~0_5 1) InVars {~t6_pc~0=v_~t6_pc~0_5} OutVars{~t6_pc~0=v_~t6_pc~0_5} AuxVars[] AssignedVars[] 4315#L424-2 [2503] L424-2-->L435: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 4311#L435 [4273] L435-->L863: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___5~0_49 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_28|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_28|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 4235#L863 [2425] L863-->L863-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___5~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} AuxVars[] AssignedVars[] 4206#L863-2 [3720] L863-2-->L733-1: Formula: (< v_~M_E~0_15 1) InVars {~M_E~0=v_~M_E~0_15} OutVars{~M_E~0=v_~M_E~0_15} AuxVars[] AssignedVars[] 4207#L733-1 [3722] L733-1-->L738-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 4600#L738-1 [3724] L738-1-->L743-1: Formula: (> 1 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 4333#L743-1 [3726] L743-1-->L748-1: Formula: (< 1 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 4334#L748-1 [3727] L748-1-->L753-1: Formula: (< v_~T4_E~0_10 1) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 4214#L753-1 [2407] L753-1-->L758-1: Formula: (and (= v_~T5_E~0_8 2) (= v_~T5_E~0_9 1)) InVars {~T5_E~0=v_~T5_E~0_9} OutVars{~T5_E~0=v_~T5_E~0_8} AuxVars[] AssignedVars[~T5_E~0] 4215#L758-1 [3732] L758-1-->L763-1: Formula: (< v_~T6_E~0_10 1) InVars {~T6_E~0=v_~T6_E~0_10} OutVars{~T6_E~0=v_~T6_E~0_10} AuxVars[] AssignedVars[] 4286#L763-1 [2475] L763-1-->L768-1: Formula: (and (= v_~E_1~0_12 2) (= 1 v_~E_1~0_13)) InVars {~E_1~0=v_~E_1~0_13} OutVars{~E_1~0=v_~E_1~0_12} AuxVars[] AssignedVars[~E_1~0] 4287#L768-1 [3736] L768-1-->L773-1: Formula: (< 1 v_~E_2~0_14) InVars {~E_2~0=v_~E_2~0_14} OutVars{~E_2~0=v_~E_2~0_14} AuxVars[] AssignedVars[] 4495#L773-1 [2767] L773-1-->L778-1: Formula: (and (= 1 v_~E_3~0_13) (= v_~E_3~0_12 2)) InVars {~E_3~0=v_~E_3~0_13} OutVars{~E_3~0=v_~E_3~0_12} AuxVars[] AssignedVars[~E_3~0] 4496#L778-1 [3740] L778-1-->L783-1: Formula: (< 1 v_~E_4~0_14) InVars {~E_4~0=v_~E_4~0_14} OutVars{~E_4~0=v_~E_4~0_14} AuxVars[] AssignedVars[] 4387#L783-1 [3742] L783-1-->L788-1: Formula: (> 1 v_~E_5~0_14) InVars {~E_5~0=v_~E_5~0_14} OutVars{~E_5~0=v_~E_5~0_14} AuxVars[] AssignedVars[] 4388#L788-1 [3743] L788-1-->L1014-1: Formula: (> 1 v_~E_6~0_14) InVars {~E_6~0=v_~E_6~0_14} OutVars{~E_6~0=v_~E_6~0_14} AuxVars[] AssignedVars[] 4224#L1014-1 [2020-06-22 00:13:02,150 INFO L796 eck$LassoCheckResult]: Loop: 4224#L1014-1 [4274] L1014-1-->L635: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp_ndt_7~0=v_ULTIMATE.start_eval_~tmp_ndt_7~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp_ndt_7~0] 4189#L635 [4275] L635-->L494: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_37} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 4562#L494 [2876] L494-->L531: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21 1) (= v_~m_st~0_8 0)) InVars {~m_st~0=v_~m_st~0_8} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21, ~m_st~0=v_~m_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 4258#L531 [4276] L531-->L546: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 4484#L546 [4278] L546-->L660-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 4627#L660-2 [3747] L660-2-->L660-4: Formula: (> v_~M_E~0_30 0) InVars {~M_E~0=v_~M_E~0_30} OutVars{~M_E~0=v_~M_E~0_30} AuxVars[] AssignedVars[] 4628#L660-4 [3058] L660-4-->L665-3: Formula: (and (= v_~T1_E~0_11 1) (= v_~T1_E~0_12 0)) InVars {~T1_E~0=v_~T1_E~0_12} OutVars{~T1_E~0=v_~T1_E~0_11} AuxVars[] AssignedVars[~T1_E~0] 4199#L665-3 [2394] L665-3-->L670-3: Formula: (and (= 0 v_~T2_E~0_12) (= v_~T2_E~0_11 1)) InVars {~T2_E~0=v_~T2_E~0_12} OutVars{~T2_E~0=v_~T2_E~0_11} AuxVars[] AssignedVars[~T2_E~0] 4200#L670-3 [3761] L670-3-->L675-3: Formula: (> 0 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 4276#L675-3 [2467] L675-3-->L680-3: Formula: (and (= v_~T4_E~0_11 1) (= v_~T4_E~0_12 0)) InVars {~T4_E~0=v_~T4_E~0_12} OutVars{~T4_E~0=v_~T4_E~0_11} AuxVars[] AssignedVars[~T4_E~0] 4277#L680-3 [3776] L680-3-->L685-3: Formula: (< 0 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 4503#L685-3 [3785] L685-3-->L690-3: Formula: (> v_~T6_E~0_13 0) InVars {~T6_E~0=v_~T6_E~0_13} OutVars{~T6_E~0=v_~T6_E~0_13} AuxVars[] AssignedVars[] 4504#L690-3 [3795] L690-3-->L695-3: Formula: (< 0 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 4382#L695-3 [2609] L695-3-->L700-3: Formula: (and (= 0 v_~E_2~0_30) (= v_~E_2~0_29 1)) InVars {~E_2~0=v_~E_2~0_30} OutVars{~E_2~0=v_~E_2~0_29} AuxVars[] AssignedVars[~E_2~0] 4383#L700-3 [3155] L700-3-->L705-3: Formula: (and (= v_~E_3~0_29 1) (= 0 v_~E_3~0_30)) InVars {~E_3~0=v_~E_3~0_30} OutVars{~E_3~0=v_~E_3~0_29} AuxVars[] AssignedVars[~E_3~0] 4445#L705-3 [2688] L705-3-->L710-3: Formula: (and (= v_~E_4~0_29 1) (= 0 v_~E_4~0_30)) InVars {~E_4~0=v_~E_4~0_30} OutVars{~E_4~0=v_~E_4~0_29} AuxVars[] AssignedVars[~E_4~0] 4327#L710-3 [2515] L710-3-->L715-3: Formula: (and (= 0 v_~E_5~0_30) (= v_~E_5~0_29 1)) InVars {~E_5~0=v_~E_5~0_30} OutVars{~E_5~0=v_~E_5~0_29} AuxVars[] AssignedVars[~E_5~0] 4328#L715-3 [3048] L715-3-->L720-3: Formula: (and (= v_~E_6~0_29 1) (= 0 v_~E_6~0_30)) InVars {~E_6~0=v_~E_6~0_30} OutVars{~E_6~0=v_~E_6~0_29} AuxVars[] AssignedVars[~E_6~0] 4190#L720-3 [2388] L720-3-->L310-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_43, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_43, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_25|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_25|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_25|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_43, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_43, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_43, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_25|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_25|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_25|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_25|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_43, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_25|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_43, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_43} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 4191#L310-21 [2779] L310-21-->L311-7: Formula: (= v_~m_pc~0_23 1) InVars {~m_pc~0=v_~m_pc~0_23} OutVars{~m_pc~0=v_~m_pc~0_23} AuxVars[] AssignedVars[] 4468#L311-7 [2720] L311-7-->L321-7: Formula: (and (= v_~M_E~0_31 1) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_46 1)) InVars {~M_E~0=v_~M_E~0_31} OutVars{~M_E~0=v_~M_E~0_31, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_46} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 4469#L321-7 [4303] L321-7-->L815-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 4430#L815-21 [3897] L815-21-->L815-23: Formula: (and (> 0 v_ULTIMATE.start_activate_threads_~tmp~1_47) (= v_~m_st~0_20 0)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_47} OutVars{~m_st~0=v_~m_st~0_20, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_47} AuxVars[] AssignedVars[~m_st~0] 4411#L815-23 [2638] L815-23-->L329-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 4412#L329-21 [3911] L329-21-->L329-23: Formula: (< v_~t1_pc~0_24 1) InVars {~t1_pc~0=v_~t1_pc~0_24} OutVars{~t1_pc~0=v_~t1_pc~0_24} AuxVars[] AssignedVars[] 4608#L329-23 [3052] L329-23-->L340-7: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 4522#L340-7 [4310] L340-7-->L823-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 4523#L823-21 [2931] L823-21-->L823-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} AuxVars[] AssignedVars[] 4582#L823-23 [2934] L823-23-->L348-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_25|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 4584#L348-21 [3306] L348-21-->L349-7: Formula: (= 1 v_~t2_pc~0_23) InVars {~t2_pc~0=v_~t2_pc~0_23} OutVars{~t2_pc~0=v_~t2_pc~0_23} AuxVars[] AssignedVars[] 4688#L349-7 [3255] L349-7-->L359-7: Formula: (and (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_52 1) (= 1 v_~E_2~0_32)) InVars {~E_2~0=v_~E_2~0_32} OutVars{~E_2~0=v_~E_2~0_32, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_52} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 4664#L359-7 [4317] L359-7-->L831-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 4305#L831-21 [2490] L831-21-->L831-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} AuxVars[] AssignedVars[] 4306#L831-23 [3197] L831-23-->L367-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_25|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 4216#L367-21 [2409] L367-21-->L368-7: Formula: (= v_~t3_pc~0_23 1) InVars {~t3_pc~0=v_~t3_pc~0_23} OutVars{~t3_pc~0=v_~t3_pc~0_23} AuxVars[] AssignedVars[] 4217#L368-7 [2539] L368-7-->L378-7: Formula: (and (= 1 v_~E_3~0_32) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_52 1)) InVars {~E_3~0=v_~E_3~0_32} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_52, ~E_3~0=v_~E_3~0_32} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 4186#L378-7 [4324] L378-7-->L839-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 4240#L839-21 [4023] L839-21-->L839-23: Formula: (and (= v_~t3_st~0_21 0) (> v_ULTIMATE.start_activate_threads_~tmp___2~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} OutVars{~t3_st~0=v_~t3_st~0_21, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} AuxVars[] AssignedVars[~t3_st~0] 4464#L839-23 [2722] L839-23-->L386-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_49, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 4391#L386-21 [4037] L386-21-->L386-23: Formula: (< 1 v_~t4_pc~0_24) InVars {~t4_pc~0=v_~t4_pc~0_24} OutVars{~t4_pc~0=v_~t4_pc~0_24} AuxVars[] AssignedVars[] 4392#L386-23 [2623] L386-23-->L397-7: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 4398#L397-7 [4331] L397-7-->L847-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 4427#L847-21 [4065] L847-21-->L847-23: Formula: (and (= v_~t4_st~0_22 0) (< v_ULTIMATE.start_activate_threads_~tmp___3~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47, ~t4_st~0=v_~t4_st~0_22} AuxVars[] AssignedVars[~t4_st~0] 4609#L847-23 [2983] L847-23-->L405-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_25|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 4573#L405-21 [4080] L405-21-->L405-23: Formula: (> v_~t5_pc~0_24 1) InVars {~t5_pc~0=v_~t5_pc~0_24} OutVars{~t5_pc~0=v_~t5_pc~0_24} AuxVars[] AssignedVars[] 4560#L405-23 [2891] L405-23-->L416-7: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 4561#L416-7 [4338] L416-7-->L855-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 4578#L855-21 [3251] L855-21-->L855-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} AuxVars[] AssignedVars[] 4687#L855-23 [3257] L855-23-->L424-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_25|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 4674#L424-21 [3173] L424-21-->L425-7: Formula: (= 1 v_~t6_pc~0_23) InVars {~t6_pc~0=v_~t6_pc~0_23} OutVars{~t6_pc~0=v_~t6_pc~0_23} AuxVars[] AssignedVars[] 4656#L425-7 [3114] L425-7-->L435-7: Formula: (and (= 1 v_~E_6~0_32) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_52 1)) InVars {~E_6~0=v_~E_6~0_32} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_52, ~E_6~0=v_~E_6~0_32} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 4300#L435-7 [4340] L435-7-->L863-21: Formula: (and (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___5~0_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_35|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_41|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 4301#L863-21 [4135] L863-21-->L863-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___5~0_47 0) (= v_~t6_st~0_22 0)) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} OutVars{~t6_st~0=v_~t6_st~0_22, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} AuxVars[] AssignedVars[~t6_st~0] 4343#L863-23 [4137] L863-23-->L733-3: Formula: (< v_~M_E~0_35 1) InVars {~M_E~0=v_~M_E~0_35} OutVars{~M_E~0=v_~M_E~0_35} AuxVars[] AssignedVars[] 4344#L733-3 [3184] L733-3-->L738-3: Formula: (and (= v_~T1_E~0_15 1) (= v_~T1_E~0_14 2)) InVars {~T1_E~0=v_~T1_E~0_15} OutVars{~T1_E~0=v_~T1_E~0_14} AuxVars[] AssignedVars[~T1_E~0] 4603#L738-3 [2971] L738-3-->L743-3: Formula: (and (= v_~T2_E~0_14 2) (= 1 v_~T2_E~0_15)) InVars {~T2_E~0=v_~T2_E~0_15} OutVars{~T2_E~0=v_~T2_E~0_14} AuxVars[] AssignedVars[~T2_E~0] 4323#L743-3 [4144] L743-3-->L748-3: Formula: (> 1 v_~T3_E~0_16) InVars {~T3_E~0=v_~T3_E~0_16} OutVars{~T3_E~0=v_~T3_E~0_16} AuxVars[] AssignedVars[] 4324#L748-3 [4145] L748-3-->L753-3: Formula: (> v_~T4_E~0_16 1) InVars {~T4_E~0=v_~T4_E~0_16} OutVars{~T4_E~0=v_~T4_E~0_16} AuxVars[] AssignedVars[] 4181#L753-3 [4147] L753-3-->L758-3: Formula: (> 1 v_~T5_E~0_16) InVars {~T5_E~0=v_~T5_E~0_16} OutVars{~T5_E~0=v_~T5_E~0_16} AuxVars[] AssignedVars[] 4182#L758-3 [4149] L758-3-->L763-3: Formula: (> v_~T6_E~0_16 1) InVars {~T6_E~0=v_~T6_E~0_16} OutVars{~T6_E~0=v_~T6_E~0_16} AuxVars[] AssignedVars[] 4272#L763-3 [4151] L763-3-->L768-3: Formula: (< 1 v_~E_1~0_36) InVars {~E_1~0=v_~E_1~0_36} OutVars{~E_1~0=v_~E_1~0_36} AuxVars[] AssignedVars[] 4273#L768-3 [3219] L768-3-->L773-3: Formula: (and (= 1 v_~E_2~0_35) (= v_~E_2~0_34 2)) InVars {~E_2~0=v_~E_2~0_35} OutVars{~E_2~0=v_~E_2~0_34} AuxVars[] AssignedVars[~E_2~0] 4498#L773-3 [2775] L773-3-->L778-3: Formula: (and (= 1 v_~E_3~0_35) (= v_~E_3~0_34 2)) InVars {~E_3~0=v_~E_3~0_35} OutVars{~E_3~0=v_~E_3~0_34} AuxVars[] AssignedVars[~E_3~0] 4499#L778-3 [3308] L778-3-->L783-3: Formula: (and (= 1 v_~E_4~0_35) (= v_~E_4~0_34 2)) InVars {~E_4~0=v_~E_4~0_35} OutVars{~E_4~0=v_~E_4~0_34} AuxVars[] AssignedVars[~E_4~0] 4394#L783-3 [4160] L783-3-->L788-3: Formula: (< 1 v_~E_5~0_36) InVars {~E_5~0=v_~E_5~0_36} OutVars{~E_5~0=v_~E_5~0_36} AuxVars[] AssignedVars[] 4395#L788-3 [4161] L788-3-->L793-3: Formula: (> 1 v_~E_6~0_36) InVars {~E_6~0=v_~E_6~0_36} OutVars{~E_6~0=v_~E_6~0_36} AuxVars[] AssignedVars[] 4601#L793-3 [2966] L793-3-->L494-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_30} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 4563#L494-1 [2878] L494-1-->L531-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33 1) (= 0 v_~m_st~0_21)) InVars {~m_st~0=v_~m_st~0_21} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33, ~m_st~0=v_~m_st~0_21} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 4260#L531-1 [4341] L531-1-->L1033: Formula: (and (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp~3] 4485#L1033 [4169] L1033-->L1033-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_6) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} AuxVars[] AssignedVars[] 4230#L1033-1 [2919] L1033-1-->L494-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_3|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_6, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_exists_runnable_thread_~__retres1~7, ULTIMATE.start_stop_simulation_#res] 4564#L494-2 [2882] L494-2-->L531-2: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9 1) (= v_~m_st~0_6 0)) InVars {~m_st~0=v_~m_st~0_6} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9, ~m_st~0=v_~m_st~0_6} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 4264#L531-2 [4343] L531-2-->L988: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 4490#L988 [3240] L988-->L995: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 4223#L995 [4354] L995-->L1014-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_6|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_#t~ret17, ULTIMATE.start_stop_simulation_#res] 4224#L1014-1 [2020-06-22 00:13:02,150 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:02,150 INFO L82 PathProgramCache]: Analyzing trace with hash -759760123, now seen corresponding path program 1 times [2020-06-22 00:13:02,150 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:02,151 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:02,152 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:02,152 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2020-06-22 00:13:02,152 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:02,159 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:02,188 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:02,189 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:02,189 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-06-22 00:13:02,189 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-06-22 00:13:02,189 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:02,189 INFO L82 PathProgramCache]: Analyzing trace with hash -60353080, now seen corresponding path program 1 times [2020-06-22 00:13:02,190 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:02,190 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:02,190 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:02,191 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:02,191 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:02,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:02,221 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:02,221 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:02,221 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2020-06-22 00:13:02,222 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-06-22 00:13:02,222 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-06-22 00:13:02,222 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-06-22 00:13:02,222 INFO L87 Difference]: Start difference. First operand 518 states and 1139 transitions. cyclomatic complexity: 622 Second operand 3 states. [2020-06-22 00:13:02,827 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-06-22 00:13:02,827 INFO L93 Difference]: Finished difference Result 518 states and 1138 transitions. [2020-06-22 00:13:02,827 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-06-22 00:13:02,828 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 518 states and 1138 transitions. [2020-06-22 00:13:02,831 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 442 [2020-06-22 00:13:02,835 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 518 states to 518 states and 1138 transitions. [2020-06-22 00:13:02,835 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 518 [2020-06-22 00:13:02,836 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 518 [2020-06-22 00:13:02,836 INFO L73 IsDeterministic]: Start isDeterministic. Operand 518 states and 1138 transitions. [2020-06-22 00:13:02,837 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-06-22 00:13:02,837 INFO L706 BuchiCegarLoop]: Abstraction has 518 states and 1138 transitions. [2020-06-22 00:13:02,838 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 518 states and 1138 transitions. [2020-06-22 00:13:02,846 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 518 to 518. [2020-06-22 00:13:02,846 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 518 states. [2020-06-22 00:13:02,848 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 518 states to 518 states and 1138 transitions. [2020-06-22 00:13:02,848 INFO L729 BuchiCegarLoop]: Abstraction has 518 states and 1138 transitions. [2020-06-22 00:13:02,848 INFO L609 BuchiCegarLoop]: Abstraction has 518 states and 1138 transitions. [2020-06-22 00:13:02,848 INFO L442 BuchiCegarLoop]: ======== Iteration 6============ [2020-06-22 00:13:02,848 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 518 states and 1138 transitions. [2020-06-22 00:13:02,851 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 442 [2020-06-22 00:13:02,851 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-06-22 00:13:02,851 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-06-22 00:13:02,852 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:02,852 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:02,854 INFO L794 eck$LassoCheckResult]: Stem: 5659#ULTIMATE.startENTRY [4266] ULTIMATE.startENTRY-->L444: Formula: (and (= 1 v_~t6_i~0_7) (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~M_E~0_37 2) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 0 v_~t6_pc~0_26) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_6~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= v_~T6_E~0_18 2) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~t6_st~0_24) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t6_pc~0=v_~t6_pc~0_26, ~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~T6_E~0=v_~T6_E~0_18, ~M_E~0=v_~M_E~0_37, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ~T4_E~0=v_~T4_E~0_18, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_4|, ~t6_i~0=v_~t6_i~0_7, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ULTIMATE.start_main_~__retres1~8=v_ULTIMATE.start_main_~__retres1~8_6, ~T2_E~0=v_~T2_E~0_18, ~t6_st~0=v_~t6_st~0_24, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_6~0=v_~E_6~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t6_pc~0, ~t5_i~0, ~t1_pc~0, ~t5_st~0, ~T6_E~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ~T4_E~0, ULTIMATE.start_start_simulation_#t~ret17, ~t6_i~0, ~t2_st~0, ~t2_pc~0, ULTIMATE.start_main_~__retres1~8, ~T2_E~0, ~t6_st~0, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_6~0, ULTIMATE.start_main_#res, ~E_2~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 5309#L444 [2453] L444-->L451-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 5310#L451-1 [3030] L451-1-->L456-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 5395#L456-1 [2574] L456-1-->L461-1: Formula: (and (= v_~t2_st~0_2 0) (= 1 v_~t2_i~0_3)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_2} AuxVars[] AssignedVars[~t2_st~0] 5396#L461-1 [3643] L461-1-->L466-1: Formula: (and (> v_~t3_i~0_4 1) (= v_~t3_st~0_4 2)) InVars {~t3_i~0=v_~t3_i~0_4} OutVars{~t3_st~0=v_~t3_st~0_4, ~t3_i~0=v_~t3_i~0_4} AuxVars[] AssignedVars[~t3_st~0] 5311#L466-1 [3646] L466-1-->L471-1: Formula: (and (< v_~t4_i~0_4 1) (= v_~t4_st~0_5 2)) InVars {~t4_i~0=v_~t4_i~0_4} OutVars{~t4_i~0=v_~t4_i~0_4, ~t4_st~0=v_~t4_st~0_5} AuxVars[] AssignedVars[~t4_st~0] 5312#L471-1 [3647] L471-1-->L476-1: Formula: (and (= v_~t5_st~0_5 2) (< v_~t5_i~0_4 1)) InVars {~t5_i~0=v_~t5_i~0_4} OutVars{~t5_i~0=v_~t5_i~0_4, ~t5_st~0=v_~t5_st~0_5} AuxVars[] AssignedVars[~t5_st~0] 5535#L476-1 [2761] L476-1-->L481-1: Formula: (and (= 1 v_~t6_i~0_3) (= v_~t6_st~0_4 0)) InVars {~t6_i~0=v_~t6_i~0_3} OutVars{~t6_st~0=v_~t6_st~0_4, ~t6_i~0=v_~t6_i~0_3} AuxVars[] AssignedVars[~t6_st~0] 5536#L481-1 [3652] L481-1-->L660-1: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 5670#L660-1 [3654] L660-1-->L665-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 5227#L665-1 [2383] L665-1-->L670-1: Formula: (and (= 0 v_~T2_E~0_3) (= v_~T2_E~0_2 1)) InVars {~T2_E~0=v_~T2_E~0_3} OutVars{~T2_E~0=v_~T2_E~0_2} AuxVars[] AssignedVars[~T2_E~0] 5228#L670-1 [2894] L670-1-->L675-1: Formula: (and (= v_~T3_E~0_2 1) (= v_~T3_E~0_3 0)) InVars {~T3_E~0=v_~T3_E~0_3} OutVars{~T3_E~0=v_~T3_E~0_2} AuxVars[] AssignedVars[~T3_E~0] 5318#L675-1 [3660] L675-1-->L680-1: Formula: (< v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 5319#L680-1 [3662] L680-1-->L685-1: Formula: (< v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 5544#L685-1 [3663] L685-1-->L690-1: Formula: (< 0 v_~T6_E~0_4) InVars {~T6_E~0=v_~T6_E~0_4} OutVars{~T6_E~0=v_~T6_E~0_4} AuxVars[] AssignedVars[] 5545#L690-1 [3310] L690-1-->L695-1: Formula: (and (= v_~E_1~0_5 0) (= v_~E_1~0_4 1)) InVars {~E_1~0=v_~E_1~0_5} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[~E_1~0] 5440#L695-1 [2621] L695-1-->L700-1: Formula: (and (= v_~E_2~0_4 1) (= v_~E_2~0_5 0)) InVars {~E_2~0=v_~E_2~0_5} OutVars{~E_2~0=v_~E_2~0_4} AuxVars[] AssignedVars[~E_2~0] 5441#L700-1 [3180] L700-1-->L705-1: Formula: (and (= v_~E_3~0_5 0) (= v_~E_3~0_4 1)) InVars {~E_3~0=v_~E_3~0_5} OutVars{~E_3~0=v_~E_3~0_4} AuxVars[] AssignedVars[~E_3~0] 5646#L705-1 [3672] L705-1-->L710-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 5379#L710-1 [2525] L710-1-->L715-1: Formula: (and (= v_~E_5~0_3 0) (= v_~E_5~0_2 1)) InVars {~E_5~0=v_~E_5~0_3} OutVars{~E_5~0=v_~E_5~0_2} AuxVars[] AssignedVars[~E_5~0] 5380#L715-1 [3676] L715-1-->L720-1: Formula: (< v_~E_6~0_4 0) InVars {~E_6~0=v_~E_6~0_4} OutVars{~E_6~0=v_~E_6~0_4} AuxVars[] AssignedVars[] 5263#L720-1 [2412] L720-1-->L310: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_7, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_4|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_4|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_7, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_4, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_4, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_2|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_2|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_4|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_4|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_7, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_2|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_4} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 5264#L310 [2597] L310-->L311: Formula: (= v_~m_pc~0_4 1) InVars {~m_pc~0=v_~m_pc~0_4} OutVars{~m_pc~0=v_~m_pc~0_4} AuxVars[] AssignedVars[] 5411#L311 [2732] L311-->L321: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_10 1) (= 1 v_~M_E~0_8)) InVars {~M_E~0=v_~M_E~0_8} OutVars{~M_E~0=v_~M_E~0_8, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_10} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 5406#L321 [4267] L321-->L815: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 5407#L815 [3682] L815-->L815-2: Formula: (and (= v_~m_st~0_5 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_11)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} OutVars{~m_st~0=v_~m_st~0_5, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} AuxVars[] AssignedVars[~m_st~0] 5642#L815-2 [2961] L815-2-->L329: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 5578#L329 [2848] L329-->L330: Formula: (= v_~t1_pc~0_4 1) InVars {~t1_pc~0=v_~t1_pc~0_4} OutVars{~t1_pc~0=v_~t1_pc~0_4} AuxVars[] AssignedVars[] 5579#L330 [3036] L330-->L340: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_10 1) (= v_~E_1~0_7 1)) InVars {~E_1~0=v_~E_1~0_7} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_10, ~E_1~0=v_~E_1~0_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 5573#L340 [4268] L340-->L823: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 5574#L823 [3688] L823-->L823-2: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___0~0_11 0) (= v_~t1_st~0_5 0)) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_11} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_11, ~t1_st~0=v_~t1_st~0_5} AuxVars[] AssignedVars[~t1_st~0] 5728#L823-2 [3235] L823-2-->L348: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_4|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 5712#L348 [3143] L348-->L349: Formula: (= v_~t2_pc~0_4 1) InVars {~t2_pc~0=v_~t2_pc~0_4} OutVars{~t2_pc~0=v_~t2_pc~0_4} AuxVars[] AssignedVars[] 5713#L349 [3267] L349-->L359: Formula: (and (= v_~E_2~0_7 1) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_10 1)) InVars {~E_2~0=v_~E_2~0_7} OutVars{~E_2~0=v_~E_2~0_7, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_10} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 5711#L359 [4269] L359-->L831: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 5386#L831 [3694] L831-->L831-2: Formula: (and (= v_~t2_st~0_5 0) (> v_ULTIMATE.start_activate_threads_~tmp___1~0_11 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_11} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_11, ~t2_st~0=v_~t2_st~0_5} AuxVars[] AssignedVars[~t2_st~0] 5374#L831-2 [2520] L831-2-->L367: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_4|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 5314#L367 [3695] L367-->L367-2: Formula: (> 1 v_~t3_pc~0_5) InVars {~t3_pc~0=v_~t3_pc~0_5} OutVars{~t3_pc~0=v_~t3_pc~0_5} AuxVars[] AssignedVars[] 5292#L367-2 [2438] L367-2-->L378: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 5293#L378 [4270] L378-->L839: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 5313#L839 [2791] L839-->L839-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} AuxVars[] AssignedVars[] 5551#L839-2 [2794] L839-2-->L386: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_7, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 5481#L386 [2675] L386-->L387: Formula: (= v_~t4_pc~0_4 1) InVars {~t4_pc~0=v_~t4_pc~0_4} OutVars{~t4_pc~0=v_~t4_pc~0_4} AuxVars[] AssignedVars[] 5400#L387 [2588] L387-->L397: Formula: (and (= v_~E_4~0_7 1) (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_10 1)) InVars {~E_4~0=v_~E_4~0_7} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_10, ~E_4~0=v_~E_4~0_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 5402#L397 [4271] L397-->L847: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 5480#L847 [3084] L847-->L847-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} AuxVars[] AssignedVars[] 5674#L847-2 [3064] L847-2-->L405: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_4|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 5675#L405 [3708] L405-->L405-2: Formula: (> 1 v_~t5_pc~0_5) InVars {~t5_pc~0=v_~t5_pc~0_5} OutVars{~t5_pc~0=v_~t5_pc~0_5} AuxVars[] AssignedVars[] 5611#L405-2 [2940] L405-2-->L416: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 5610#L416 [4272] L416-->L855: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 5681#L855 [3711] L855-->L855-2: Formula: (and (> v_ULTIMATE.start_activate_threads_~tmp___4~0_11 0) (= v_~t5_st~0_7 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_11} OutVars{~t5_st~0=v_~t5_st~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_11} AuxVars[] AssignedVars[~t5_st~0] 5682#L855-2 [3093] L855-2-->L424: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_4|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 5358#L424 [3714] L424-->L424-2: Formula: (> v_~t6_pc~0_5 1) InVars {~t6_pc~0=v_~t6_pc~0_5} OutVars{~t6_pc~0=v_~t6_pc~0_5} AuxVars[] AssignedVars[] 5359#L424-2 [2503] L424-2-->L435: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 5355#L435 [4273] L435-->L863: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___5~0_49 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_28|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_28|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 5279#L863 [2425] L863-->L863-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___5~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} AuxVars[] AssignedVars[] 5250#L863-2 [3720] L863-2-->L733-1: Formula: (< v_~M_E~0_15 1) InVars {~M_E~0=v_~M_E~0_15} OutVars{~M_E~0=v_~M_E~0_15} AuxVars[] AssignedVars[] 5251#L733-1 [3722] L733-1-->L738-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 5644#L738-1 [3724] L738-1-->L743-1: Formula: (> 1 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 5377#L743-1 [3726] L743-1-->L748-1: Formula: (< 1 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 5378#L748-1 [3727] L748-1-->L753-1: Formula: (< v_~T4_E~0_10 1) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 5258#L753-1 [2407] L753-1-->L758-1: Formula: (and (= v_~T5_E~0_8 2) (= v_~T5_E~0_9 1)) InVars {~T5_E~0=v_~T5_E~0_9} OutVars{~T5_E~0=v_~T5_E~0_8} AuxVars[] AssignedVars[~T5_E~0] 5259#L758-1 [3732] L758-1-->L763-1: Formula: (< v_~T6_E~0_10 1) InVars {~T6_E~0=v_~T6_E~0_10} OutVars{~T6_E~0=v_~T6_E~0_10} AuxVars[] AssignedVars[] 5330#L763-1 [2475] L763-1-->L768-1: Formula: (and (= v_~E_1~0_12 2) (= 1 v_~E_1~0_13)) InVars {~E_1~0=v_~E_1~0_13} OutVars{~E_1~0=v_~E_1~0_12} AuxVars[] AssignedVars[~E_1~0] 5331#L768-1 [3736] L768-1-->L773-1: Formula: (< 1 v_~E_2~0_14) InVars {~E_2~0=v_~E_2~0_14} OutVars{~E_2~0=v_~E_2~0_14} AuxVars[] AssignedVars[] 5539#L773-1 [2767] L773-1-->L778-1: Formula: (and (= 1 v_~E_3~0_13) (= v_~E_3~0_12 2)) InVars {~E_3~0=v_~E_3~0_13} OutVars{~E_3~0=v_~E_3~0_12} AuxVars[] AssignedVars[~E_3~0] 5540#L778-1 [3740] L778-1-->L783-1: Formula: (< 1 v_~E_4~0_14) InVars {~E_4~0=v_~E_4~0_14} OutVars{~E_4~0=v_~E_4~0_14} AuxVars[] AssignedVars[] 5431#L783-1 [3742] L783-1-->L788-1: Formula: (> 1 v_~E_5~0_14) InVars {~E_5~0=v_~E_5~0_14} OutVars{~E_5~0=v_~E_5~0_14} AuxVars[] AssignedVars[] 5432#L788-1 [3743] L788-1-->L1014-1: Formula: (> 1 v_~E_6~0_14) InVars {~E_6~0=v_~E_6~0_14} OutVars{~E_6~0=v_~E_6~0_14} AuxVars[] AssignedVars[] 5268#L1014-1 [2020-06-22 00:13:02,855 INFO L796 eck$LassoCheckResult]: Loop: 5268#L1014-1 [4274] L1014-1-->L635: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp_ndt_7~0=v_ULTIMATE.start_eval_~tmp_ndt_7~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp_ndt_7~0] 5233#L635 [4275] L635-->L494: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_37} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 5606#L494 [2876] L494-->L531: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21 1) (= v_~m_st~0_8 0)) InVars {~m_st~0=v_~m_st~0_8} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21, ~m_st~0=v_~m_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 5302#L531 [4276] L531-->L546: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 5528#L546 [4278] L546-->L660-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 5671#L660-2 [3747] L660-2-->L660-4: Formula: (> v_~M_E~0_30 0) InVars {~M_E~0=v_~M_E~0_30} OutVars{~M_E~0=v_~M_E~0_30} AuxVars[] AssignedVars[] 5672#L660-4 [3058] L660-4-->L665-3: Formula: (and (= v_~T1_E~0_11 1) (= v_~T1_E~0_12 0)) InVars {~T1_E~0=v_~T1_E~0_12} OutVars{~T1_E~0=v_~T1_E~0_11} AuxVars[] AssignedVars[~T1_E~0] 5243#L665-3 [2394] L665-3-->L670-3: Formula: (and (= 0 v_~T2_E~0_12) (= v_~T2_E~0_11 1)) InVars {~T2_E~0=v_~T2_E~0_12} OutVars{~T2_E~0=v_~T2_E~0_11} AuxVars[] AssignedVars[~T2_E~0] 5244#L670-3 [3761] L670-3-->L675-3: Formula: (> 0 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 5320#L675-3 [2467] L675-3-->L680-3: Formula: (and (= v_~T4_E~0_11 1) (= v_~T4_E~0_12 0)) InVars {~T4_E~0=v_~T4_E~0_12} OutVars{~T4_E~0=v_~T4_E~0_11} AuxVars[] AssignedVars[~T4_E~0] 5321#L680-3 [3776] L680-3-->L685-3: Formula: (< 0 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 5547#L685-3 [3785] L685-3-->L690-3: Formula: (> v_~T6_E~0_13 0) InVars {~T6_E~0=v_~T6_E~0_13} OutVars{~T6_E~0=v_~T6_E~0_13} AuxVars[] AssignedVars[] 5548#L690-3 [3795] L690-3-->L695-3: Formula: (< 0 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 5426#L695-3 [2609] L695-3-->L700-3: Formula: (and (= 0 v_~E_2~0_30) (= v_~E_2~0_29 1)) InVars {~E_2~0=v_~E_2~0_30} OutVars{~E_2~0=v_~E_2~0_29} AuxVars[] AssignedVars[~E_2~0] 5427#L700-3 [3155] L700-3-->L705-3: Formula: (and (= v_~E_3~0_29 1) (= 0 v_~E_3~0_30)) InVars {~E_3~0=v_~E_3~0_30} OutVars{~E_3~0=v_~E_3~0_29} AuxVars[] AssignedVars[~E_3~0] 5489#L705-3 [2688] L705-3-->L710-3: Formula: (and (= v_~E_4~0_29 1) (= 0 v_~E_4~0_30)) InVars {~E_4~0=v_~E_4~0_30} OutVars{~E_4~0=v_~E_4~0_29} AuxVars[] AssignedVars[~E_4~0] 5371#L710-3 [2515] L710-3-->L715-3: Formula: (and (= 0 v_~E_5~0_30) (= v_~E_5~0_29 1)) InVars {~E_5~0=v_~E_5~0_30} OutVars{~E_5~0=v_~E_5~0_29} AuxVars[] AssignedVars[~E_5~0] 5372#L715-3 [3048] L715-3-->L720-3: Formula: (and (= v_~E_6~0_29 1) (= 0 v_~E_6~0_30)) InVars {~E_6~0=v_~E_6~0_30} OutVars{~E_6~0=v_~E_6~0_29} AuxVars[] AssignedVars[~E_6~0] 5234#L720-3 [2388] L720-3-->L310-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_43, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_43, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_25|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_25|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_25|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_43, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_43, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_43, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_25|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_25|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_25|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_25|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_43, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_25|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_43, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_43} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 5235#L310-21 [2779] L310-21-->L311-7: Formula: (= v_~m_pc~0_23 1) InVars {~m_pc~0=v_~m_pc~0_23} OutVars{~m_pc~0=v_~m_pc~0_23} AuxVars[] AssignedVars[] 5512#L311-7 [2720] L311-7-->L321-7: Formula: (and (= v_~M_E~0_31 1) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_46 1)) InVars {~M_E~0=v_~M_E~0_31} OutVars{~M_E~0=v_~M_E~0_31, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_46} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 5513#L321-7 [4303] L321-7-->L815-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 5474#L815-21 [3897] L815-21-->L815-23: Formula: (and (> 0 v_ULTIMATE.start_activate_threads_~tmp~1_47) (= v_~m_st~0_20 0)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_47} OutVars{~m_st~0=v_~m_st~0_20, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_47} AuxVars[] AssignedVars[~m_st~0] 5455#L815-23 [2638] L815-23-->L329-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 5456#L329-21 [3038] L329-21-->L330-7: Formula: (= v_~t1_pc~0_23 1) InVars {~t1_pc~0=v_~t1_pc~0_23} OutVars{~t1_pc~0=v_~t1_pc~0_23} AuxVars[] AssignedVars[] 5651#L330-7 [2981] L330-7-->L340-7: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_52 1) (= 1 v_~E_1~0_32)) InVars {~E_1~0=v_~E_1~0_32} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_52, ~E_1~0=v_~E_1~0_32} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 5566#L340-7 [4310] L340-7-->L823-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 5567#L823-21 [2931] L823-21-->L823-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} AuxVars[] AssignedVars[] 5626#L823-23 [2934] L823-23-->L348-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_25|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 5628#L348-21 [3306] L348-21-->L349-7: Formula: (= 1 v_~t2_pc~0_23) InVars {~t2_pc~0=v_~t2_pc~0_23} OutVars{~t2_pc~0=v_~t2_pc~0_23} AuxVars[] AssignedVars[] 5732#L349-7 [3255] L349-7-->L359-7: Formula: (and (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_52 1) (= 1 v_~E_2~0_32)) InVars {~E_2~0=v_~E_2~0_32} OutVars{~E_2~0=v_~E_2~0_32, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_52} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 5708#L359-7 [4317] L359-7-->L831-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 5349#L831-21 [2490] L831-21-->L831-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} AuxVars[] AssignedVars[] 5350#L831-23 [3197] L831-23-->L367-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_25|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 5260#L367-21 [2409] L367-21-->L368-7: Formula: (= v_~t3_pc~0_23 1) InVars {~t3_pc~0=v_~t3_pc~0_23} OutVars{~t3_pc~0=v_~t3_pc~0_23} AuxVars[] AssignedVars[] 5261#L368-7 [2539] L368-7-->L378-7: Formula: (and (= 1 v_~E_3~0_32) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_52 1)) InVars {~E_3~0=v_~E_3~0_32} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_52, ~E_3~0=v_~E_3~0_32} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 5230#L378-7 [4324] L378-7-->L839-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 5284#L839-21 [4023] L839-21-->L839-23: Formula: (and (= v_~t3_st~0_21 0) (> v_ULTIMATE.start_activate_threads_~tmp___2~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} OutVars{~t3_st~0=v_~t3_st~0_21, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} AuxVars[] AssignedVars[~t3_st~0] 5508#L839-23 [2722] L839-23-->L386-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_49, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 5435#L386-21 [4037] L386-21-->L386-23: Formula: (< 1 v_~t4_pc~0_24) InVars {~t4_pc~0=v_~t4_pc~0_24} OutVars{~t4_pc~0=v_~t4_pc~0_24} AuxVars[] AssignedVars[] 5436#L386-23 [2623] L386-23-->L397-7: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 5442#L397-7 [4331] L397-7-->L847-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 5471#L847-21 [4065] L847-21-->L847-23: Formula: (and (= v_~t4_st~0_22 0) (< v_ULTIMATE.start_activate_threads_~tmp___3~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47, ~t4_st~0=v_~t4_st~0_22} AuxVars[] AssignedVars[~t4_st~0] 5653#L847-23 [2983] L847-23-->L405-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_25|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 5617#L405-21 [2911] L405-21-->L406-7: Formula: (= v_~t5_pc~0_23 1) InVars {~t5_pc~0=v_~t5_pc~0_23} OutVars{~t5_pc~0=v_~t5_pc~0_23} AuxVars[] AssignedVars[] 5603#L406-7 [2874] L406-7-->L416-7: Formula: (and (= 1 v_~E_5~0_32) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_52 1)) InVars {~E_5~0=v_~E_5~0_32} OutVars{~E_5~0=v_~E_5~0_32, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_52} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 5605#L416-7 [4338] L416-7-->L855-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 5622#L855-21 [3251] L855-21-->L855-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} AuxVars[] AssignedVars[] 5731#L855-23 [3257] L855-23-->L424-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_25|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 5718#L424-21 [3173] L424-21-->L425-7: Formula: (= 1 v_~t6_pc~0_23) InVars {~t6_pc~0=v_~t6_pc~0_23} OutVars{~t6_pc~0=v_~t6_pc~0_23} AuxVars[] AssignedVars[] 5700#L425-7 [3114] L425-7-->L435-7: Formula: (and (= 1 v_~E_6~0_32) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_52 1)) InVars {~E_6~0=v_~E_6~0_32} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_52, ~E_6~0=v_~E_6~0_32} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 5344#L435-7 [4340] L435-7-->L863-21: Formula: (and (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___5~0_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_35|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_41|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 5345#L863-21 [4135] L863-21-->L863-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___5~0_47 0) (= v_~t6_st~0_22 0)) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} OutVars{~t6_st~0=v_~t6_st~0_22, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} AuxVars[] AssignedVars[~t6_st~0] 5387#L863-23 [4137] L863-23-->L733-3: Formula: (< v_~M_E~0_35 1) InVars {~M_E~0=v_~M_E~0_35} OutVars{~M_E~0=v_~M_E~0_35} AuxVars[] AssignedVars[] 5388#L733-3 [3184] L733-3-->L738-3: Formula: (and (= v_~T1_E~0_15 1) (= v_~T1_E~0_14 2)) InVars {~T1_E~0=v_~T1_E~0_15} OutVars{~T1_E~0=v_~T1_E~0_14} AuxVars[] AssignedVars[~T1_E~0] 5647#L738-3 [2971] L738-3-->L743-3: Formula: (and (= v_~T2_E~0_14 2) (= 1 v_~T2_E~0_15)) InVars {~T2_E~0=v_~T2_E~0_15} OutVars{~T2_E~0=v_~T2_E~0_14} AuxVars[] AssignedVars[~T2_E~0] 5367#L743-3 [4144] L743-3-->L748-3: Formula: (> 1 v_~T3_E~0_16) InVars {~T3_E~0=v_~T3_E~0_16} OutVars{~T3_E~0=v_~T3_E~0_16} AuxVars[] AssignedVars[] 5368#L748-3 [4145] L748-3-->L753-3: Formula: (> v_~T4_E~0_16 1) InVars {~T4_E~0=v_~T4_E~0_16} OutVars{~T4_E~0=v_~T4_E~0_16} AuxVars[] AssignedVars[] 5225#L753-3 [4147] L753-3-->L758-3: Formula: (> 1 v_~T5_E~0_16) InVars {~T5_E~0=v_~T5_E~0_16} OutVars{~T5_E~0=v_~T5_E~0_16} AuxVars[] AssignedVars[] 5226#L758-3 [4149] L758-3-->L763-3: Formula: (> v_~T6_E~0_16 1) InVars {~T6_E~0=v_~T6_E~0_16} OutVars{~T6_E~0=v_~T6_E~0_16} AuxVars[] AssignedVars[] 5316#L763-3 [4151] L763-3-->L768-3: Formula: (< 1 v_~E_1~0_36) InVars {~E_1~0=v_~E_1~0_36} OutVars{~E_1~0=v_~E_1~0_36} AuxVars[] AssignedVars[] 5317#L768-3 [3219] L768-3-->L773-3: Formula: (and (= 1 v_~E_2~0_35) (= v_~E_2~0_34 2)) InVars {~E_2~0=v_~E_2~0_35} OutVars{~E_2~0=v_~E_2~0_34} AuxVars[] AssignedVars[~E_2~0] 5542#L773-3 [2775] L773-3-->L778-3: Formula: (and (= 1 v_~E_3~0_35) (= v_~E_3~0_34 2)) InVars {~E_3~0=v_~E_3~0_35} OutVars{~E_3~0=v_~E_3~0_34} AuxVars[] AssignedVars[~E_3~0] 5543#L778-3 [3308] L778-3-->L783-3: Formula: (and (= 1 v_~E_4~0_35) (= v_~E_4~0_34 2)) InVars {~E_4~0=v_~E_4~0_35} OutVars{~E_4~0=v_~E_4~0_34} AuxVars[] AssignedVars[~E_4~0] 5438#L783-3 [4160] L783-3-->L788-3: Formula: (< 1 v_~E_5~0_36) InVars {~E_5~0=v_~E_5~0_36} OutVars{~E_5~0=v_~E_5~0_36} AuxVars[] AssignedVars[] 5439#L788-3 [4161] L788-3-->L793-3: Formula: (> 1 v_~E_6~0_36) InVars {~E_6~0=v_~E_6~0_36} OutVars{~E_6~0=v_~E_6~0_36} AuxVars[] AssignedVars[] 5645#L793-3 [2966] L793-3-->L494-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_30} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 5607#L494-1 [2878] L494-1-->L531-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33 1) (= 0 v_~m_st~0_21)) InVars {~m_st~0=v_~m_st~0_21} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33, ~m_st~0=v_~m_st~0_21} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 5304#L531-1 [4341] L531-1-->L1033: Formula: (and (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp~3] 5529#L1033 [4169] L1033-->L1033-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_6) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} AuxVars[] AssignedVars[] 5274#L1033-1 [2919] L1033-1-->L494-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_3|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_6, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_exists_runnable_thread_~__retres1~7, ULTIMATE.start_stop_simulation_#res] 5608#L494-2 [2882] L494-2-->L531-2: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9 1) (= v_~m_st~0_6 0)) InVars {~m_st~0=v_~m_st~0_6} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9, ~m_st~0=v_~m_st~0_6} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 5308#L531-2 [4343] L531-2-->L988: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 5534#L988 [3240] L988-->L995: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 5267#L995 [4354] L995-->L1014-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_6|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_#t~ret17, ULTIMATE.start_stop_simulation_#res] 5268#L1014-1 [2020-06-22 00:13:02,855 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:02,855 INFO L82 PathProgramCache]: Analyzing trace with hash -2064153852, now seen corresponding path program 1 times [2020-06-22 00:13:02,856 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:02,856 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:02,857 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:02,857 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:02,857 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:02,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:02,900 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:02,901 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:02,901 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-06-22 00:13:02,901 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-06-22 00:13:02,902 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:02,902 INFO L82 PathProgramCache]: Analyzing trace with hash 444577190, now seen corresponding path program 4 times [2020-06-22 00:13:02,902 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:02,902 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:02,903 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:02,903 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:02,903 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:02,907 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:02,938 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:02,938 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:02,938 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2020-06-22 00:13:02,939 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-06-22 00:13:02,939 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-06-22 00:13:02,939 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-06-22 00:13:02,939 INFO L87 Difference]: Start difference. First operand 518 states and 1138 transitions. cyclomatic complexity: 621 Second operand 3 states. [2020-06-22 00:13:03,515 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-06-22 00:13:03,516 INFO L93 Difference]: Finished difference Result 518 states and 1137 transitions. [2020-06-22 00:13:03,516 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-06-22 00:13:03,516 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 518 states and 1137 transitions. [2020-06-22 00:13:03,520 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 442 [2020-06-22 00:13:03,523 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 518 states to 518 states and 1137 transitions. [2020-06-22 00:13:03,524 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 518 [2020-06-22 00:13:03,524 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 518 [2020-06-22 00:13:03,524 INFO L73 IsDeterministic]: Start isDeterministic. Operand 518 states and 1137 transitions. [2020-06-22 00:13:03,525 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-06-22 00:13:03,525 INFO L706 BuchiCegarLoop]: Abstraction has 518 states and 1137 transitions. [2020-06-22 00:13:03,526 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 518 states and 1137 transitions. [2020-06-22 00:13:03,534 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 518 to 518. [2020-06-22 00:13:03,534 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 518 states. [2020-06-22 00:13:03,535 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 518 states to 518 states and 1137 transitions. [2020-06-22 00:13:03,535 INFO L729 BuchiCegarLoop]: Abstraction has 518 states and 1137 transitions. [2020-06-22 00:13:03,536 INFO L609 BuchiCegarLoop]: Abstraction has 518 states and 1137 transitions. [2020-06-22 00:13:03,536 INFO L442 BuchiCegarLoop]: ======== Iteration 7============ [2020-06-22 00:13:03,536 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 518 states and 1137 transitions. [2020-06-22 00:13:03,538 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 442 [2020-06-22 00:13:03,538 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-06-22 00:13:03,538 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-06-22 00:13:03,540 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:03,540 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:03,541 INFO L794 eck$LassoCheckResult]: Stem: 6703#ULTIMATE.startENTRY [4266] ULTIMATE.startENTRY-->L444: Formula: (and (= 1 v_~t6_i~0_7) (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~M_E~0_37 2) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 0 v_~t6_pc~0_26) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_6~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= v_~T6_E~0_18 2) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~t6_st~0_24) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t6_pc~0=v_~t6_pc~0_26, ~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~T6_E~0=v_~T6_E~0_18, ~M_E~0=v_~M_E~0_37, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ~T4_E~0=v_~T4_E~0_18, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_4|, ~t6_i~0=v_~t6_i~0_7, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ULTIMATE.start_main_~__retres1~8=v_ULTIMATE.start_main_~__retres1~8_6, ~T2_E~0=v_~T2_E~0_18, ~t6_st~0=v_~t6_st~0_24, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_6~0=v_~E_6~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t6_pc~0, ~t5_i~0, ~t1_pc~0, ~t5_st~0, ~T6_E~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ~T4_E~0, ULTIMATE.start_start_simulation_#t~ret17, ~t6_i~0, ~t2_st~0, ~t2_pc~0, ULTIMATE.start_main_~__retres1~8, ~T2_E~0, ~t6_st~0, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_6~0, ULTIMATE.start_main_#res, ~E_2~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 6353#L444 [2453] L444-->L451-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 6354#L451-1 [3030] L451-1-->L456-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 6439#L456-1 [2574] L456-1-->L461-1: Formula: (and (= v_~t2_st~0_2 0) (= 1 v_~t2_i~0_3)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_2} AuxVars[] AssignedVars[~t2_st~0] 6440#L461-1 [2880] L461-1-->L466-1: Formula: (and (= v_~t3_st~0_3 0) (= v_~t3_i~0_3 1)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_3, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 6355#L466-1 [3646] L466-1-->L471-1: Formula: (and (< v_~t4_i~0_4 1) (= v_~t4_st~0_5 2)) InVars {~t4_i~0=v_~t4_i~0_4} OutVars{~t4_i~0=v_~t4_i~0_4, ~t4_st~0=v_~t4_st~0_5} AuxVars[] AssignedVars[~t4_st~0] 6356#L471-1 [3647] L471-1-->L476-1: Formula: (and (= v_~t5_st~0_5 2) (< v_~t5_i~0_4 1)) InVars {~t5_i~0=v_~t5_i~0_4} OutVars{~t5_i~0=v_~t5_i~0_4, ~t5_st~0=v_~t5_st~0_5} AuxVars[] AssignedVars[~t5_st~0] 6579#L476-1 [2761] L476-1-->L481-1: Formula: (and (= 1 v_~t6_i~0_3) (= v_~t6_st~0_4 0)) InVars {~t6_i~0=v_~t6_i~0_3} OutVars{~t6_st~0=v_~t6_st~0_4, ~t6_i~0=v_~t6_i~0_3} AuxVars[] AssignedVars[~t6_st~0] 6580#L481-1 [3652] L481-1-->L660-1: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 6714#L660-1 [3654] L660-1-->L665-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 6271#L665-1 [2383] L665-1-->L670-1: Formula: (and (= 0 v_~T2_E~0_3) (= v_~T2_E~0_2 1)) InVars {~T2_E~0=v_~T2_E~0_3} OutVars{~T2_E~0=v_~T2_E~0_2} AuxVars[] AssignedVars[~T2_E~0] 6272#L670-1 [2894] L670-1-->L675-1: Formula: (and (= v_~T3_E~0_2 1) (= v_~T3_E~0_3 0)) InVars {~T3_E~0=v_~T3_E~0_3} OutVars{~T3_E~0=v_~T3_E~0_2} AuxVars[] AssignedVars[~T3_E~0] 6362#L675-1 [3660] L675-1-->L680-1: Formula: (< v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 6363#L680-1 [3662] L680-1-->L685-1: Formula: (< v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 6588#L685-1 [3663] L685-1-->L690-1: Formula: (< 0 v_~T6_E~0_4) InVars {~T6_E~0=v_~T6_E~0_4} OutVars{~T6_E~0=v_~T6_E~0_4} AuxVars[] AssignedVars[] 6589#L690-1 [3310] L690-1-->L695-1: Formula: (and (= v_~E_1~0_5 0) (= v_~E_1~0_4 1)) InVars {~E_1~0=v_~E_1~0_5} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[~E_1~0] 6484#L695-1 [2621] L695-1-->L700-1: Formula: (and (= v_~E_2~0_4 1) (= v_~E_2~0_5 0)) InVars {~E_2~0=v_~E_2~0_5} OutVars{~E_2~0=v_~E_2~0_4} AuxVars[] AssignedVars[~E_2~0] 6485#L700-1 [3180] L700-1-->L705-1: Formula: (and (= v_~E_3~0_5 0) (= v_~E_3~0_4 1)) InVars {~E_3~0=v_~E_3~0_5} OutVars{~E_3~0=v_~E_3~0_4} AuxVars[] AssignedVars[~E_3~0] 6690#L705-1 [3672] L705-1-->L710-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 6423#L710-1 [2525] L710-1-->L715-1: Formula: (and (= v_~E_5~0_3 0) (= v_~E_5~0_2 1)) InVars {~E_5~0=v_~E_5~0_3} OutVars{~E_5~0=v_~E_5~0_2} AuxVars[] AssignedVars[~E_5~0] 6424#L715-1 [3676] L715-1-->L720-1: Formula: (< v_~E_6~0_4 0) InVars {~E_6~0=v_~E_6~0_4} OutVars{~E_6~0=v_~E_6~0_4} AuxVars[] AssignedVars[] 6307#L720-1 [2412] L720-1-->L310: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_7, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_4|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_4|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_7, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_4, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_4, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_2|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_2|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_4|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_4|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_7, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_2|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_4} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 6308#L310 [2597] L310-->L311: Formula: (= v_~m_pc~0_4 1) InVars {~m_pc~0=v_~m_pc~0_4} OutVars{~m_pc~0=v_~m_pc~0_4} AuxVars[] AssignedVars[] 6455#L311 [2732] L311-->L321: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_10 1) (= 1 v_~M_E~0_8)) InVars {~M_E~0=v_~M_E~0_8} OutVars{~M_E~0=v_~M_E~0_8, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_10} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 6450#L321 [4267] L321-->L815: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 6451#L815 [3682] L815-->L815-2: Formula: (and (= v_~m_st~0_5 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_11)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} OutVars{~m_st~0=v_~m_st~0_5, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} AuxVars[] AssignedVars[~m_st~0] 6686#L815-2 [2961] L815-2-->L329: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 6622#L329 [2848] L329-->L330: Formula: (= v_~t1_pc~0_4 1) InVars {~t1_pc~0=v_~t1_pc~0_4} OutVars{~t1_pc~0=v_~t1_pc~0_4} AuxVars[] AssignedVars[] 6623#L330 [3036] L330-->L340: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_10 1) (= v_~E_1~0_7 1)) InVars {~E_1~0=v_~E_1~0_7} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_10, ~E_1~0=v_~E_1~0_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 6617#L340 [4268] L340-->L823: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 6618#L823 [3688] L823-->L823-2: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___0~0_11 0) (= v_~t1_st~0_5 0)) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_11} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_11, ~t1_st~0=v_~t1_st~0_5} AuxVars[] AssignedVars[~t1_st~0] 6772#L823-2 [3235] L823-2-->L348: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_4|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 6756#L348 [3143] L348-->L349: Formula: (= v_~t2_pc~0_4 1) InVars {~t2_pc~0=v_~t2_pc~0_4} OutVars{~t2_pc~0=v_~t2_pc~0_4} AuxVars[] AssignedVars[] 6757#L349 [3267] L349-->L359: Formula: (and (= v_~E_2~0_7 1) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_10 1)) InVars {~E_2~0=v_~E_2~0_7} OutVars{~E_2~0=v_~E_2~0_7, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_10} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 6755#L359 [4269] L359-->L831: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 6430#L831 [3694] L831-->L831-2: Formula: (and (= v_~t2_st~0_5 0) (> v_ULTIMATE.start_activate_threads_~tmp___1~0_11 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_11} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_11, ~t2_st~0=v_~t2_st~0_5} AuxVars[] AssignedVars[~t2_st~0] 6418#L831-2 [2520] L831-2-->L367: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_4|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 6358#L367 [3695] L367-->L367-2: Formula: (> 1 v_~t3_pc~0_5) InVars {~t3_pc~0=v_~t3_pc~0_5} OutVars{~t3_pc~0=v_~t3_pc~0_5} AuxVars[] AssignedVars[] 6336#L367-2 [2438] L367-2-->L378: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 6337#L378 [4270] L378-->L839: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 6357#L839 [2791] L839-->L839-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} AuxVars[] AssignedVars[] 6595#L839-2 [2794] L839-2-->L386: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_7, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 6525#L386 [2675] L386-->L387: Formula: (= v_~t4_pc~0_4 1) InVars {~t4_pc~0=v_~t4_pc~0_4} OutVars{~t4_pc~0=v_~t4_pc~0_4} AuxVars[] AssignedVars[] 6444#L387 [2588] L387-->L397: Formula: (and (= v_~E_4~0_7 1) (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_10 1)) InVars {~E_4~0=v_~E_4~0_7} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_10, ~E_4~0=v_~E_4~0_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 6446#L397 [4271] L397-->L847: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 6524#L847 [3084] L847-->L847-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} AuxVars[] AssignedVars[] 6718#L847-2 [3064] L847-2-->L405: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_4|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 6719#L405 [3708] L405-->L405-2: Formula: (> 1 v_~t5_pc~0_5) InVars {~t5_pc~0=v_~t5_pc~0_5} OutVars{~t5_pc~0=v_~t5_pc~0_5} AuxVars[] AssignedVars[] 6655#L405-2 [2940] L405-2-->L416: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 6654#L416 [4272] L416-->L855: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 6725#L855 [3711] L855-->L855-2: Formula: (and (> v_ULTIMATE.start_activate_threads_~tmp___4~0_11 0) (= v_~t5_st~0_7 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_11} OutVars{~t5_st~0=v_~t5_st~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_11} AuxVars[] AssignedVars[~t5_st~0] 6726#L855-2 [3093] L855-2-->L424: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_4|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 6402#L424 [3714] L424-->L424-2: Formula: (> v_~t6_pc~0_5 1) InVars {~t6_pc~0=v_~t6_pc~0_5} OutVars{~t6_pc~0=v_~t6_pc~0_5} AuxVars[] AssignedVars[] 6403#L424-2 [2503] L424-2-->L435: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 6399#L435 [4273] L435-->L863: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___5~0_49 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_28|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_28|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 6323#L863 [2425] L863-->L863-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___5~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} AuxVars[] AssignedVars[] 6294#L863-2 [3720] L863-2-->L733-1: Formula: (< v_~M_E~0_15 1) InVars {~M_E~0=v_~M_E~0_15} OutVars{~M_E~0=v_~M_E~0_15} AuxVars[] AssignedVars[] 6295#L733-1 [3722] L733-1-->L738-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 6688#L738-1 [3724] L738-1-->L743-1: Formula: (> 1 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 6421#L743-1 [3726] L743-1-->L748-1: Formula: (< 1 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 6422#L748-1 [3727] L748-1-->L753-1: Formula: (< v_~T4_E~0_10 1) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 6302#L753-1 [2407] L753-1-->L758-1: Formula: (and (= v_~T5_E~0_8 2) (= v_~T5_E~0_9 1)) InVars {~T5_E~0=v_~T5_E~0_9} OutVars{~T5_E~0=v_~T5_E~0_8} AuxVars[] AssignedVars[~T5_E~0] 6303#L758-1 [3732] L758-1-->L763-1: Formula: (< v_~T6_E~0_10 1) InVars {~T6_E~0=v_~T6_E~0_10} OutVars{~T6_E~0=v_~T6_E~0_10} AuxVars[] AssignedVars[] 6374#L763-1 [2475] L763-1-->L768-1: Formula: (and (= v_~E_1~0_12 2) (= 1 v_~E_1~0_13)) InVars {~E_1~0=v_~E_1~0_13} OutVars{~E_1~0=v_~E_1~0_12} AuxVars[] AssignedVars[~E_1~0] 6375#L768-1 [3736] L768-1-->L773-1: Formula: (< 1 v_~E_2~0_14) InVars {~E_2~0=v_~E_2~0_14} OutVars{~E_2~0=v_~E_2~0_14} AuxVars[] AssignedVars[] 6583#L773-1 [2767] L773-1-->L778-1: Formula: (and (= 1 v_~E_3~0_13) (= v_~E_3~0_12 2)) InVars {~E_3~0=v_~E_3~0_13} OutVars{~E_3~0=v_~E_3~0_12} AuxVars[] AssignedVars[~E_3~0] 6584#L778-1 [3740] L778-1-->L783-1: Formula: (< 1 v_~E_4~0_14) InVars {~E_4~0=v_~E_4~0_14} OutVars{~E_4~0=v_~E_4~0_14} AuxVars[] AssignedVars[] 6475#L783-1 [3742] L783-1-->L788-1: Formula: (> 1 v_~E_5~0_14) InVars {~E_5~0=v_~E_5~0_14} OutVars{~E_5~0=v_~E_5~0_14} AuxVars[] AssignedVars[] 6476#L788-1 [3743] L788-1-->L1014-1: Formula: (> 1 v_~E_6~0_14) InVars {~E_6~0=v_~E_6~0_14} OutVars{~E_6~0=v_~E_6~0_14} AuxVars[] AssignedVars[] 6312#L1014-1 [2020-06-22 00:13:03,542 INFO L796 eck$LassoCheckResult]: Loop: 6312#L1014-1 [4274] L1014-1-->L635: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp_ndt_7~0=v_ULTIMATE.start_eval_~tmp_ndt_7~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp_ndt_7~0] 6277#L635 [4275] L635-->L494: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_37} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 6650#L494 [2876] L494-->L531: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21 1) (= v_~m_st~0_8 0)) InVars {~m_st~0=v_~m_st~0_8} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21, ~m_st~0=v_~m_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 6346#L531 [4276] L531-->L546: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 6572#L546 [4278] L546-->L660-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 6715#L660-2 [3747] L660-2-->L660-4: Formula: (> v_~M_E~0_30 0) InVars {~M_E~0=v_~M_E~0_30} OutVars{~M_E~0=v_~M_E~0_30} AuxVars[] AssignedVars[] 6716#L660-4 [3058] L660-4-->L665-3: Formula: (and (= v_~T1_E~0_11 1) (= v_~T1_E~0_12 0)) InVars {~T1_E~0=v_~T1_E~0_12} OutVars{~T1_E~0=v_~T1_E~0_11} AuxVars[] AssignedVars[~T1_E~0] 6289#L665-3 [2394] L665-3-->L670-3: Formula: (and (= 0 v_~T2_E~0_12) (= v_~T2_E~0_11 1)) InVars {~T2_E~0=v_~T2_E~0_12} OutVars{~T2_E~0=v_~T2_E~0_11} AuxVars[] AssignedVars[~T2_E~0] 6290#L670-3 [3761] L670-3-->L675-3: Formula: (> 0 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 6364#L675-3 [2467] L675-3-->L680-3: Formula: (and (= v_~T4_E~0_11 1) (= v_~T4_E~0_12 0)) InVars {~T4_E~0=v_~T4_E~0_12} OutVars{~T4_E~0=v_~T4_E~0_11} AuxVars[] AssignedVars[~T4_E~0] 6365#L680-3 [3776] L680-3-->L685-3: Formula: (< 0 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 6591#L685-3 [3785] L685-3-->L690-3: Formula: (> v_~T6_E~0_13 0) InVars {~T6_E~0=v_~T6_E~0_13} OutVars{~T6_E~0=v_~T6_E~0_13} AuxVars[] AssignedVars[] 6592#L690-3 [3795] L690-3-->L695-3: Formula: (< 0 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 6470#L695-3 [2609] L695-3-->L700-3: Formula: (and (= 0 v_~E_2~0_30) (= v_~E_2~0_29 1)) InVars {~E_2~0=v_~E_2~0_30} OutVars{~E_2~0=v_~E_2~0_29} AuxVars[] AssignedVars[~E_2~0] 6471#L700-3 [3155] L700-3-->L705-3: Formula: (and (= v_~E_3~0_29 1) (= 0 v_~E_3~0_30)) InVars {~E_3~0=v_~E_3~0_30} OutVars{~E_3~0=v_~E_3~0_29} AuxVars[] AssignedVars[~E_3~0] 6533#L705-3 [2688] L705-3-->L710-3: Formula: (and (= v_~E_4~0_29 1) (= 0 v_~E_4~0_30)) InVars {~E_4~0=v_~E_4~0_30} OutVars{~E_4~0=v_~E_4~0_29} AuxVars[] AssignedVars[~E_4~0] 6415#L710-3 [2515] L710-3-->L715-3: Formula: (and (= 0 v_~E_5~0_30) (= v_~E_5~0_29 1)) InVars {~E_5~0=v_~E_5~0_30} OutVars{~E_5~0=v_~E_5~0_29} AuxVars[] AssignedVars[~E_5~0] 6416#L715-3 [3048] L715-3-->L720-3: Formula: (and (= v_~E_6~0_29 1) (= 0 v_~E_6~0_30)) InVars {~E_6~0=v_~E_6~0_30} OutVars{~E_6~0=v_~E_6~0_29} AuxVars[] AssignedVars[~E_6~0] 6278#L720-3 [2388] L720-3-->L310-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_43, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_43, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_25|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_25|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_25|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_43, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_43, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_43, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_25|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_25|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_25|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_25|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_43, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_25|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_43, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_43} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 6279#L310-21 [2779] L310-21-->L311-7: Formula: (= v_~m_pc~0_23 1) InVars {~m_pc~0=v_~m_pc~0_23} OutVars{~m_pc~0=v_~m_pc~0_23} AuxVars[] AssignedVars[] 6556#L311-7 [2720] L311-7-->L321-7: Formula: (and (= v_~M_E~0_31 1) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_46 1)) InVars {~M_E~0=v_~M_E~0_31} OutVars{~M_E~0=v_~M_E~0_31, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_46} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 6557#L321-7 [4303] L321-7-->L815-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 6518#L815-21 [3897] L815-21-->L815-23: Formula: (and (> 0 v_ULTIMATE.start_activate_threads_~tmp~1_47) (= v_~m_st~0_20 0)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_47} OutVars{~m_st~0=v_~m_st~0_20, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_47} AuxVars[] AssignedVars[~m_st~0] 6499#L815-23 [2638] L815-23-->L329-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 6500#L329-21 [3038] L329-21-->L330-7: Formula: (= v_~t1_pc~0_23 1) InVars {~t1_pc~0=v_~t1_pc~0_23} OutVars{~t1_pc~0=v_~t1_pc~0_23} AuxVars[] AssignedVars[] 6695#L330-7 [2981] L330-7-->L340-7: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_52 1) (= 1 v_~E_1~0_32)) InVars {~E_1~0=v_~E_1~0_32} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_52, ~E_1~0=v_~E_1~0_32} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 6610#L340-7 [4310] L340-7-->L823-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 6611#L823-21 [2931] L823-21-->L823-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} AuxVars[] AssignedVars[] 6670#L823-23 [2934] L823-23-->L348-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_25|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 6672#L348-21 [3306] L348-21-->L349-7: Formula: (= 1 v_~t2_pc~0_23) InVars {~t2_pc~0=v_~t2_pc~0_23} OutVars{~t2_pc~0=v_~t2_pc~0_23} AuxVars[] AssignedVars[] 6776#L349-7 [3255] L349-7-->L359-7: Formula: (and (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_52 1) (= 1 v_~E_2~0_32)) InVars {~E_2~0=v_~E_2~0_32} OutVars{~E_2~0=v_~E_2~0_32, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_52} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 6752#L359-7 [4317] L359-7-->L831-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 6393#L831-21 [2490] L831-21-->L831-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} AuxVars[] AssignedVars[] 6394#L831-23 [3197] L831-23-->L367-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_25|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 6305#L367-21 [3995] L367-21-->L367-23: Formula: (> v_~t3_pc~0_24 1) InVars {~t3_pc~0=v_~t3_pc~0_24} OutVars{~t3_pc~0=v_~t3_pc~0_24} AuxVars[] AssignedVars[] 6273#L367-23 [2385] L367-23-->L378-7: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 6274#L378-7 [4324] L378-7-->L839-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 6328#L839-21 [4023] L839-21-->L839-23: Formula: (and (= v_~t3_st~0_21 0) (> v_ULTIMATE.start_activate_threads_~tmp___2~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} OutVars{~t3_st~0=v_~t3_st~0_21, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} AuxVars[] AssignedVars[~t3_st~0] 6552#L839-23 [2722] L839-23-->L386-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_49, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 6479#L386-21 [4037] L386-21-->L386-23: Formula: (< 1 v_~t4_pc~0_24) InVars {~t4_pc~0=v_~t4_pc~0_24} OutVars{~t4_pc~0=v_~t4_pc~0_24} AuxVars[] AssignedVars[] 6480#L386-23 [2623] L386-23-->L397-7: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 6486#L397-7 [4331] L397-7-->L847-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 6515#L847-21 [4065] L847-21-->L847-23: Formula: (and (= v_~t4_st~0_22 0) (< v_ULTIMATE.start_activate_threads_~tmp___3~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47, ~t4_st~0=v_~t4_st~0_22} AuxVars[] AssignedVars[~t4_st~0] 6697#L847-23 [2983] L847-23-->L405-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_25|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 6661#L405-21 [2911] L405-21-->L406-7: Formula: (= v_~t5_pc~0_23 1) InVars {~t5_pc~0=v_~t5_pc~0_23} OutVars{~t5_pc~0=v_~t5_pc~0_23} AuxVars[] AssignedVars[] 6645#L406-7 [2874] L406-7-->L416-7: Formula: (and (= 1 v_~E_5~0_32) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_52 1)) InVars {~E_5~0=v_~E_5~0_32} OutVars{~E_5~0=v_~E_5~0_32, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_52} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 6647#L416-7 [4338] L416-7-->L855-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 6666#L855-21 [3251] L855-21-->L855-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} AuxVars[] AssignedVars[] 6775#L855-23 [3257] L855-23-->L424-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_25|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 6762#L424-21 [3173] L424-21-->L425-7: Formula: (= 1 v_~t6_pc~0_23) InVars {~t6_pc~0=v_~t6_pc~0_23} OutVars{~t6_pc~0=v_~t6_pc~0_23} AuxVars[] AssignedVars[] 6744#L425-7 [3114] L425-7-->L435-7: Formula: (and (= 1 v_~E_6~0_32) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_52 1)) InVars {~E_6~0=v_~E_6~0_32} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_52, ~E_6~0=v_~E_6~0_32} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 6388#L435-7 [4340] L435-7-->L863-21: Formula: (and (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___5~0_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_35|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_41|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 6389#L863-21 [4135] L863-21-->L863-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___5~0_47 0) (= v_~t6_st~0_22 0)) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} OutVars{~t6_st~0=v_~t6_st~0_22, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} AuxVars[] AssignedVars[~t6_st~0] 6431#L863-23 [4137] L863-23-->L733-3: Formula: (< v_~M_E~0_35 1) InVars {~M_E~0=v_~M_E~0_35} OutVars{~M_E~0=v_~M_E~0_35} AuxVars[] AssignedVars[] 6432#L733-3 [3184] L733-3-->L738-3: Formula: (and (= v_~T1_E~0_15 1) (= v_~T1_E~0_14 2)) InVars {~T1_E~0=v_~T1_E~0_15} OutVars{~T1_E~0=v_~T1_E~0_14} AuxVars[] AssignedVars[~T1_E~0] 6691#L738-3 [2971] L738-3-->L743-3: Formula: (and (= v_~T2_E~0_14 2) (= 1 v_~T2_E~0_15)) InVars {~T2_E~0=v_~T2_E~0_15} OutVars{~T2_E~0=v_~T2_E~0_14} AuxVars[] AssignedVars[~T2_E~0] 6411#L743-3 [4144] L743-3-->L748-3: Formula: (> 1 v_~T3_E~0_16) InVars {~T3_E~0=v_~T3_E~0_16} OutVars{~T3_E~0=v_~T3_E~0_16} AuxVars[] AssignedVars[] 6412#L748-3 [4145] L748-3-->L753-3: Formula: (> v_~T4_E~0_16 1) InVars {~T4_E~0=v_~T4_E~0_16} OutVars{~T4_E~0=v_~T4_E~0_16} AuxVars[] AssignedVars[] 6269#L753-3 [4147] L753-3-->L758-3: Formula: (> 1 v_~T5_E~0_16) InVars {~T5_E~0=v_~T5_E~0_16} OutVars{~T5_E~0=v_~T5_E~0_16} AuxVars[] AssignedVars[] 6270#L758-3 [4149] L758-3-->L763-3: Formula: (> v_~T6_E~0_16 1) InVars {~T6_E~0=v_~T6_E~0_16} OutVars{~T6_E~0=v_~T6_E~0_16} AuxVars[] AssignedVars[] 6360#L763-3 [4151] L763-3-->L768-3: Formula: (< 1 v_~E_1~0_36) InVars {~E_1~0=v_~E_1~0_36} OutVars{~E_1~0=v_~E_1~0_36} AuxVars[] AssignedVars[] 6361#L768-3 [3219] L768-3-->L773-3: Formula: (and (= 1 v_~E_2~0_35) (= v_~E_2~0_34 2)) InVars {~E_2~0=v_~E_2~0_35} OutVars{~E_2~0=v_~E_2~0_34} AuxVars[] AssignedVars[~E_2~0] 6586#L773-3 [2775] L773-3-->L778-3: Formula: (and (= 1 v_~E_3~0_35) (= v_~E_3~0_34 2)) InVars {~E_3~0=v_~E_3~0_35} OutVars{~E_3~0=v_~E_3~0_34} AuxVars[] AssignedVars[~E_3~0] 6587#L778-3 [3308] L778-3-->L783-3: Formula: (and (= 1 v_~E_4~0_35) (= v_~E_4~0_34 2)) InVars {~E_4~0=v_~E_4~0_35} OutVars{~E_4~0=v_~E_4~0_34} AuxVars[] AssignedVars[~E_4~0] 6482#L783-3 [4160] L783-3-->L788-3: Formula: (< 1 v_~E_5~0_36) InVars {~E_5~0=v_~E_5~0_36} OutVars{~E_5~0=v_~E_5~0_36} AuxVars[] AssignedVars[] 6483#L788-3 [4161] L788-3-->L793-3: Formula: (> 1 v_~E_6~0_36) InVars {~E_6~0=v_~E_6~0_36} OutVars{~E_6~0=v_~E_6~0_36} AuxVars[] AssignedVars[] 6689#L793-3 [2966] L793-3-->L494-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_30} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 6651#L494-1 [2878] L494-1-->L531-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33 1) (= 0 v_~m_st~0_21)) InVars {~m_st~0=v_~m_st~0_21} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33, ~m_st~0=v_~m_st~0_21} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 6348#L531-1 [4341] L531-1-->L1033: Formula: (and (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp~3] 6573#L1033 [4169] L1033-->L1033-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_6) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} AuxVars[] AssignedVars[] 6318#L1033-1 [2919] L1033-1-->L494-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_3|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_6, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_exists_runnable_thread_~__retres1~7, ULTIMATE.start_stop_simulation_#res] 6652#L494-2 [2882] L494-2-->L531-2: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9 1) (= v_~m_st~0_6 0)) InVars {~m_st~0=v_~m_st~0_6} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9, ~m_st~0=v_~m_st~0_6} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 6352#L531-2 [4343] L531-2-->L988: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 6578#L988 [3240] L988-->L995: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 6311#L995 [4354] L995-->L1014-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_6|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_#t~ret17, ULTIMATE.start_stop_simulation_#res] 6312#L1014-1 [2020-06-22 00:13:03,542 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:03,543 INFO L82 PathProgramCache]: Analyzing trace with hash -884156407, now seen corresponding path program 1 times [2020-06-22 00:13:03,543 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:03,543 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:03,544 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:03,544 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2020-06-22 00:13:03,544 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:03,549 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:03,566 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:03,567 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:03,567 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-06-22 00:13:03,567 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-06-22 00:13:03,567 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:03,567 INFO L82 PathProgramCache]: Analyzing trace with hash -356041806, now seen corresponding path program 1 times [2020-06-22 00:13:03,568 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:03,568 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:03,568 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:03,569 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:03,569 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:03,572 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:03,608 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:03,608 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:03,608 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2020-06-22 00:13:03,608 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-06-22 00:13:03,609 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-06-22 00:13:03,609 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-06-22 00:13:03,609 INFO L87 Difference]: Start difference. First operand 518 states and 1137 transitions. cyclomatic complexity: 620 Second operand 3 states. [2020-06-22 00:13:04,167 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-06-22 00:13:04,167 INFO L93 Difference]: Finished difference Result 518 states and 1136 transitions. [2020-06-22 00:13:04,167 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-06-22 00:13:04,168 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 518 states and 1136 transitions. [2020-06-22 00:13:04,171 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 442 [2020-06-22 00:13:04,175 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 518 states to 518 states and 1136 transitions. [2020-06-22 00:13:04,175 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 518 [2020-06-22 00:13:04,175 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 518 [2020-06-22 00:13:04,176 INFO L73 IsDeterministic]: Start isDeterministic. Operand 518 states and 1136 transitions. [2020-06-22 00:13:04,177 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-06-22 00:13:04,177 INFO L706 BuchiCegarLoop]: Abstraction has 518 states and 1136 transitions. [2020-06-22 00:13:04,178 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 518 states and 1136 transitions. [2020-06-22 00:13:04,185 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 518 to 518. [2020-06-22 00:13:04,186 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 518 states. [2020-06-22 00:13:04,187 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 518 states to 518 states and 1136 transitions. [2020-06-22 00:13:04,187 INFO L729 BuchiCegarLoop]: Abstraction has 518 states and 1136 transitions. [2020-06-22 00:13:04,187 INFO L609 BuchiCegarLoop]: Abstraction has 518 states and 1136 transitions. [2020-06-22 00:13:04,187 INFO L442 BuchiCegarLoop]: ======== Iteration 8============ [2020-06-22 00:13:04,188 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 518 states and 1136 transitions. [2020-06-22 00:13:04,190 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 442 [2020-06-22 00:13:04,190 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-06-22 00:13:04,190 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-06-22 00:13:04,192 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:04,192 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:04,193 INFO L794 eck$LassoCheckResult]: Stem: 7747#ULTIMATE.startENTRY [4266] ULTIMATE.startENTRY-->L444: Formula: (and (= 1 v_~t6_i~0_7) (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~M_E~0_37 2) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 0 v_~t6_pc~0_26) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_6~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= v_~T6_E~0_18 2) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~t6_st~0_24) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t6_pc~0=v_~t6_pc~0_26, ~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~T6_E~0=v_~T6_E~0_18, ~M_E~0=v_~M_E~0_37, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ~T4_E~0=v_~T4_E~0_18, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_4|, ~t6_i~0=v_~t6_i~0_7, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ULTIMATE.start_main_~__retres1~8=v_ULTIMATE.start_main_~__retres1~8_6, ~T2_E~0=v_~T2_E~0_18, ~t6_st~0=v_~t6_st~0_24, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_6~0=v_~E_6~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t6_pc~0, ~t5_i~0, ~t1_pc~0, ~t5_st~0, ~T6_E~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ~T4_E~0, ULTIMATE.start_start_simulation_#t~ret17, ~t6_i~0, ~t2_st~0, ~t2_pc~0, ULTIMATE.start_main_~__retres1~8, ~T2_E~0, ~t6_st~0, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_6~0, ULTIMATE.start_main_#res, ~E_2~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 7397#L444 [2453] L444-->L451-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 7398#L451-1 [3030] L451-1-->L456-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 7483#L456-1 [2574] L456-1-->L461-1: Formula: (and (= v_~t2_st~0_2 0) (= 1 v_~t2_i~0_3)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_2} AuxVars[] AssignedVars[~t2_st~0] 7484#L461-1 [2880] L461-1-->L466-1: Formula: (and (= v_~t3_st~0_3 0) (= v_~t3_i~0_3 1)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_3, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 7399#L466-1 [3645] L466-1-->L471-1: Formula: (and (= v_~t4_st~0_5 2) (> v_~t4_i~0_4 1)) InVars {~t4_i~0=v_~t4_i~0_4} OutVars{~t4_i~0=v_~t4_i~0_4, ~t4_st~0=v_~t4_st~0_5} AuxVars[] AssignedVars[~t4_st~0] 7400#L471-1 [3647] L471-1-->L476-1: Formula: (and (= v_~t5_st~0_5 2) (< v_~t5_i~0_4 1)) InVars {~t5_i~0=v_~t5_i~0_4} OutVars{~t5_i~0=v_~t5_i~0_4, ~t5_st~0=v_~t5_st~0_5} AuxVars[] AssignedVars[~t5_st~0] 7623#L476-1 [2761] L476-1-->L481-1: Formula: (and (= 1 v_~t6_i~0_3) (= v_~t6_st~0_4 0)) InVars {~t6_i~0=v_~t6_i~0_3} OutVars{~t6_st~0=v_~t6_st~0_4, ~t6_i~0=v_~t6_i~0_3} AuxVars[] AssignedVars[~t6_st~0] 7624#L481-1 [3652] L481-1-->L660-1: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 7758#L660-1 [3654] L660-1-->L665-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 7315#L665-1 [2383] L665-1-->L670-1: Formula: (and (= 0 v_~T2_E~0_3) (= v_~T2_E~0_2 1)) InVars {~T2_E~0=v_~T2_E~0_3} OutVars{~T2_E~0=v_~T2_E~0_2} AuxVars[] AssignedVars[~T2_E~0] 7316#L670-1 [2894] L670-1-->L675-1: Formula: (and (= v_~T3_E~0_2 1) (= v_~T3_E~0_3 0)) InVars {~T3_E~0=v_~T3_E~0_3} OutVars{~T3_E~0=v_~T3_E~0_2} AuxVars[] AssignedVars[~T3_E~0] 7406#L675-1 [3660] L675-1-->L680-1: Formula: (< v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 7407#L680-1 [3662] L680-1-->L685-1: Formula: (< v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 7632#L685-1 [3663] L685-1-->L690-1: Formula: (< 0 v_~T6_E~0_4) InVars {~T6_E~0=v_~T6_E~0_4} OutVars{~T6_E~0=v_~T6_E~0_4} AuxVars[] AssignedVars[] 7633#L690-1 [3310] L690-1-->L695-1: Formula: (and (= v_~E_1~0_5 0) (= v_~E_1~0_4 1)) InVars {~E_1~0=v_~E_1~0_5} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[~E_1~0] 7528#L695-1 [2621] L695-1-->L700-1: Formula: (and (= v_~E_2~0_4 1) (= v_~E_2~0_5 0)) InVars {~E_2~0=v_~E_2~0_5} OutVars{~E_2~0=v_~E_2~0_4} AuxVars[] AssignedVars[~E_2~0] 7529#L700-1 [3180] L700-1-->L705-1: Formula: (and (= v_~E_3~0_5 0) (= v_~E_3~0_4 1)) InVars {~E_3~0=v_~E_3~0_5} OutVars{~E_3~0=v_~E_3~0_4} AuxVars[] AssignedVars[~E_3~0] 7734#L705-1 [3672] L705-1-->L710-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 7467#L710-1 [2525] L710-1-->L715-1: Formula: (and (= v_~E_5~0_3 0) (= v_~E_5~0_2 1)) InVars {~E_5~0=v_~E_5~0_3} OutVars{~E_5~0=v_~E_5~0_2} AuxVars[] AssignedVars[~E_5~0] 7468#L715-1 [3676] L715-1-->L720-1: Formula: (< v_~E_6~0_4 0) InVars {~E_6~0=v_~E_6~0_4} OutVars{~E_6~0=v_~E_6~0_4} AuxVars[] AssignedVars[] 7351#L720-1 [2412] L720-1-->L310: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_7, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_4|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_4|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_7, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_4, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_4, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_2|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_2|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_4|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_4|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_7, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_2|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_4} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 7352#L310 [2597] L310-->L311: Formula: (= v_~m_pc~0_4 1) InVars {~m_pc~0=v_~m_pc~0_4} OutVars{~m_pc~0=v_~m_pc~0_4} AuxVars[] AssignedVars[] 7499#L311 [2732] L311-->L321: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_10 1) (= 1 v_~M_E~0_8)) InVars {~M_E~0=v_~M_E~0_8} OutVars{~M_E~0=v_~M_E~0_8, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_10} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 7494#L321 [4267] L321-->L815: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 7495#L815 [3682] L815-->L815-2: Formula: (and (= v_~m_st~0_5 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_11)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} OutVars{~m_st~0=v_~m_st~0_5, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} AuxVars[] AssignedVars[~m_st~0] 7730#L815-2 [2961] L815-2-->L329: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 7666#L329 [2848] L329-->L330: Formula: (= v_~t1_pc~0_4 1) InVars {~t1_pc~0=v_~t1_pc~0_4} OutVars{~t1_pc~0=v_~t1_pc~0_4} AuxVars[] AssignedVars[] 7667#L330 [3036] L330-->L340: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_10 1) (= v_~E_1~0_7 1)) InVars {~E_1~0=v_~E_1~0_7} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_10, ~E_1~0=v_~E_1~0_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 7661#L340 [4268] L340-->L823: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 7662#L823 [3688] L823-->L823-2: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___0~0_11 0) (= v_~t1_st~0_5 0)) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_11} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_11, ~t1_st~0=v_~t1_st~0_5} AuxVars[] AssignedVars[~t1_st~0] 7816#L823-2 [3235] L823-2-->L348: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_4|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 7800#L348 [3143] L348-->L349: Formula: (= v_~t2_pc~0_4 1) InVars {~t2_pc~0=v_~t2_pc~0_4} OutVars{~t2_pc~0=v_~t2_pc~0_4} AuxVars[] AssignedVars[] 7801#L349 [3267] L349-->L359: Formula: (and (= v_~E_2~0_7 1) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_10 1)) InVars {~E_2~0=v_~E_2~0_7} OutVars{~E_2~0=v_~E_2~0_7, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_10} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 7799#L359 [4269] L359-->L831: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 7474#L831 [3694] L831-->L831-2: Formula: (and (= v_~t2_st~0_5 0) (> v_ULTIMATE.start_activate_threads_~tmp___1~0_11 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_11} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_11, ~t2_st~0=v_~t2_st~0_5} AuxVars[] AssignedVars[~t2_st~0] 7462#L831-2 [2520] L831-2-->L367: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_4|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 7402#L367 [3695] L367-->L367-2: Formula: (> 1 v_~t3_pc~0_5) InVars {~t3_pc~0=v_~t3_pc~0_5} OutVars{~t3_pc~0=v_~t3_pc~0_5} AuxVars[] AssignedVars[] 7380#L367-2 [2438] L367-2-->L378: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 7381#L378 [4270] L378-->L839: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 7401#L839 [2791] L839-->L839-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} AuxVars[] AssignedVars[] 7639#L839-2 [2794] L839-2-->L386: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_7, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 7569#L386 [2675] L386-->L387: Formula: (= v_~t4_pc~0_4 1) InVars {~t4_pc~0=v_~t4_pc~0_4} OutVars{~t4_pc~0=v_~t4_pc~0_4} AuxVars[] AssignedVars[] 7488#L387 [2588] L387-->L397: Formula: (and (= v_~E_4~0_7 1) (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_10 1)) InVars {~E_4~0=v_~E_4~0_7} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_10, ~E_4~0=v_~E_4~0_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 7490#L397 [4271] L397-->L847: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 7568#L847 [3084] L847-->L847-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} AuxVars[] AssignedVars[] 7762#L847-2 [3064] L847-2-->L405: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_4|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 7763#L405 [3708] L405-->L405-2: Formula: (> 1 v_~t5_pc~0_5) InVars {~t5_pc~0=v_~t5_pc~0_5} OutVars{~t5_pc~0=v_~t5_pc~0_5} AuxVars[] AssignedVars[] 7699#L405-2 [2940] L405-2-->L416: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 7698#L416 [4272] L416-->L855: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 7769#L855 [3711] L855-->L855-2: Formula: (and (> v_ULTIMATE.start_activate_threads_~tmp___4~0_11 0) (= v_~t5_st~0_7 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_11} OutVars{~t5_st~0=v_~t5_st~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_11} AuxVars[] AssignedVars[~t5_st~0] 7770#L855-2 [3093] L855-2-->L424: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_4|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 7446#L424 [3714] L424-->L424-2: Formula: (> v_~t6_pc~0_5 1) InVars {~t6_pc~0=v_~t6_pc~0_5} OutVars{~t6_pc~0=v_~t6_pc~0_5} AuxVars[] AssignedVars[] 7447#L424-2 [2503] L424-2-->L435: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 7443#L435 [4273] L435-->L863: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___5~0_49 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_28|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_28|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 7367#L863 [2425] L863-->L863-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___5~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} AuxVars[] AssignedVars[] 7338#L863-2 [3720] L863-2-->L733-1: Formula: (< v_~M_E~0_15 1) InVars {~M_E~0=v_~M_E~0_15} OutVars{~M_E~0=v_~M_E~0_15} AuxVars[] AssignedVars[] 7339#L733-1 [3722] L733-1-->L738-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 7732#L738-1 [3724] L738-1-->L743-1: Formula: (> 1 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 7465#L743-1 [3726] L743-1-->L748-1: Formula: (< 1 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 7466#L748-1 [3727] L748-1-->L753-1: Formula: (< v_~T4_E~0_10 1) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 7346#L753-1 [2407] L753-1-->L758-1: Formula: (and (= v_~T5_E~0_8 2) (= v_~T5_E~0_9 1)) InVars {~T5_E~0=v_~T5_E~0_9} OutVars{~T5_E~0=v_~T5_E~0_8} AuxVars[] AssignedVars[~T5_E~0] 7347#L758-1 [3732] L758-1-->L763-1: Formula: (< v_~T6_E~0_10 1) InVars {~T6_E~0=v_~T6_E~0_10} OutVars{~T6_E~0=v_~T6_E~0_10} AuxVars[] AssignedVars[] 7418#L763-1 [2475] L763-1-->L768-1: Formula: (and (= v_~E_1~0_12 2) (= 1 v_~E_1~0_13)) InVars {~E_1~0=v_~E_1~0_13} OutVars{~E_1~0=v_~E_1~0_12} AuxVars[] AssignedVars[~E_1~0] 7419#L768-1 [3736] L768-1-->L773-1: Formula: (< 1 v_~E_2~0_14) InVars {~E_2~0=v_~E_2~0_14} OutVars{~E_2~0=v_~E_2~0_14} AuxVars[] AssignedVars[] 7627#L773-1 [2767] L773-1-->L778-1: Formula: (and (= 1 v_~E_3~0_13) (= v_~E_3~0_12 2)) InVars {~E_3~0=v_~E_3~0_13} OutVars{~E_3~0=v_~E_3~0_12} AuxVars[] AssignedVars[~E_3~0] 7628#L778-1 [3740] L778-1-->L783-1: Formula: (< 1 v_~E_4~0_14) InVars {~E_4~0=v_~E_4~0_14} OutVars{~E_4~0=v_~E_4~0_14} AuxVars[] AssignedVars[] 7519#L783-1 [3742] L783-1-->L788-1: Formula: (> 1 v_~E_5~0_14) InVars {~E_5~0=v_~E_5~0_14} OutVars{~E_5~0=v_~E_5~0_14} AuxVars[] AssignedVars[] 7520#L788-1 [3743] L788-1-->L1014-1: Formula: (> 1 v_~E_6~0_14) InVars {~E_6~0=v_~E_6~0_14} OutVars{~E_6~0=v_~E_6~0_14} AuxVars[] AssignedVars[] 7356#L1014-1 [2020-06-22 00:13:04,194 INFO L796 eck$LassoCheckResult]: Loop: 7356#L1014-1 [4274] L1014-1-->L635: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp_ndt_7~0=v_ULTIMATE.start_eval_~tmp_ndt_7~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp_ndt_7~0] 7321#L635 [4275] L635-->L494: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_37} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 7694#L494 [2876] L494-->L531: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21 1) (= v_~m_st~0_8 0)) InVars {~m_st~0=v_~m_st~0_8} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21, ~m_st~0=v_~m_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 7390#L531 [4276] L531-->L546: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 7616#L546 [4278] L546-->L660-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 7759#L660-2 [3747] L660-2-->L660-4: Formula: (> v_~M_E~0_30 0) InVars {~M_E~0=v_~M_E~0_30} OutVars{~M_E~0=v_~M_E~0_30} AuxVars[] AssignedVars[] 7760#L660-4 [3058] L660-4-->L665-3: Formula: (and (= v_~T1_E~0_11 1) (= v_~T1_E~0_12 0)) InVars {~T1_E~0=v_~T1_E~0_12} OutVars{~T1_E~0=v_~T1_E~0_11} AuxVars[] AssignedVars[~T1_E~0] 7333#L665-3 [2394] L665-3-->L670-3: Formula: (and (= 0 v_~T2_E~0_12) (= v_~T2_E~0_11 1)) InVars {~T2_E~0=v_~T2_E~0_12} OutVars{~T2_E~0=v_~T2_E~0_11} AuxVars[] AssignedVars[~T2_E~0] 7334#L670-3 [3761] L670-3-->L675-3: Formula: (> 0 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 7408#L675-3 [2467] L675-3-->L680-3: Formula: (and (= v_~T4_E~0_11 1) (= v_~T4_E~0_12 0)) InVars {~T4_E~0=v_~T4_E~0_12} OutVars{~T4_E~0=v_~T4_E~0_11} AuxVars[] AssignedVars[~T4_E~0] 7409#L680-3 [3776] L680-3-->L685-3: Formula: (< 0 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 7635#L685-3 [3785] L685-3-->L690-3: Formula: (> v_~T6_E~0_13 0) InVars {~T6_E~0=v_~T6_E~0_13} OutVars{~T6_E~0=v_~T6_E~0_13} AuxVars[] AssignedVars[] 7636#L690-3 [3795] L690-3-->L695-3: Formula: (< 0 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 7514#L695-3 [2609] L695-3-->L700-3: Formula: (and (= 0 v_~E_2~0_30) (= v_~E_2~0_29 1)) InVars {~E_2~0=v_~E_2~0_30} OutVars{~E_2~0=v_~E_2~0_29} AuxVars[] AssignedVars[~E_2~0] 7515#L700-3 [3155] L700-3-->L705-3: Formula: (and (= v_~E_3~0_29 1) (= 0 v_~E_3~0_30)) InVars {~E_3~0=v_~E_3~0_30} OutVars{~E_3~0=v_~E_3~0_29} AuxVars[] AssignedVars[~E_3~0] 7577#L705-3 [2688] L705-3-->L710-3: Formula: (and (= v_~E_4~0_29 1) (= 0 v_~E_4~0_30)) InVars {~E_4~0=v_~E_4~0_30} OutVars{~E_4~0=v_~E_4~0_29} AuxVars[] AssignedVars[~E_4~0] 7459#L710-3 [2515] L710-3-->L715-3: Formula: (and (= 0 v_~E_5~0_30) (= v_~E_5~0_29 1)) InVars {~E_5~0=v_~E_5~0_30} OutVars{~E_5~0=v_~E_5~0_29} AuxVars[] AssignedVars[~E_5~0] 7460#L715-3 [3048] L715-3-->L720-3: Formula: (and (= v_~E_6~0_29 1) (= 0 v_~E_6~0_30)) InVars {~E_6~0=v_~E_6~0_30} OutVars{~E_6~0=v_~E_6~0_29} AuxVars[] AssignedVars[~E_6~0] 7322#L720-3 [2388] L720-3-->L310-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_43, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_43, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_25|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_25|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_25|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_43, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_43, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_43, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_25|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_25|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_25|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_25|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_43, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_25|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_43, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_43} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 7323#L310-21 [2779] L310-21-->L311-7: Formula: (= v_~m_pc~0_23 1) InVars {~m_pc~0=v_~m_pc~0_23} OutVars{~m_pc~0=v_~m_pc~0_23} AuxVars[] AssignedVars[] 7600#L311-7 [2720] L311-7-->L321-7: Formula: (and (= v_~M_E~0_31 1) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_46 1)) InVars {~M_E~0=v_~M_E~0_31} OutVars{~M_E~0=v_~M_E~0_31, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_46} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 7601#L321-7 [4303] L321-7-->L815-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 7562#L815-21 [3897] L815-21-->L815-23: Formula: (and (> 0 v_ULTIMATE.start_activate_threads_~tmp~1_47) (= v_~m_st~0_20 0)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_47} OutVars{~m_st~0=v_~m_st~0_20, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_47} AuxVars[] AssignedVars[~m_st~0] 7543#L815-23 [2638] L815-23-->L329-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 7544#L329-21 [3038] L329-21-->L330-7: Formula: (= v_~t1_pc~0_23 1) InVars {~t1_pc~0=v_~t1_pc~0_23} OutVars{~t1_pc~0=v_~t1_pc~0_23} AuxVars[] AssignedVars[] 7739#L330-7 [2981] L330-7-->L340-7: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_52 1) (= 1 v_~E_1~0_32)) InVars {~E_1~0=v_~E_1~0_32} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_52, ~E_1~0=v_~E_1~0_32} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 7654#L340-7 [4310] L340-7-->L823-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 7655#L823-21 [2931] L823-21-->L823-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} AuxVars[] AssignedVars[] 7714#L823-23 [2934] L823-23-->L348-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_25|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 7716#L348-21 [3306] L348-21-->L349-7: Formula: (= 1 v_~t2_pc~0_23) InVars {~t2_pc~0=v_~t2_pc~0_23} OutVars{~t2_pc~0=v_~t2_pc~0_23} AuxVars[] AssignedVars[] 7820#L349-7 [3255] L349-7-->L359-7: Formula: (and (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_52 1) (= 1 v_~E_2~0_32)) InVars {~E_2~0=v_~E_2~0_32} OutVars{~E_2~0=v_~E_2~0_32, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_52} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 7796#L359-7 [4317] L359-7-->L831-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 7437#L831-21 [2490] L831-21-->L831-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} AuxVars[] AssignedVars[] 7438#L831-23 [3197] L831-23-->L367-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_25|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 7349#L367-21 [3995] L367-21-->L367-23: Formula: (> v_~t3_pc~0_24 1) InVars {~t3_pc~0=v_~t3_pc~0_24} OutVars{~t3_pc~0=v_~t3_pc~0_24} AuxVars[] AssignedVars[] 7317#L367-23 [2385] L367-23-->L378-7: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 7318#L378-7 [4324] L378-7-->L839-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 7372#L839-21 [4023] L839-21-->L839-23: Formula: (and (= v_~t3_st~0_21 0) (> v_ULTIMATE.start_activate_threads_~tmp___2~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} OutVars{~t3_st~0=v_~t3_st~0_21, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} AuxVars[] AssignedVars[~t3_st~0] 7596#L839-23 [2722] L839-23-->L386-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_49, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 7523#L386-21 [4037] L386-21-->L386-23: Formula: (< 1 v_~t4_pc~0_24) InVars {~t4_pc~0=v_~t4_pc~0_24} OutVars{~t4_pc~0=v_~t4_pc~0_24} AuxVars[] AssignedVars[] 7524#L386-23 [2623] L386-23-->L397-7: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 7530#L397-7 [4331] L397-7-->L847-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 7559#L847-21 [4065] L847-21-->L847-23: Formula: (and (= v_~t4_st~0_22 0) (< v_ULTIMATE.start_activate_threads_~tmp___3~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47, ~t4_st~0=v_~t4_st~0_22} AuxVars[] AssignedVars[~t4_st~0] 7741#L847-23 [2983] L847-23-->L405-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_25|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 7705#L405-21 [2911] L405-21-->L406-7: Formula: (= v_~t5_pc~0_23 1) InVars {~t5_pc~0=v_~t5_pc~0_23} OutVars{~t5_pc~0=v_~t5_pc~0_23} AuxVars[] AssignedVars[] 7689#L406-7 [2874] L406-7-->L416-7: Formula: (and (= 1 v_~E_5~0_32) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_52 1)) InVars {~E_5~0=v_~E_5~0_32} OutVars{~E_5~0=v_~E_5~0_32, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_52} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 7691#L416-7 [4338] L416-7-->L855-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 7710#L855-21 [3251] L855-21-->L855-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} AuxVars[] AssignedVars[] 7819#L855-23 [3257] L855-23-->L424-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_25|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 7806#L424-21 [3173] L424-21-->L425-7: Formula: (= 1 v_~t6_pc~0_23) InVars {~t6_pc~0=v_~t6_pc~0_23} OutVars{~t6_pc~0=v_~t6_pc~0_23} AuxVars[] AssignedVars[] 7788#L425-7 [3114] L425-7-->L435-7: Formula: (and (= 1 v_~E_6~0_32) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_52 1)) InVars {~E_6~0=v_~E_6~0_32} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_52, ~E_6~0=v_~E_6~0_32} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 7432#L435-7 [4340] L435-7-->L863-21: Formula: (and (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___5~0_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_35|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_41|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 7433#L863-21 [4135] L863-21-->L863-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___5~0_47 0) (= v_~t6_st~0_22 0)) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} OutVars{~t6_st~0=v_~t6_st~0_22, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} AuxVars[] AssignedVars[~t6_st~0] 7475#L863-23 [4137] L863-23-->L733-3: Formula: (< v_~M_E~0_35 1) InVars {~M_E~0=v_~M_E~0_35} OutVars{~M_E~0=v_~M_E~0_35} AuxVars[] AssignedVars[] 7476#L733-3 [3184] L733-3-->L738-3: Formula: (and (= v_~T1_E~0_15 1) (= v_~T1_E~0_14 2)) InVars {~T1_E~0=v_~T1_E~0_15} OutVars{~T1_E~0=v_~T1_E~0_14} AuxVars[] AssignedVars[~T1_E~0] 7735#L738-3 [2971] L738-3-->L743-3: Formula: (and (= v_~T2_E~0_14 2) (= 1 v_~T2_E~0_15)) InVars {~T2_E~0=v_~T2_E~0_15} OutVars{~T2_E~0=v_~T2_E~0_14} AuxVars[] AssignedVars[~T2_E~0] 7455#L743-3 [4144] L743-3-->L748-3: Formula: (> 1 v_~T3_E~0_16) InVars {~T3_E~0=v_~T3_E~0_16} OutVars{~T3_E~0=v_~T3_E~0_16} AuxVars[] AssignedVars[] 7456#L748-3 [4145] L748-3-->L753-3: Formula: (> v_~T4_E~0_16 1) InVars {~T4_E~0=v_~T4_E~0_16} OutVars{~T4_E~0=v_~T4_E~0_16} AuxVars[] AssignedVars[] 7313#L753-3 [4147] L753-3-->L758-3: Formula: (> 1 v_~T5_E~0_16) InVars {~T5_E~0=v_~T5_E~0_16} OutVars{~T5_E~0=v_~T5_E~0_16} AuxVars[] AssignedVars[] 7314#L758-3 [4149] L758-3-->L763-3: Formula: (> v_~T6_E~0_16 1) InVars {~T6_E~0=v_~T6_E~0_16} OutVars{~T6_E~0=v_~T6_E~0_16} AuxVars[] AssignedVars[] 7404#L763-3 [4151] L763-3-->L768-3: Formula: (< 1 v_~E_1~0_36) InVars {~E_1~0=v_~E_1~0_36} OutVars{~E_1~0=v_~E_1~0_36} AuxVars[] AssignedVars[] 7405#L768-3 [3219] L768-3-->L773-3: Formula: (and (= 1 v_~E_2~0_35) (= v_~E_2~0_34 2)) InVars {~E_2~0=v_~E_2~0_35} OutVars{~E_2~0=v_~E_2~0_34} AuxVars[] AssignedVars[~E_2~0] 7630#L773-3 [2775] L773-3-->L778-3: Formula: (and (= 1 v_~E_3~0_35) (= v_~E_3~0_34 2)) InVars {~E_3~0=v_~E_3~0_35} OutVars{~E_3~0=v_~E_3~0_34} AuxVars[] AssignedVars[~E_3~0] 7631#L778-3 [3308] L778-3-->L783-3: Formula: (and (= 1 v_~E_4~0_35) (= v_~E_4~0_34 2)) InVars {~E_4~0=v_~E_4~0_35} OutVars{~E_4~0=v_~E_4~0_34} AuxVars[] AssignedVars[~E_4~0] 7526#L783-3 [4160] L783-3-->L788-3: Formula: (< 1 v_~E_5~0_36) InVars {~E_5~0=v_~E_5~0_36} OutVars{~E_5~0=v_~E_5~0_36} AuxVars[] AssignedVars[] 7527#L788-3 [4161] L788-3-->L793-3: Formula: (> 1 v_~E_6~0_36) InVars {~E_6~0=v_~E_6~0_36} OutVars{~E_6~0=v_~E_6~0_36} AuxVars[] AssignedVars[] 7733#L793-3 [2966] L793-3-->L494-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_30} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 7695#L494-1 [2878] L494-1-->L531-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33 1) (= 0 v_~m_st~0_21)) InVars {~m_st~0=v_~m_st~0_21} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33, ~m_st~0=v_~m_st~0_21} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 7392#L531-1 [4341] L531-1-->L1033: Formula: (and (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp~3] 7617#L1033 [4169] L1033-->L1033-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_6) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} AuxVars[] AssignedVars[] 7362#L1033-1 [2919] L1033-1-->L494-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_3|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_6, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_exists_runnable_thread_~__retres1~7, ULTIMATE.start_stop_simulation_#res] 7696#L494-2 [2882] L494-2-->L531-2: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9 1) (= v_~m_st~0_6 0)) InVars {~m_st~0=v_~m_st~0_6} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9, ~m_st~0=v_~m_st~0_6} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 7396#L531-2 [4343] L531-2-->L988: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 7622#L988 [3240] L988-->L995: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 7355#L995 [4354] L995-->L1014-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_6|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_#t~ret17, ULTIMATE.start_stop_simulation_#res] 7356#L1014-1 [2020-06-22 00:13:04,195 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:04,195 INFO L82 PathProgramCache]: Analyzing trace with hash 1290523690, now seen corresponding path program 1 times [2020-06-22 00:13:04,195 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:04,195 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:04,196 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:04,196 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:04,196 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:04,201 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:04,216 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:04,216 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:04,217 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-06-22 00:13:04,217 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-06-22 00:13:04,217 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:04,217 INFO L82 PathProgramCache]: Analyzing trace with hash -356041806, now seen corresponding path program 2 times [2020-06-22 00:13:04,217 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:04,218 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:04,218 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:04,219 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:04,219 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:04,222 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:04,258 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:04,258 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:04,258 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2020-06-22 00:13:04,259 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-06-22 00:13:04,259 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-06-22 00:13:04,259 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-06-22 00:13:04,259 INFO L87 Difference]: Start difference. First operand 518 states and 1136 transitions. cyclomatic complexity: 619 Second operand 3 states. [2020-06-22 00:13:04,810 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-06-22 00:13:04,810 INFO L93 Difference]: Finished difference Result 518 states and 1135 transitions. [2020-06-22 00:13:04,810 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-06-22 00:13:04,811 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 518 states and 1135 transitions. [2020-06-22 00:13:04,814 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 442 [2020-06-22 00:13:04,817 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 518 states to 518 states and 1135 transitions. [2020-06-22 00:13:04,818 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 518 [2020-06-22 00:13:04,818 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 518 [2020-06-22 00:13:04,818 INFO L73 IsDeterministic]: Start isDeterministic. Operand 518 states and 1135 transitions. [2020-06-22 00:13:04,819 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-06-22 00:13:04,819 INFO L706 BuchiCegarLoop]: Abstraction has 518 states and 1135 transitions. [2020-06-22 00:13:04,820 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 518 states and 1135 transitions. [2020-06-22 00:13:04,827 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 518 to 518. [2020-06-22 00:13:04,827 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 518 states. [2020-06-22 00:13:04,829 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 518 states to 518 states and 1135 transitions. [2020-06-22 00:13:04,829 INFO L729 BuchiCegarLoop]: Abstraction has 518 states and 1135 transitions. [2020-06-22 00:13:04,829 INFO L609 BuchiCegarLoop]: Abstraction has 518 states and 1135 transitions. [2020-06-22 00:13:04,829 INFO L442 BuchiCegarLoop]: ======== Iteration 9============ [2020-06-22 00:13:04,829 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 518 states and 1135 transitions. [2020-06-22 00:13:04,832 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 442 [2020-06-22 00:13:04,832 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-06-22 00:13:04,832 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-06-22 00:13:04,833 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:04,833 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:04,834 INFO L794 eck$LassoCheckResult]: Stem: 8791#ULTIMATE.startENTRY [4266] ULTIMATE.startENTRY-->L444: Formula: (and (= 1 v_~t6_i~0_7) (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~M_E~0_37 2) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 0 v_~t6_pc~0_26) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_6~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= v_~T6_E~0_18 2) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~t6_st~0_24) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t6_pc~0=v_~t6_pc~0_26, ~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~T6_E~0=v_~T6_E~0_18, ~M_E~0=v_~M_E~0_37, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ~T4_E~0=v_~T4_E~0_18, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_4|, ~t6_i~0=v_~t6_i~0_7, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ULTIMATE.start_main_~__retres1~8=v_ULTIMATE.start_main_~__retres1~8_6, ~T2_E~0=v_~T2_E~0_18, ~t6_st~0=v_~t6_st~0_24, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_6~0=v_~E_6~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t6_pc~0, ~t5_i~0, ~t1_pc~0, ~t5_st~0, ~T6_E~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ~T4_E~0, ULTIMATE.start_start_simulation_#t~ret17, ~t6_i~0, ~t2_st~0, ~t2_pc~0, ULTIMATE.start_main_~__retres1~8, ~T2_E~0, ~t6_st~0, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_6~0, ULTIMATE.start_main_#res, ~E_2~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 8441#L444 [2453] L444-->L451-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 8442#L451-1 [3030] L451-1-->L456-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 8527#L456-1 [2574] L456-1-->L461-1: Formula: (and (= v_~t2_st~0_2 0) (= 1 v_~t2_i~0_3)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_2} AuxVars[] AssignedVars[~t2_st~0] 8528#L461-1 [2880] L461-1-->L466-1: Formula: (and (= v_~t3_st~0_3 0) (= v_~t3_i~0_3 1)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_3, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 8443#L466-1 [2457] L466-1-->L471-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 8444#L471-1 [3647] L471-1-->L476-1: Formula: (and (= v_~t5_st~0_5 2) (< v_~t5_i~0_4 1)) InVars {~t5_i~0=v_~t5_i~0_4} OutVars{~t5_i~0=v_~t5_i~0_4, ~t5_st~0=v_~t5_st~0_5} AuxVars[] AssignedVars[~t5_st~0] 8667#L476-1 [2761] L476-1-->L481-1: Formula: (and (= 1 v_~t6_i~0_3) (= v_~t6_st~0_4 0)) InVars {~t6_i~0=v_~t6_i~0_3} OutVars{~t6_st~0=v_~t6_st~0_4, ~t6_i~0=v_~t6_i~0_3} AuxVars[] AssignedVars[~t6_st~0] 8668#L481-1 [3652] L481-1-->L660-1: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 8802#L660-1 [3654] L660-1-->L665-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 8359#L665-1 [2383] L665-1-->L670-1: Formula: (and (= 0 v_~T2_E~0_3) (= v_~T2_E~0_2 1)) InVars {~T2_E~0=v_~T2_E~0_3} OutVars{~T2_E~0=v_~T2_E~0_2} AuxVars[] AssignedVars[~T2_E~0] 8360#L670-1 [2894] L670-1-->L675-1: Formula: (and (= v_~T3_E~0_2 1) (= v_~T3_E~0_3 0)) InVars {~T3_E~0=v_~T3_E~0_3} OutVars{~T3_E~0=v_~T3_E~0_2} AuxVars[] AssignedVars[~T3_E~0] 8450#L675-1 [3660] L675-1-->L680-1: Formula: (< v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 8451#L680-1 [3662] L680-1-->L685-1: Formula: (< v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 8676#L685-1 [3663] L685-1-->L690-1: Formula: (< 0 v_~T6_E~0_4) InVars {~T6_E~0=v_~T6_E~0_4} OutVars{~T6_E~0=v_~T6_E~0_4} AuxVars[] AssignedVars[] 8677#L690-1 [3310] L690-1-->L695-1: Formula: (and (= v_~E_1~0_5 0) (= v_~E_1~0_4 1)) InVars {~E_1~0=v_~E_1~0_5} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[~E_1~0] 8572#L695-1 [2621] L695-1-->L700-1: Formula: (and (= v_~E_2~0_4 1) (= v_~E_2~0_5 0)) InVars {~E_2~0=v_~E_2~0_5} OutVars{~E_2~0=v_~E_2~0_4} AuxVars[] AssignedVars[~E_2~0] 8573#L700-1 [3180] L700-1-->L705-1: Formula: (and (= v_~E_3~0_5 0) (= v_~E_3~0_4 1)) InVars {~E_3~0=v_~E_3~0_5} OutVars{~E_3~0=v_~E_3~0_4} AuxVars[] AssignedVars[~E_3~0] 8778#L705-1 [3672] L705-1-->L710-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 8511#L710-1 [2525] L710-1-->L715-1: Formula: (and (= v_~E_5~0_3 0) (= v_~E_5~0_2 1)) InVars {~E_5~0=v_~E_5~0_3} OutVars{~E_5~0=v_~E_5~0_2} AuxVars[] AssignedVars[~E_5~0] 8512#L715-1 [3676] L715-1-->L720-1: Formula: (< v_~E_6~0_4 0) InVars {~E_6~0=v_~E_6~0_4} OutVars{~E_6~0=v_~E_6~0_4} AuxVars[] AssignedVars[] 8395#L720-1 [2412] L720-1-->L310: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_7, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_4|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_4|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_7, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_4, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_4, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_2|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_2|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_4|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_4|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_7, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_2|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_4} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 8396#L310 [2597] L310-->L311: Formula: (= v_~m_pc~0_4 1) InVars {~m_pc~0=v_~m_pc~0_4} OutVars{~m_pc~0=v_~m_pc~0_4} AuxVars[] AssignedVars[] 8543#L311 [2732] L311-->L321: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_10 1) (= 1 v_~M_E~0_8)) InVars {~M_E~0=v_~M_E~0_8} OutVars{~M_E~0=v_~M_E~0_8, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_10} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 8538#L321 [4267] L321-->L815: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 8539#L815 [3682] L815-->L815-2: Formula: (and (= v_~m_st~0_5 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_11)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} OutVars{~m_st~0=v_~m_st~0_5, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} AuxVars[] AssignedVars[~m_st~0] 8774#L815-2 [2961] L815-2-->L329: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 8710#L329 [2848] L329-->L330: Formula: (= v_~t1_pc~0_4 1) InVars {~t1_pc~0=v_~t1_pc~0_4} OutVars{~t1_pc~0=v_~t1_pc~0_4} AuxVars[] AssignedVars[] 8711#L330 [3036] L330-->L340: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_10 1) (= v_~E_1~0_7 1)) InVars {~E_1~0=v_~E_1~0_7} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_10, ~E_1~0=v_~E_1~0_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 8705#L340 [4268] L340-->L823: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 8706#L823 [3688] L823-->L823-2: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___0~0_11 0) (= v_~t1_st~0_5 0)) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_11} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_11, ~t1_st~0=v_~t1_st~0_5} AuxVars[] AssignedVars[~t1_st~0] 8860#L823-2 [3235] L823-2-->L348: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_4|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 8844#L348 [3143] L348-->L349: Formula: (= v_~t2_pc~0_4 1) InVars {~t2_pc~0=v_~t2_pc~0_4} OutVars{~t2_pc~0=v_~t2_pc~0_4} AuxVars[] AssignedVars[] 8845#L349 [3267] L349-->L359: Formula: (and (= v_~E_2~0_7 1) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_10 1)) InVars {~E_2~0=v_~E_2~0_7} OutVars{~E_2~0=v_~E_2~0_7, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_10} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 8843#L359 [4269] L359-->L831: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 8518#L831 [3694] L831-->L831-2: Formula: (and (= v_~t2_st~0_5 0) (> v_ULTIMATE.start_activate_threads_~tmp___1~0_11 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_11} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_11, ~t2_st~0=v_~t2_st~0_5} AuxVars[] AssignedVars[~t2_st~0] 8506#L831-2 [2520] L831-2-->L367: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_4|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 8446#L367 [3695] L367-->L367-2: Formula: (> 1 v_~t3_pc~0_5) InVars {~t3_pc~0=v_~t3_pc~0_5} OutVars{~t3_pc~0=v_~t3_pc~0_5} AuxVars[] AssignedVars[] 8424#L367-2 [2438] L367-2-->L378: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 8425#L378 [4270] L378-->L839: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 8445#L839 [2791] L839-->L839-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} AuxVars[] AssignedVars[] 8683#L839-2 [2794] L839-2-->L386: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_7, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 8613#L386 [2675] L386-->L387: Formula: (= v_~t4_pc~0_4 1) InVars {~t4_pc~0=v_~t4_pc~0_4} OutVars{~t4_pc~0=v_~t4_pc~0_4} AuxVars[] AssignedVars[] 8532#L387 [2588] L387-->L397: Formula: (and (= v_~E_4~0_7 1) (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_10 1)) InVars {~E_4~0=v_~E_4~0_7} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_10, ~E_4~0=v_~E_4~0_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 8534#L397 [4271] L397-->L847: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 8612#L847 [3084] L847-->L847-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} AuxVars[] AssignedVars[] 8806#L847-2 [3064] L847-2-->L405: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_4|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 8807#L405 [3708] L405-->L405-2: Formula: (> 1 v_~t5_pc~0_5) InVars {~t5_pc~0=v_~t5_pc~0_5} OutVars{~t5_pc~0=v_~t5_pc~0_5} AuxVars[] AssignedVars[] 8743#L405-2 [2940] L405-2-->L416: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 8742#L416 [4272] L416-->L855: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 8813#L855 [3711] L855-->L855-2: Formula: (and (> v_ULTIMATE.start_activate_threads_~tmp___4~0_11 0) (= v_~t5_st~0_7 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_11} OutVars{~t5_st~0=v_~t5_st~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_11} AuxVars[] AssignedVars[~t5_st~0] 8814#L855-2 [3093] L855-2-->L424: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_4|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 8490#L424 [3714] L424-->L424-2: Formula: (> v_~t6_pc~0_5 1) InVars {~t6_pc~0=v_~t6_pc~0_5} OutVars{~t6_pc~0=v_~t6_pc~0_5} AuxVars[] AssignedVars[] 8491#L424-2 [2503] L424-2-->L435: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 8487#L435 [4273] L435-->L863: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___5~0_49 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_28|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_28|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 8411#L863 [2425] L863-->L863-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___5~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} AuxVars[] AssignedVars[] 8382#L863-2 [3720] L863-2-->L733-1: Formula: (< v_~M_E~0_15 1) InVars {~M_E~0=v_~M_E~0_15} OutVars{~M_E~0=v_~M_E~0_15} AuxVars[] AssignedVars[] 8383#L733-1 [3722] L733-1-->L738-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 8776#L738-1 [3724] L738-1-->L743-1: Formula: (> 1 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 8509#L743-1 [3726] L743-1-->L748-1: Formula: (< 1 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 8510#L748-1 [3727] L748-1-->L753-1: Formula: (< v_~T4_E~0_10 1) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 8390#L753-1 [2407] L753-1-->L758-1: Formula: (and (= v_~T5_E~0_8 2) (= v_~T5_E~0_9 1)) InVars {~T5_E~0=v_~T5_E~0_9} OutVars{~T5_E~0=v_~T5_E~0_8} AuxVars[] AssignedVars[~T5_E~0] 8391#L758-1 [3732] L758-1-->L763-1: Formula: (< v_~T6_E~0_10 1) InVars {~T6_E~0=v_~T6_E~0_10} OutVars{~T6_E~0=v_~T6_E~0_10} AuxVars[] AssignedVars[] 8462#L763-1 [2475] L763-1-->L768-1: Formula: (and (= v_~E_1~0_12 2) (= 1 v_~E_1~0_13)) InVars {~E_1~0=v_~E_1~0_13} OutVars{~E_1~0=v_~E_1~0_12} AuxVars[] AssignedVars[~E_1~0] 8463#L768-1 [3736] L768-1-->L773-1: Formula: (< 1 v_~E_2~0_14) InVars {~E_2~0=v_~E_2~0_14} OutVars{~E_2~0=v_~E_2~0_14} AuxVars[] AssignedVars[] 8671#L773-1 [2767] L773-1-->L778-1: Formula: (and (= 1 v_~E_3~0_13) (= v_~E_3~0_12 2)) InVars {~E_3~0=v_~E_3~0_13} OutVars{~E_3~0=v_~E_3~0_12} AuxVars[] AssignedVars[~E_3~0] 8672#L778-1 [3740] L778-1-->L783-1: Formula: (< 1 v_~E_4~0_14) InVars {~E_4~0=v_~E_4~0_14} OutVars{~E_4~0=v_~E_4~0_14} AuxVars[] AssignedVars[] 8563#L783-1 [3742] L783-1-->L788-1: Formula: (> 1 v_~E_5~0_14) InVars {~E_5~0=v_~E_5~0_14} OutVars{~E_5~0=v_~E_5~0_14} AuxVars[] AssignedVars[] 8564#L788-1 [3743] L788-1-->L1014-1: Formula: (> 1 v_~E_6~0_14) InVars {~E_6~0=v_~E_6~0_14} OutVars{~E_6~0=v_~E_6~0_14} AuxVars[] AssignedVars[] 8400#L1014-1 [2020-06-22 00:13:04,836 INFO L796 eck$LassoCheckResult]: Loop: 8400#L1014-1 [4274] L1014-1-->L635: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp_ndt_7~0=v_ULTIMATE.start_eval_~tmp_ndt_7~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp_ndt_7~0] 8365#L635 [4275] L635-->L494: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_37} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 8738#L494 [2876] L494-->L531: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21 1) (= v_~m_st~0_8 0)) InVars {~m_st~0=v_~m_st~0_8} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21, ~m_st~0=v_~m_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 8434#L531 [4276] L531-->L546: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 8660#L546 [4278] L546-->L660-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 8803#L660-2 [3747] L660-2-->L660-4: Formula: (> v_~M_E~0_30 0) InVars {~M_E~0=v_~M_E~0_30} OutVars{~M_E~0=v_~M_E~0_30} AuxVars[] AssignedVars[] 8804#L660-4 [3058] L660-4-->L665-3: Formula: (and (= v_~T1_E~0_11 1) (= v_~T1_E~0_12 0)) InVars {~T1_E~0=v_~T1_E~0_12} OutVars{~T1_E~0=v_~T1_E~0_11} AuxVars[] AssignedVars[~T1_E~0] 8377#L665-3 [2394] L665-3-->L670-3: Formula: (and (= 0 v_~T2_E~0_12) (= v_~T2_E~0_11 1)) InVars {~T2_E~0=v_~T2_E~0_12} OutVars{~T2_E~0=v_~T2_E~0_11} AuxVars[] AssignedVars[~T2_E~0] 8378#L670-3 [3761] L670-3-->L675-3: Formula: (> 0 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 8452#L675-3 [2467] L675-3-->L680-3: Formula: (and (= v_~T4_E~0_11 1) (= v_~T4_E~0_12 0)) InVars {~T4_E~0=v_~T4_E~0_12} OutVars{~T4_E~0=v_~T4_E~0_11} AuxVars[] AssignedVars[~T4_E~0] 8453#L680-3 [3776] L680-3-->L685-3: Formula: (< 0 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 8679#L685-3 [3785] L685-3-->L690-3: Formula: (> v_~T6_E~0_13 0) InVars {~T6_E~0=v_~T6_E~0_13} OutVars{~T6_E~0=v_~T6_E~0_13} AuxVars[] AssignedVars[] 8680#L690-3 [3795] L690-3-->L695-3: Formula: (< 0 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 8558#L695-3 [2609] L695-3-->L700-3: Formula: (and (= 0 v_~E_2~0_30) (= v_~E_2~0_29 1)) InVars {~E_2~0=v_~E_2~0_30} OutVars{~E_2~0=v_~E_2~0_29} AuxVars[] AssignedVars[~E_2~0] 8559#L700-3 [3155] L700-3-->L705-3: Formula: (and (= v_~E_3~0_29 1) (= 0 v_~E_3~0_30)) InVars {~E_3~0=v_~E_3~0_30} OutVars{~E_3~0=v_~E_3~0_29} AuxVars[] AssignedVars[~E_3~0] 8621#L705-3 [2688] L705-3-->L710-3: Formula: (and (= v_~E_4~0_29 1) (= 0 v_~E_4~0_30)) InVars {~E_4~0=v_~E_4~0_30} OutVars{~E_4~0=v_~E_4~0_29} AuxVars[] AssignedVars[~E_4~0] 8503#L710-3 [2515] L710-3-->L715-3: Formula: (and (= 0 v_~E_5~0_30) (= v_~E_5~0_29 1)) InVars {~E_5~0=v_~E_5~0_30} OutVars{~E_5~0=v_~E_5~0_29} AuxVars[] AssignedVars[~E_5~0] 8504#L715-3 [3048] L715-3-->L720-3: Formula: (and (= v_~E_6~0_29 1) (= 0 v_~E_6~0_30)) InVars {~E_6~0=v_~E_6~0_30} OutVars{~E_6~0=v_~E_6~0_29} AuxVars[] AssignedVars[~E_6~0] 8366#L720-3 [2388] L720-3-->L310-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_43, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_43, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_25|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_25|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_25|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_43, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_43, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_43, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_25|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_25|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_25|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_25|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_43, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_25|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_43, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_43} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 8367#L310-21 [2779] L310-21-->L311-7: Formula: (= v_~m_pc~0_23 1) InVars {~m_pc~0=v_~m_pc~0_23} OutVars{~m_pc~0=v_~m_pc~0_23} AuxVars[] AssignedVars[] 8644#L311-7 [2720] L311-7-->L321-7: Formula: (and (= v_~M_E~0_31 1) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_46 1)) InVars {~M_E~0=v_~M_E~0_31} OutVars{~M_E~0=v_~M_E~0_31, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_46} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 8645#L321-7 [4303] L321-7-->L815-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 8606#L815-21 [3897] L815-21-->L815-23: Formula: (and (> 0 v_ULTIMATE.start_activate_threads_~tmp~1_47) (= v_~m_st~0_20 0)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_47} OutVars{~m_st~0=v_~m_st~0_20, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_47} AuxVars[] AssignedVars[~m_st~0] 8587#L815-23 [2638] L815-23-->L329-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 8588#L329-21 [3911] L329-21-->L329-23: Formula: (< v_~t1_pc~0_24 1) InVars {~t1_pc~0=v_~t1_pc~0_24} OutVars{~t1_pc~0=v_~t1_pc~0_24} AuxVars[] AssignedVars[] 8784#L329-23 [3052] L329-23-->L340-7: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 8698#L340-7 [4310] L340-7-->L823-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 8699#L823-21 [2931] L823-21-->L823-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} AuxVars[] AssignedVars[] 8758#L823-23 [2934] L823-23-->L348-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_25|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 8760#L348-21 [3306] L348-21-->L349-7: Formula: (= 1 v_~t2_pc~0_23) InVars {~t2_pc~0=v_~t2_pc~0_23} OutVars{~t2_pc~0=v_~t2_pc~0_23} AuxVars[] AssignedVars[] 8864#L349-7 [3255] L349-7-->L359-7: Formula: (and (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_52 1) (= 1 v_~E_2~0_32)) InVars {~E_2~0=v_~E_2~0_32} OutVars{~E_2~0=v_~E_2~0_32, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_52} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 8840#L359-7 [4317] L359-7-->L831-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 8481#L831-21 [2490] L831-21-->L831-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} AuxVars[] AssignedVars[] 8482#L831-23 [3197] L831-23-->L367-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_25|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 8393#L367-21 [3995] L367-21-->L367-23: Formula: (> v_~t3_pc~0_24 1) InVars {~t3_pc~0=v_~t3_pc~0_24} OutVars{~t3_pc~0=v_~t3_pc~0_24} AuxVars[] AssignedVars[] 8361#L367-23 [2385] L367-23-->L378-7: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 8362#L378-7 [4324] L378-7-->L839-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 8416#L839-21 [4023] L839-21-->L839-23: Formula: (and (= v_~t3_st~0_21 0) (> v_ULTIMATE.start_activate_threads_~tmp___2~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} OutVars{~t3_st~0=v_~t3_st~0_21, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} AuxVars[] AssignedVars[~t3_st~0] 8640#L839-23 [2722] L839-23-->L386-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_49, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 8567#L386-21 [4037] L386-21-->L386-23: Formula: (< 1 v_~t4_pc~0_24) InVars {~t4_pc~0=v_~t4_pc~0_24} OutVars{~t4_pc~0=v_~t4_pc~0_24} AuxVars[] AssignedVars[] 8568#L386-23 [2623] L386-23-->L397-7: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 8574#L397-7 [4331] L397-7-->L847-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 8603#L847-21 [4065] L847-21-->L847-23: Formula: (and (= v_~t4_st~0_22 0) (< v_ULTIMATE.start_activate_threads_~tmp___3~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47, ~t4_st~0=v_~t4_st~0_22} AuxVars[] AssignedVars[~t4_st~0] 8785#L847-23 [2983] L847-23-->L405-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_25|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 8749#L405-21 [2911] L405-21-->L406-7: Formula: (= v_~t5_pc~0_23 1) InVars {~t5_pc~0=v_~t5_pc~0_23} OutVars{~t5_pc~0=v_~t5_pc~0_23} AuxVars[] AssignedVars[] 8733#L406-7 [2874] L406-7-->L416-7: Formula: (and (= 1 v_~E_5~0_32) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_52 1)) InVars {~E_5~0=v_~E_5~0_32} OutVars{~E_5~0=v_~E_5~0_32, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_52} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 8735#L416-7 [4338] L416-7-->L855-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 8754#L855-21 [3251] L855-21-->L855-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} AuxVars[] AssignedVars[] 8863#L855-23 [3257] L855-23-->L424-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_25|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 8850#L424-21 [3173] L424-21-->L425-7: Formula: (= 1 v_~t6_pc~0_23) InVars {~t6_pc~0=v_~t6_pc~0_23} OutVars{~t6_pc~0=v_~t6_pc~0_23} AuxVars[] AssignedVars[] 8832#L425-7 [3114] L425-7-->L435-7: Formula: (and (= 1 v_~E_6~0_32) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_52 1)) InVars {~E_6~0=v_~E_6~0_32} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_52, ~E_6~0=v_~E_6~0_32} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 8476#L435-7 [4340] L435-7-->L863-21: Formula: (and (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___5~0_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_35|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_41|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 8477#L863-21 [4135] L863-21-->L863-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___5~0_47 0) (= v_~t6_st~0_22 0)) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} OutVars{~t6_st~0=v_~t6_st~0_22, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} AuxVars[] AssignedVars[~t6_st~0] 8519#L863-23 [4137] L863-23-->L733-3: Formula: (< v_~M_E~0_35 1) InVars {~M_E~0=v_~M_E~0_35} OutVars{~M_E~0=v_~M_E~0_35} AuxVars[] AssignedVars[] 8520#L733-3 [3184] L733-3-->L738-3: Formula: (and (= v_~T1_E~0_15 1) (= v_~T1_E~0_14 2)) InVars {~T1_E~0=v_~T1_E~0_15} OutVars{~T1_E~0=v_~T1_E~0_14} AuxVars[] AssignedVars[~T1_E~0] 8779#L738-3 [2971] L738-3-->L743-3: Formula: (and (= v_~T2_E~0_14 2) (= 1 v_~T2_E~0_15)) InVars {~T2_E~0=v_~T2_E~0_15} OutVars{~T2_E~0=v_~T2_E~0_14} AuxVars[] AssignedVars[~T2_E~0] 8499#L743-3 [4144] L743-3-->L748-3: Formula: (> 1 v_~T3_E~0_16) InVars {~T3_E~0=v_~T3_E~0_16} OutVars{~T3_E~0=v_~T3_E~0_16} AuxVars[] AssignedVars[] 8500#L748-3 [4145] L748-3-->L753-3: Formula: (> v_~T4_E~0_16 1) InVars {~T4_E~0=v_~T4_E~0_16} OutVars{~T4_E~0=v_~T4_E~0_16} AuxVars[] AssignedVars[] 8357#L753-3 [4147] L753-3-->L758-3: Formula: (> 1 v_~T5_E~0_16) InVars {~T5_E~0=v_~T5_E~0_16} OutVars{~T5_E~0=v_~T5_E~0_16} AuxVars[] AssignedVars[] 8358#L758-3 [4149] L758-3-->L763-3: Formula: (> v_~T6_E~0_16 1) InVars {~T6_E~0=v_~T6_E~0_16} OutVars{~T6_E~0=v_~T6_E~0_16} AuxVars[] AssignedVars[] 8448#L763-3 [4151] L763-3-->L768-3: Formula: (< 1 v_~E_1~0_36) InVars {~E_1~0=v_~E_1~0_36} OutVars{~E_1~0=v_~E_1~0_36} AuxVars[] AssignedVars[] 8449#L768-3 [3219] L768-3-->L773-3: Formula: (and (= 1 v_~E_2~0_35) (= v_~E_2~0_34 2)) InVars {~E_2~0=v_~E_2~0_35} OutVars{~E_2~0=v_~E_2~0_34} AuxVars[] AssignedVars[~E_2~0] 8674#L773-3 [2775] L773-3-->L778-3: Formula: (and (= 1 v_~E_3~0_35) (= v_~E_3~0_34 2)) InVars {~E_3~0=v_~E_3~0_35} OutVars{~E_3~0=v_~E_3~0_34} AuxVars[] AssignedVars[~E_3~0] 8675#L778-3 [3308] L778-3-->L783-3: Formula: (and (= 1 v_~E_4~0_35) (= v_~E_4~0_34 2)) InVars {~E_4~0=v_~E_4~0_35} OutVars{~E_4~0=v_~E_4~0_34} AuxVars[] AssignedVars[~E_4~0] 8570#L783-3 [4160] L783-3-->L788-3: Formula: (< 1 v_~E_5~0_36) InVars {~E_5~0=v_~E_5~0_36} OutVars{~E_5~0=v_~E_5~0_36} AuxVars[] AssignedVars[] 8571#L788-3 [4161] L788-3-->L793-3: Formula: (> 1 v_~E_6~0_36) InVars {~E_6~0=v_~E_6~0_36} OutVars{~E_6~0=v_~E_6~0_36} AuxVars[] AssignedVars[] 8777#L793-3 [2966] L793-3-->L494-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_30} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 8739#L494-1 [2878] L494-1-->L531-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33 1) (= 0 v_~m_st~0_21)) InVars {~m_st~0=v_~m_st~0_21} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33, ~m_st~0=v_~m_st~0_21} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 8436#L531-1 [4341] L531-1-->L1033: Formula: (and (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp~3] 8661#L1033 [4169] L1033-->L1033-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_6) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} AuxVars[] AssignedVars[] 8406#L1033-1 [2919] L1033-1-->L494-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_3|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_6, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_exists_runnable_thread_~__retres1~7, ULTIMATE.start_stop_simulation_#res] 8740#L494-2 [2882] L494-2-->L531-2: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9 1) (= v_~m_st~0_6 0)) InVars {~m_st~0=v_~m_st~0_6} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9, ~m_st~0=v_~m_st~0_6} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 8440#L531-2 [4343] L531-2-->L988: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 8666#L988 [3240] L988-->L995: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 8399#L995 [4354] L995-->L1014-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_6|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_#t~ret17, ULTIMATE.start_stop_simulation_#res] 8400#L1014-1 [2020-06-22 00:13:04,836 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:04,836 INFO L82 PathProgramCache]: Analyzing trace with hash -759833266, now seen corresponding path program 1 times [2020-06-22 00:13:04,836 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:04,837 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:04,837 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:04,837 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2020-06-22 00:13:04,838 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:04,843 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:04,867 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:04,867 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:04,868 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-06-22 00:13:04,868 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-06-22 00:13:04,868 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:04,868 INFO L82 PathProgramCache]: Analyzing trace with hash 1178387828, now seen corresponding path program 1 times [2020-06-22 00:13:04,868 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:04,868 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:04,869 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:04,869 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:04,870 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:04,873 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:04,896 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:04,896 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:04,896 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2020-06-22 00:13:04,897 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-06-22 00:13:04,897 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-06-22 00:13:04,897 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-06-22 00:13:04,897 INFO L87 Difference]: Start difference. First operand 518 states and 1135 transitions. cyclomatic complexity: 618 Second operand 3 states. [2020-06-22 00:13:05,494 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-06-22 00:13:05,494 INFO L93 Difference]: Finished difference Result 518 states and 1134 transitions. [2020-06-22 00:13:05,495 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-06-22 00:13:05,495 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 518 states and 1134 transitions. [2020-06-22 00:13:05,498 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 442 [2020-06-22 00:13:05,502 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 518 states to 518 states and 1134 transitions. [2020-06-22 00:13:05,502 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 518 [2020-06-22 00:13:05,502 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 518 [2020-06-22 00:13:05,502 INFO L73 IsDeterministic]: Start isDeterministic. Operand 518 states and 1134 transitions. [2020-06-22 00:13:05,503 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-06-22 00:13:05,503 INFO L706 BuchiCegarLoop]: Abstraction has 518 states and 1134 transitions. [2020-06-22 00:13:05,504 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 518 states and 1134 transitions. [2020-06-22 00:13:05,510 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 518 to 518. [2020-06-22 00:13:05,510 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 518 states. [2020-06-22 00:13:05,511 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 518 states to 518 states and 1134 transitions. [2020-06-22 00:13:05,511 INFO L729 BuchiCegarLoop]: Abstraction has 518 states and 1134 transitions. [2020-06-22 00:13:05,512 INFO L609 BuchiCegarLoop]: Abstraction has 518 states and 1134 transitions. [2020-06-22 00:13:05,512 INFO L442 BuchiCegarLoop]: ======== Iteration 10============ [2020-06-22 00:13:05,512 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 518 states and 1134 transitions. [2020-06-22 00:13:05,514 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 442 [2020-06-22 00:13:05,514 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-06-22 00:13:05,514 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-06-22 00:13:05,515 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:05,517 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:05,518 INFO L794 eck$LassoCheckResult]: Stem: 9835#ULTIMATE.startENTRY [4266] ULTIMATE.startENTRY-->L444: Formula: (and (= 1 v_~t6_i~0_7) (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~M_E~0_37 2) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 0 v_~t6_pc~0_26) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_6~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= v_~T6_E~0_18 2) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~t6_st~0_24) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t6_pc~0=v_~t6_pc~0_26, ~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~T6_E~0=v_~T6_E~0_18, ~M_E~0=v_~M_E~0_37, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ~T4_E~0=v_~T4_E~0_18, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_4|, ~t6_i~0=v_~t6_i~0_7, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ULTIMATE.start_main_~__retres1~8=v_ULTIMATE.start_main_~__retres1~8_6, ~T2_E~0=v_~T2_E~0_18, ~t6_st~0=v_~t6_st~0_24, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_6~0=v_~E_6~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t6_pc~0, ~t5_i~0, ~t1_pc~0, ~t5_st~0, ~T6_E~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ~T4_E~0, ULTIMATE.start_start_simulation_#t~ret17, ~t6_i~0, ~t2_st~0, ~t2_pc~0, ULTIMATE.start_main_~__retres1~8, ~T2_E~0, ~t6_st~0, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_6~0, ULTIMATE.start_main_#res, ~E_2~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 9485#L444 [2453] L444-->L451-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 9486#L451-1 [3030] L451-1-->L456-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 9571#L456-1 [2574] L456-1-->L461-1: Formula: (and (= v_~t2_st~0_2 0) (= 1 v_~t2_i~0_3)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_2} AuxVars[] AssignedVars[~t2_st~0] 9572#L461-1 [2880] L461-1-->L466-1: Formula: (and (= v_~t3_st~0_3 0) (= v_~t3_i~0_3 1)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_3, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 9487#L466-1 [2457] L466-1-->L471-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 9488#L471-1 [3209] L471-1-->L476-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 9711#L476-1 [2761] L476-1-->L481-1: Formula: (and (= 1 v_~t6_i~0_3) (= v_~t6_st~0_4 0)) InVars {~t6_i~0=v_~t6_i~0_3} OutVars{~t6_st~0=v_~t6_st~0_4, ~t6_i~0=v_~t6_i~0_3} AuxVars[] AssignedVars[~t6_st~0] 9712#L481-1 [3652] L481-1-->L660-1: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 9846#L660-1 [3654] L660-1-->L665-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 9403#L665-1 [2383] L665-1-->L670-1: Formula: (and (= 0 v_~T2_E~0_3) (= v_~T2_E~0_2 1)) InVars {~T2_E~0=v_~T2_E~0_3} OutVars{~T2_E~0=v_~T2_E~0_2} AuxVars[] AssignedVars[~T2_E~0] 9404#L670-1 [2894] L670-1-->L675-1: Formula: (and (= v_~T3_E~0_2 1) (= v_~T3_E~0_3 0)) InVars {~T3_E~0=v_~T3_E~0_3} OutVars{~T3_E~0=v_~T3_E~0_2} AuxVars[] AssignedVars[~T3_E~0] 9494#L675-1 [3660] L675-1-->L680-1: Formula: (< v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 9495#L680-1 [3662] L680-1-->L685-1: Formula: (< v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 9720#L685-1 [3663] L685-1-->L690-1: Formula: (< 0 v_~T6_E~0_4) InVars {~T6_E~0=v_~T6_E~0_4} OutVars{~T6_E~0=v_~T6_E~0_4} AuxVars[] AssignedVars[] 9721#L690-1 [3310] L690-1-->L695-1: Formula: (and (= v_~E_1~0_5 0) (= v_~E_1~0_4 1)) InVars {~E_1~0=v_~E_1~0_5} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[~E_1~0] 9616#L695-1 [2621] L695-1-->L700-1: Formula: (and (= v_~E_2~0_4 1) (= v_~E_2~0_5 0)) InVars {~E_2~0=v_~E_2~0_5} OutVars{~E_2~0=v_~E_2~0_4} AuxVars[] AssignedVars[~E_2~0] 9617#L700-1 [3180] L700-1-->L705-1: Formula: (and (= v_~E_3~0_5 0) (= v_~E_3~0_4 1)) InVars {~E_3~0=v_~E_3~0_5} OutVars{~E_3~0=v_~E_3~0_4} AuxVars[] AssignedVars[~E_3~0] 9822#L705-1 [3672] L705-1-->L710-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 9555#L710-1 [2525] L710-1-->L715-1: Formula: (and (= v_~E_5~0_3 0) (= v_~E_5~0_2 1)) InVars {~E_5~0=v_~E_5~0_3} OutVars{~E_5~0=v_~E_5~0_2} AuxVars[] AssignedVars[~E_5~0] 9556#L715-1 [3676] L715-1-->L720-1: Formula: (< v_~E_6~0_4 0) InVars {~E_6~0=v_~E_6~0_4} OutVars{~E_6~0=v_~E_6~0_4} AuxVars[] AssignedVars[] 9439#L720-1 [2412] L720-1-->L310: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_7, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_4|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_4|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_7, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_4, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_4, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_2|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_2|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_4|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_4|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_7, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_2|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_4} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 9440#L310 [2597] L310-->L311: Formula: (= v_~m_pc~0_4 1) InVars {~m_pc~0=v_~m_pc~0_4} OutVars{~m_pc~0=v_~m_pc~0_4} AuxVars[] AssignedVars[] 9587#L311 [2732] L311-->L321: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_10 1) (= 1 v_~M_E~0_8)) InVars {~M_E~0=v_~M_E~0_8} OutVars{~M_E~0=v_~M_E~0_8, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_10} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 9582#L321 [4267] L321-->L815: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 9583#L815 [3682] L815-->L815-2: Formula: (and (= v_~m_st~0_5 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_11)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} OutVars{~m_st~0=v_~m_st~0_5, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} AuxVars[] AssignedVars[~m_st~0] 9818#L815-2 [2961] L815-2-->L329: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 9754#L329 [2848] L329-->L330: Formula: (= v_~t1_pc~0_4 1) InVars {~t1_pc~0=v_~t1_pc~0_4} OutVars{~t1_pc~0=v_~t1_pc~0_4} AuxVars[] AssignedVars[] 9755#L330 [3036] L330-->L340: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_10 1) (= v_~E_1~0_7 1)) InVars {~E_1~0=v_~E_1~0_7} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_10, ~E_1~0=v_~E_1~0_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 9752#L340 [4268] L340-->L823: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 9753#L823 [3688] L823-->L823-2: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___0~0_11 0) (= v_~t1_st~0_5 0)) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_11} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_11, ~t1_st~0=v_~t1_st~0_5} AuxVars[] AssignedVars[~t1_st~0] 9904#L823-2 [3235] L823-2-->L348: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_4|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 9888#L348 [3143] L348-->L349: Formula: (= v_~t2_pc~0_4 1) InVars {~t2_pc~0=v_~t2_pc~0_4} OutVars{~t2_pc~0=v_~t2_pc~0_4} AuxVars[] AssignedVars[] 9889#L349 [3267] L349-->L359: Formula: (and (= v_~E_2~0_7 1) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_10 1)) InVars {~E_2~0=v_~E_2~0_7} OutVars{~E_2~0=v_~E_2~0_7, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_10} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 9887#L359 [4269] L359-->L831: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 9562#L831 [3694] L831-->L831-2: Formula: (and (= v_~t2_st~0_5 0) (> v_ULTIMATE.start_activate_threads_~tmp___1~0_11 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_11} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_11, ~t2_st~0=v_~t2_st~0_5} AuxVars[] AssignedVars[~t2_st~0] 9550#L831-2 [2520] L831-2-->L367: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_4|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 9490#L367 [3695] L367-->L367-2: Formula: (> 1 v_~t3_pc~0_5) InVars {~t3_pc~0=v_~t3_pc~0_5} OutVars{~t3_pc~0=v_~t3_pc~0_5} AuxVars[] AssignedVars[] 9468#L367-2 [2438] L367-2-->L378: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 9469#L378 [4270] L378-->L839: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 9489#L839 [2791] L839-->L839-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} AuxVars[] AssignedVars[] 9727#L839-2 [2794] L839-2-->L386: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_7, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 9657#L386 [2675] L386-->L387: Formula: (= v_~t4_pc~0_4 1) InVars {~t4_pc~0=v_~t4_pc~0_4} OutVars{~t4_pc~0=v_~t4_pc~0_4} AuxVars[] AssignedVars[] 9576#L387 [2588] L387-->L397: Formula: (and (= v_~E_4~0_7 1) (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_10 1)) InVars {~E_4~0=v_~E_4~0_7} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_10, ~E_4~0=v_~E_4~0_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 9578#L397 [4271] L397-->L847: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 9656#L847 [3084] L847-->L847-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} AuxVars[] AssignedVars[] 9850#L847-2 [3064] L847-2-->L405: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_4|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 9851#L405 [3708] L405-->L405-2: Formula: (> 1 v_~t5_pc~0_5) InVars {~t5_pc~0=v_~t5_pc~0_5} OutVars{~t5_pc~0=v_~t5_pc~0_5} AuxVars[] AssignedVars[] 9787#L405-2 [2940] L405-2-->L416: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 9786#L416 [4272] L416-->L855: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 9857#L855 [3711] L855-->L855-2: Formula: (and (> v_ULTIMATE.start_activate_threads_~tmp___4~0_11 0) (= v_~t5_st~0_7 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_11} OutVars{~t5_st~0=v_~t5_st~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_11} AuxVars[] AssignedVars[~t5_st~0] 9858#L855-2 [3093] L855-2-->L424: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_4|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 9534#L424 [3714] L424-->L424-2: Formula: (> v_~t6_pc~0_5 1) InVars {~t6_pc~0=v_~t6_pc~0_5} OutVars{~t6_pc~0=v_~t6_pc~0_5} AuxVars[] AssignedVars[] 9535#L424-2 [2503] L424-2-->L435: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 9531#L435 [4273] L435-->L863: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___5~0_49 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_28|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_28|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 9455#L863 [2425] L863-->L863-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___5~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} AuxVars[] AssignedVars[] 9426#L863-2 [3720] L863-2-->L733-1: Formula: (< v_~M_E~0_15 1) InVars {~M_E~0=v_~M_E~0_15} OutVars{~M_E~0=v_~M_E~0_15} AuxVars[] AssignedVars[] 9427#L733-1 [3722] L733-1-->L738-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 9820#L738-1 [3724] L738-1-->L743-1: Formula: (> 1 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 9553#L743-1 [3726] L743-1-->L748-1: Formula: (< 1 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 9554#L748-1 [3727] L748-1-->L753-1: Formula: (< v_~T4_E~0_10 1) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 9434#L753-1 [2407] L753-1-->L758-1: Formula: (and (= v_~T5_E~0_8 2) (= v_~T5_E~0_9 1)) InVars {~T5_E~0=v_~T5_E~0_9} OutVars{~T5_E~0=v_~T5_E~0_8} AuxVars[] AssignedVars[~T5_E~0] 9435#L758-1 [3732] L758-1-->L763-1: Formula: (< v_~T6_E~0_10 1) InVars {~T6_E~0=v_~T6_E~0_10} OutVars{~T6_E~0=v_~T6_E~0_10} AuxVars[] AssignedVars[] 9506#L763-1 [2475] L763-1-->L768-1: Formula: (and (= v_~E_1~0_12 2) (= 1 v_~E_1~0_13)) InVars {~E_1~0=v_~E_1~0_13} OutVars{~E_1~0=v_~E_1~0_12} AuxVars[] AssignedVars[~E_1~0] 9507#L768-1 [3736] L768-1-->L773-1: Formula: (< 1 v_~E_2~0_14) InVars {~E_2~0=v_~E_2~0_14} OutVars{~E_2~0=v_~E_2~0_14} AuxVars[] AssignedVars[] 9715#L773-1 [2767] L773-1-->L778-1: Formula: (and (= 1 v_~E_3~0_13) (= v_~E_3~0_12 2)) InVars {~E_3~0=v_~E_3~0_13} OutVars{~E_3~0=v_~E_3~0_12} AuxVars[] AssignedVars[~E_3~0] 9716#L778-1 [3740] L778-1-->L783-1: Formula: (< 1 v_~E_4~0_14) InVars {~E_4~0=v_~E_4~0_14} OutVars{~E_4~0=v_~E_4~0_14} AuxVars[] AssignedVars[] 9607#L783-1 [3742] L783-1-->L788-1: Formula: (> 1 v_~E_5~0_14) InVars {~E_5~0=v_~E_5~0_14} OutVars{~E_5~0=v_~E_5~0_14} AuxVars[] AssignedVars[] 9608#L788-1 [3743] L788-1-->L1014-1: Formula: (> 1 v_~E_6~0_14) InVars {~E_6~0=v_~E_6~0_14} OutVars{~E_6~0=v_~E_6~0_14} AuxVars[] AssignedVars[] 9444#L1014-1 [2020-06-22 00:13:05,519 INFO L796 eck$LassoCheckResult]: Loop: 9444#L1014-1 [4274] L1014-1-->L635: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp_ndt_7~0=v_ULTIMATE.start_eval_~tmp_ndt_7~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp_ndt_7~0] 9409#L635 [4275] L635-->L494: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_37} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 9782#L494 [2876] L494-->L531: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21 1) (= v_~m_st~0_8 0)) InVars {~m_st~0=v_~m_st~0_8} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21, ~m_st~0=v_~m_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 9478#L531 [4276] L531-->L546: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 9704#L546 [4278] L546-->L660-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 9847#L660-2 [3747] L660-2-->L660-4: Formula: (> v_~M_E~0_30 0) InVars {~M_E~0=v_~M_E~0_30} OutVars{~M_E~0=v_~M_E~0_30} AuxVars[] AssignedVars[] 9848#L660-4 [3058] L660-4-->L665-3: Formula: (and (= v_~T1_E~0_11 1) (= v_~T1_E~0_12 0)) InVars {~T1_E~0=v_~T1_E~0_12} OutVars{~T1_E~0=v_~T1_E~0_11} AuxVars[] AssignedVars[~T1_E~0] 9421#L665-3 [2394] L665-3-->L670-3: Formula: (and (= 0 v_~T2_E~0_12) (= v_~T2_E~0_11 1)) InVars {~T2_E~0=v_~T2_E~0_12} OutVars{~T2_E~0=v_~T2_E~0_11} AuxVars[] AssignedVars[~T2_E~0] 9422#L670-3 [3761] L670-3-->L675-3: Formula: (> 0 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 9496#L675-3 [2467] L675-3-->L680-3: Formula: (and (= v_~T4_E~0_11 1) (= v_~T4_E~0_12 0)) InVars {~T4_E~0=v_~T4_E~0_12} OutVars{~T4_E~0=v_~T4_E~0_11} AuxVars[] AssignedVars[~T4_E~0] 9497#L680-3 [3776] L680-3-->L685-3: Formula: (< 0 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 9723#L685-3 [3785] L685-3-->L690-3: Formula: (> v_~T6_E~0_13 0) InVars {~T6_E~0=v_~T6_E~0_13} OutVars{~T6_E~0=v_~T6_E~0_13} AuxVars[] AssignedVars[] 9724#L690-3 [3795] L690-3-->L695-3: Formula: (< 0 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 9602#L695-3 [2609] L695-3-->L700-3: Formula: (and (= 0 v_~E_2~0_30) (= v_~E_2~0_29 1)) InVars {~E_2~0=v_~E_2~0_30} OutVars{~E_2~0=v_~E_2~0_29} AuxVars[] AssignedVars[~E_2~0] 9603#L700-3 [3155] L700-3-->L705-3: Formula: (and (= v_~E_3~0_29 1) (= 0 v_~E_3~0_30)) InVars {~E_3~0=v_~E_3~0_30} OutVars{~E_3~0=v_~E_3~0_29} AuxVars[] AssignedVars[~E_3~0] 9665#L705-3 [2688] L705-3-->L710-3: Formula: (and (= v_~E_4~0_29 1) (= 0 v_~E_4~0_30)) InVars {~E_4~0=v_~E_4~0_30} OutVars{~E_4~0=v_~E_4~0_29} AuxVars[] AssignedVars[~E_4~0] 9547#L710-3 [2515] L710-3-->L715-3: Formula: (and (= 0 v_~E_5~0_30) (= v_~E_5~0_29 1)) InVars {~E_5~0=v_~E_5~0_30} OutVars{~E_5~0=v_~E_5~0_29} AuxVars[] AssignedVars[~E_5~0] 9548#L715-3 [3048] L715-3-->L720-3: Formula: (and (= v_~E_6~0_29 1) (= 0 v_~E_6~0_30)) InVars {~E_6~0=v_~E_6~0_30} OutVars{~E_6~0=v_~E_6~0_29} AuxVars[] AssignedVars[~E_6~0] 9410#L720-3 [2388] L720-3-->L310-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_43, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_43, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_25|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_25|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_25|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_43, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_43, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_43, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_25|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_25|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_25|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_25|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_43, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_25|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_43, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_43} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 9411#L310-21 [2779] L310-21-->L311-7: Formula: (= v_~m_pc~0_23 1) InVars {~m_pc~0=v_~m_pc~0_23} OutVars{~m_pc~0=v_~m_pc~0_23} AuxVars[] AssignedVars[] 9688#L311-7 [2720] L311-7-->L321-7: Formula: (and (= v_~M_E~0_31 1) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_46 1)) InVars {~M_E~0=v_~M_E~0_31} OutVars{~M_E~0=v_~M_E~0_31, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_46} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 9689#L321-7 [4303] L321-7-->L815-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 9650#L815-21 [3897] L815-21-->L815-23: Formula: (and (> 0 v_ULTIMATE.start_activate_threads_~tmp~1_47) (= v_~m_st~0_20 0)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_47} OutVars{~m_st~0=v_~m_st~0_20, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_47} AuxVars[] AssignedVars[~m_st~0] 9631#L815-23 [2638] L815-23-->L329-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 9632#L329-21 [3038] L329-21-->L330-7: Formula: (= v_~t1_pc~0_23 1) InVars {~t1_pc~0=v_~t1_pc~0_23} OutVars{~t1_pc~0=v_~t1_pc~0_23} AuxVars[] AssignedVars[] 9827#L330-7 [2981] L330-7-->L340-7: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_52 1) (= 1 v_~E_1~0_32)) InVars {~E_1~0=v_~E_1~0_32} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_52, ~E_1~0=v_~E_1~0_32} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 9742#L340-7 [4310] L340-7-->L823-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 9743#L823-21 [2931] L823-21-->L823-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} AuxVars[] AssignedVars[] 9802#L823-23 [2934] L823-23-->L348-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_25|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 9804#L348-21 [3306] L348-21-->L349-7: Formula: (= 1 v_~t2_pc~0_23) InVars {~t2_pc~0=v_~t2_pc~0_23} OutVars{~t2_pc~0=v_~t2_pc~0_23} AuxVars[] AssignedVars[] 9908#L349-7 [3255] L349-7-->L359-7: Formula: (and (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_52 1) (= 1 v_~E_2~0_32)) InVars {~E_2~0=v_~E_2~0_32} OutVars{~E_2~0=v_~E_2~0_32, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_52} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 9884#L359-7 [4317] L359-7-->L831-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 9525#L831-21 [2490] L831-21-->L831-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} AuxVars[] AssignedVars[] 9526#L831-23 [3197] L831-23-->L367-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_25|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 9437#L367-21 [3995] L367-21-->L367-23: Formula: (> v_~t3_pc~0_24 1) InVars {~t3_pc~0=v_~t3_pc~0_24} OutVars{~t3_pc~0=v_~t3_pc~0_24} AuxVars[] AssignedVars[] 9405#L367-23 [2385] L367-23-->L378-7: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 9406#L378-7 [4324] L378-7-->L839-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 9460#L839-21 [4023] L839-21-->L839-23: Formula: (and (= v_~t3_st~0_21 0) (> v_ULTIMATE.start_activate_threads_~tmp___2~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} OutVars{~t3_st~0=v_~t3_st~0_21, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} AuxVars[] AssignedVars[~t3_st~0] 9681#L839-23 [2722] L839-23-->L386-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_49, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 9611#L386-21 [4037] L386-21-->L386-23: Formula: (< 1 v_~t4_pc~0_24) InVars {~t4_pc~0=v_~t4_pc~0_24} OutVars{~t4_pc~0=v_~t4_pc~0_24} AuxVars[] AssignedVars[] 9612#L386-23 [2623] L386-23-->L397-7: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 9618#L397-7 [4331] L397-7-->L847-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 9647#L847-21 [4065] L847-21-->L847-23: Formula: (and (= v_~t4_st~0_22 0) (< v_ULTIMATE.start_activate_threads_~tmp___3~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47, ~t4_st~0=v_~t4_st~0_22} AuxVars[] AssignedVars[~t4_st~0] 9829#L847-23 [2983] L847-23-->L405-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_25|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 9793#L405-21 [2911] L405-21-->L406-7: Formula: (= v_~t5_pc~0_23 1) InVars {~t5_pc~0=v_~t5_pc~0_23} OutVars{~t5_pc~0=v_~t5_pc~0_23} AuxVars[] AssignedVars[] 9777#L406-7 [2874] L406-7-->L416-7: Formula: (and (= 1 v_~E_5~0_32) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_52 1)) InVars {~E_5~0=v_~E_5~0_32} OutVars{~E_5~0=v_~E_5~0_32, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_52} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 9779#L416-7 [4338] L416-7-->L855-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 9798#L855-21 [3251] L855-21-->L855-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} AuxVars[] AssignedVars[] 9907#L855-23 [3257] L855-23-->L424-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_25|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 9894#L424-21 [3173] L424-21-->L425-7: Formula: (= 1 v_~t6_pc~0_23) InVars {~t6_pc~0=v_~t6_pc~0_23} OutVars{~t6_pc~0=v_~t6_pc~0_23} AuxVars[] AssignedVars[] 9876#L425-7 [3114] L425-7-->L435-7: Formula: (and (= 1 v_~E_6~0_32) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_52 1)) InVars {~E_6~0=v_~E_6~0_32} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_52, ~E_6~0=v_~E_6~0_32} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 9520#L435-7 [4340] L435-7-->L863-21: Formula: (and (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___5~0_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_35|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_41|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 9521#L863-21 [4135] L863-21-->L863-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___5~0_47 0) (= v_~t6_st~0_22 0)) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} OutVars{~t6_st~0=v_~t6_st~0_22, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} AuxVars[] AssignedVars[~t6_st~0] 9563#L863-23 [4137] L863-23-->L733-3: Formula: (< v_~M_E~0_35 1) InVars {~M_E~0=v_~M_E~0_35} OutVars{~M_E~0=v_~M_E~0_35} AuxVars[] AssignedVars[] 9564#L733-3 [3184] L733-3-->L738-3: Formula: (and (= v_~T1_E~0_15 1) (= v_~T1_E~0_14 2)) InVars {~T1_E~0=v_~T1_E~0_15} OutVars{~T1_E~0=v_~T1_E~0_14} AuxVars[] AssignedVars[~T1_E~0] 9823#L738-3 [2971] L738-3-->L743-3: Formula: (and (= v_~T2_E~0_14 2) (= 1 v_~T2_E~0_15)) InVars {~T2_E~0=v_~T2_E~0_15} OutVars{~T2_E~0=v_~T2_E~0_14} AuxVars[] AssignedVars[~T2_E~0] 9543#L743-3 [4144] L743-3-->L748-3: Formula: (> 1 v_~T3_E~0_16) InVars {~T3_E~0=v_~T3_E~0_16} OutVars{~T3_E~0=v_~T3_E~0_16} AuxVars[] AssignedVars[] 9544#L748-3 [4145] L748-3-->L753-3: Formula: (> v_~T4_E~0_16 1) InVars {~T4_E~0=v_~T4_E~0_16} OutVars{~T4_E~0=v_~T4_E~0_16} AuxVars[] AssignedVars[] 9401#L753-3 [4147] L753-3-->L758-3: Formula: (> 1 v_~T5_E~0_16) InVars {~T5_E~0=v_~T5_E~0_16} OutVars{~T5_E~0=v_~T5_E~0_16} AuxVars[] AssignedVars[] 9402#L758-3 [4149] L758-3-->L763-3: Formula: (> v_~T6_E~0_16 1) InVars {~T6_E~0=v_~T6_E~0_16} OutVars{~T6_E~0=v_~T6_E~0_16} AuxVars[] AssignedVars[] 9492#L763-3 [4151] L763-3-->L768-3: Formula: (< 1 v_~E_1~0_36) InVars {~E_1~0=v_~E_1~0_36} OutVars{~E_1~0=v_~E_1~0_36} AuxVars[] AssignedVars[] 9493#L768-3 [3219] L768-3-->L773-3: Formula: (and (= 1 v_~E_2~0_35) (= v_~E_2~0_34 2)) InVars {~E_2~0=v_~E_2~0_35} OutVars{~E_2~0=v_~E_2~0_34} AuxVars[] AssignedVars[~E_2~0] 9718#L773-3 [2775] L773-3-->L778-3: Formula: (and (= 1 v_~E_3~0_35) (= v_~E_3~0_34 2)) InVars {~E_3~0=v_~E_3~0_35} OutVars{~E_3~0=v_~E_3~0_34} AuxVars[] AssignedVars[~E_3~0] 9719#L778-3 [3308] L778-3-->L783-3: Formula: (and (= 1 v_~E_4~0_35) (= v_~E_4~0_34 2)) InVars {~E_4~0=v_~E_4~0_35} OutVars{~E_4~0=v_~E_4~0_34} AuxVars[] AssignedVars[~E_4~0] 9614#L783-3 [4160] L783-3-->L788-3: Formula: (< 1 v_~E_5~0_36) InVars {~E_5~0=v_~E_5~0_36} OutVars{~E_5~0=v_~E_5~0_36} AuxVars[] AssignedVars[] 9615#L788-3 [4161] L788-3-->L793-3: Formula: (> 1 v_~E_6~0_36) InVars {~E_6~0=v_~E_6~0_36} OutVars{~E_6~0=v_~E_6~0_36} AuxVars[] AssignedVars[] 9821#L793-3 [2966] L793-3-->L494-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_30} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 9783#L494-1 [2878] L494-1-->L531-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33 1) (= 0 v_~m_st~0_21)) InVars {~m_st~0=v_~m_st~0_21} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33, ~m_st~0=v_~m_st~0_21} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 9480#L531-1 [4341] L531-1-->L1033: Formula: (and (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp~3] 9705#L1033 [4169] L1033-->L1033-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_6) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} AuxVars[] AssignedVars[] 9450#L1033-1 [2919] L1033-1-->L494-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_3|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_6, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_exists_runnable_thread_~__retres1~7, ULTIMATE.start_stop_simulation_#res] 9784#L494-2 [2882] L494-2-->L531-2: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9 1) (= v_~m_st~0_6 0)) InVars {~m_st~0=v_~m_st~0_6} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9, ~m_st~0=v_~m_st~0_6} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 9484#L531-2 [4343] L531-2-->L988: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 9710#L988 [3240] L988-->L995: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 9443#L995 [4354] L995-->L1014-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_6|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_#t~ret17, ULTIMATE.start_stop_simulation_#res] 9444#L1014-1 [2020-06-22 00:13:05,519 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:05,520 INFO L82 PathProgramCache]: Analyzing trace with hash 455710232, now seen corresponding path program 1 times [2020-06-22 00:13:05,520 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:05,520 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:05,521 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:05,521 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:05,521 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:05,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:05,542 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:05,542 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:05,542 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-06-22 00:13:05,542 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-06-22 00:13:05,543 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:05,543 INFO L82 PathProgramCache]: Analyzing trace with hash -356041806, now seen corresponding path program 3 times [2020-06-22 00:13:05,543 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:05,543 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:05,544 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:05,544 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:05,544 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:05,547 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:05,570 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:05,571 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:05,571 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2020-06-22 00:13:05,571 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-06-22 00:13:05,571 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-06-22 00:13:05,572 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-06-22 00:13:05,572 INFO L87 Difference]: Start difference. First operand 518 states and 1134 transitions. cyclomatic complexity: 617 Second operand 3 states. [2020-06-22 00:13:06,219 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-06-22 00:13:06,219 INFO L93 Difference]: Finished difference Result 518 states and 1124 transitions. [2020-06-22 00:13:06,220 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-06-22 00:13:06,220 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 518 states and 1124 transitions. [2020-06-22 00:13:06,223 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 442 [2020-06-22 00:13:06,226 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 518 states to 518 states and 1124 transitions. [2020-06-22 00:13:06,227 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 518 [2020-06-22 00:13:06,227 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 518 [2020-06-22 00:13:06,227 INFO L73 IsDeterministic]: Start isDeterministic. Operand 518 states and 1124 transitions. [2020-06-22 00:13:06,228 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-06-22 00:13:06,228 INFO L706 BuchiCegarLoop]: Abstraction has 518 states and 1124 transitions. [2020-06-22 00:13:06,229 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 518 states and 1124 transitions. [2020-06-22 00:13:06,234 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 518 to 518. [2020-06-22 00:13:06,235 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 518 states. [2020-06-22 00:13:06,236 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 518 states to 518 states and 1124 transitions. [2020-06-22 00:13:06,236 INFO L729 BuchiCegarLoop]: Abstraction has 518 states and 1124 transitions. [2020-06-22 00:13:06,236 INFO L609 BuchiCegarLoop]: Abstraction has 518 states and 1124 transitions. [2020-06-22 00:13:06,236 INFO L442 BuchiCegarLoop]: ======== Iteration 11============ [2020-06-22 00:13:06,236 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 518 states and 1124 transitions. [2020-06-22 00:13:06,239 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 442 [2020-06-22 00:13:06,239 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-06-22 00:13:06,239 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-06-22 00:13:06,240 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:06,240 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:06,241 INFO L794 eck$LassoCheckResult]: Stem: 10879#ULTIMATE.startENTRY [4266] ULTIMATE.startENTRY-->L444: Formula: (and (= 1 v_~t6_i~0_7) (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~M_E~0_37 2) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 0 v_~t6_pc~0_26) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_6~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= v_~T6_E~0_18 2) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~t6_st~0_24) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t6_pc~0=v_~t6_pc~0_26, ~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~T6_E~0=v_~T6_E~0_18, ~M_E~0=v_~M_E~0_37, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ~T4_E~0=v_~T4_E~0_18, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_4|, ~t6_i~0=v_~t6_i~0_7, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ULTIMATE.start_main_~__retres1~8=v_ULTIMATE.start_main_~__retres1~8_6, ~T2_E~0=v_~T2_E~0_18, ~t6_st~0=v_~t6_st~0_24, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_6~0=v_~E_6~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t6_pc~0, ~t5_i~0, ~t1_pc~0, ~t5_st~0, ~T6_E~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ~T4_E~0, ULTIMATE.start_start_simulation_#t~ret17, ~t6_i~0, ~t2_st~0, ~t2_pc~0, ULTIMATE.start_main_~__retres1~8, ~T2_E~0, ~t6_st~0, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_6~0, ULTIMATE.start_main_#res, ~E_2~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 10529#L444 [2453] L444-->L451-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 10530#L451-1 [3030] L451-1-->L456-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 10615#L456-1 [2574] L456-1-->L461-1: Formula: (and (= v_~t2_st~0_2 0) (= 1 v_~t2_i~0_3)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_2} AuxVars[] AssignedVars[~t2_st~0] 10616#L461-1 [2880] L461-1-->L466-1: Formula: (and (= v_~t3_st~0_3 0) (= v_~t3_i~0_3 1)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_3, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 10531#L466-1 [2457] L466-1-->L471-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 10532#L471-1 [3209] L471-1-->L476-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 10755#L476-1 [2761] L476-1-->L481-1: Formula: (and (= 1 v_~t6_i~0_3) (= v_~t6_st~0_4 0)) InVars {~t6_i~0=v_~t6_i~0_3} OutVars{~t6_st~0=v_~t6_st~0_4, ~t6_i~0=v_~t6_i~0_3} AuxVars[] AssignedVars[~t6_st~0] 10756#L481-1 [3652] L481-1-->L660-1: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 10890#L660-1 [3654] L660-1-->L665-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 10449#L665-1 [3655] L665-1-->L670-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 10450#L670-1 [2894] L670-1-->L675-1: Formula: (and (= v_~T3_E~0_2 1) (= v_~T3_E~0_3 0)) InVars {~T3_E~0=v_~T3_E~0_3} OutVars{~T3_E~0=v_~T3_E~0_2} AuxVars[] AssignedVars[~T3_E~0] 10538#L675-1 [3660] L675-1-->L680-1: Formula: (< v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 10539#L680-1 [3662] L680-1-->L685-1: Formula: (< v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 10764#L685-1 [3663] L685-1-->L690-1: Formula: (< 0 v_~T6_E~0_4) InVars {~T6_E~0=v_~T6_E~0_4} OutVars{~T6_E~0=v_~T6_E~0_4} AuxVars[] AssignedVars[] 10765#L690-1 [3310] L690-1-->L695-1: Formula: (and (= v_~E_1~0_5 0) (= v_~E_1~0_4 1)) InVars {~E_1~0=v_~E_1~0_5} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[~E_1~0] 10660#L695-1 [2621] L695-1-->L700-1: Formula: (and (= v_~E_2~0_4 1) (= v_~E_2~0_5 0)) InVars {~E_2~0=v_~E_2~0_5} OutVars{~E_2~0=v_~E_2~0_4} AuxVars[] AssignedVars[~E_2~0] 10661#L700-1 [3180] L700-1-->L705-1: Formula: (and (= v_~E_3~0_5 0) (= v_~E_3~0_4 1)) InVars {~E_3~0=v_~E_3~0_5} OutVars{~E_3~0=v_~E_3~0_4} AuxVars[] AssignedVars[~E_3~0] 10866#L705-1 [3672] L705-1-->L710-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 10599#L710-1 [2525] L710-1-->L715-1: Formula: (and (= v_~E_5~0_3 0) (= v_~E_5~0_2 1)) InVars {~E_5~0=v_~E_5~0_3} OutVars{~E_5~0=v_~E_5~0_2} AuxVars[] AssignedVars[~E_5~0] 10600#L715-1 [3676] L715-1-->L720-1: Formula: (< v_~E_6~0_4 0) InVars {~E_6~0=v_~E_6~0_4} OutVars{~E_6~0=v_~E_6~0_4} AuxVars[] AssignedVars[] 10483#L720-1 [2412] L720-1-->L310: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_7, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_4|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_4|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_7, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_4, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_4, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_2|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_2|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_4|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_4|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_7, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_2|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_4} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 10484#L310 [2597] L310-->L311: Formula: (= v_~m_pc~0_4 1) InVars {~m_pc~0=v_~m_pc~0_4} OutVars{~m_pc~0=v_~m_pc~0_4} AuxVars[] AssignedVars[] 10631#L311 [2732] L311-->L321: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_10 1) (= 1 v_~M_E~0_8)) InVars {~M_E~0=v_~M_E~0_8} OutVars{~M_E~0=v_~M_E~0_8, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_10} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 10626#L321 [4267] L321-->L815: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 10627#L815 [3682] L815-->L815-2: Formula: (and (= v_~m_st~0_5 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_11)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} OutVars{~m_st~0=v_~m_st~0_5, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} AuxVars[] AssignedVars[~m_st~0] 10862#L815-2 [2961] L815-2-->L329: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 10798#L329 [2848] L329-->L330: Formula: (= v_~t1_pc~0_4 1) InVars {~t1_pc~0=v_~t1_pc~0_4} OutVars{~t1_pc~0=v_~t1_pc~0_4} AuxVars[] AssignedVars[] 10799#L330 [3036] L330-->L340: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_10 1) (= v_~E_1~0_7 1)) InVars {~E_1~0=v_~E_1~0_7} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_10, ~E_1~0=v_~E_1~0_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 10796#L340 [4268] L340-->L823: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 10797#L823 [3688] L823-->L823-2: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___0~0_11 0) (= v_~t1_st~0_5 0)) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_11} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_11, ~t1_st~0=v_~t1_st~0_5} AuxVars[] AssignedVars[~t1_st~0] 10948#L823-2 [3235] L823-2-->L348: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_4|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 10932#L348 [3143] L348-->L349: Formula: (= v_~t2_pc~0_4 1) InVars {~t2_pc~0=v_~t2_pc~0_4} OutVars{~t2_pc~0=v_~t2_pc~0_4} AuxVars[] AssignedVars[] 10933#L349 [3267] L349-->L359: Formula: (and (= v_~E_2~0_7 1) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_10 1)) InVars {~E_2~0=v_~E_2~0_7} OutVars{~E_2~0=v_~E_2~0_7, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_10} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 10931#L359 [4269] L359-->L831: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 10606#L831 [3694] L831-->L831-2: Formula: (and (= v_~t2_st~0_5 0) (> v_ULTIMATE.start_activate_threads_~tmp___1~0_11 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_11} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_11, ~t2_st~0=v_~t2_st~0_5} AuxVars[] AssignedVars[~t2_st~0] 10594#L831-2 [2520] L831-2-->L367: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_4|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 10534#L367 [3695] L367-->L367-2: Formula: (> 1 v_~t3_pc~0_5) InVars {~t3_pc~0=v_~t3_pc~0_5} OutVars{~t3_pc~0=v_~t3_pc~0_5} AuxVars[] AssignedVars[] 10512#L367-2 [2438] L367-2-->L378: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 10513#L378 [4270] L378-->L839: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 10533#L839 [2791] L839-->L839-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} AuxVars[] AssignedVars[] 10771#L839-2 [2794] L839-2-->L386: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_7, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 10701#L386 [2675] L386-->L387: Formula: (= v_~t4_pc~0_4 1) InVars {~t4_pc~0=v_~t4_pc~0_4} OutVars{~t4_pc~0=v_~t4_pc~0_4} AuxVars[] AssignedVars[] 10620#L387 [2588] L387-->L397: Formula: (and (= v_~E_4~0_7 1) (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_10 1)) InVars {~E_4~0=v_~E_4~0_7} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_10, ~E_4~0=v_~E_4~0_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 10622#L397 [4271] L397-->L847: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 10700#L847 [3084] L847-->L847-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} AuxVars[] AssignedVars[] 10894#L847-2 [3064] L847-2-->L405: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_4|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 10895#L405 [3708] L405-->L405-2: Formula: (> 1 v_~t5_pc~0_5) InVars {~t5_pc~0=v_~t5_pc~0_5} OutVars{~t5_pc~0=v_~t5_pc~0_5} AuxVars[] AssignedVars[] 10831#L405-2 [2940] L405-2-->L416: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 10830#L416 [4272] L416-->L855: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 10901#L855 [3711] L855-->L855-2: Formula: (and (> v_ULTIMATE.start_activate_threads_~tmp___4~0_11 0) (= v_~t5_st~0_7 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_11} OutVars{~t5_st~0=v_~t5_st~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_11} AuxVars[] AssignedVars[~t5_st~0] 10902#L855-2 [3093] L855-2-->L424: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_4|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 10578#L424 [3714] L424-->L424-2: Formula: (> v_~t6_pc~0_5 1) InVars {~t6_pc~0=v_~t6_pc~0_5} OutVars{~t6_pc~0=v_~t6_pc~0_5} AuxVars[] AssignedVars[] 10579#L424-2 [2503] L424-2-->L435: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 10575#L435 [4273] L435-->L863: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___5~0_49 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_28|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_28|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 10499#L863 [2425] L863-->L863-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___5~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} AuxVars[] AssignedVars[] 10470#L863-2 [3720] L863-2-->L733-1: Formula: (< v_~M_E~0_15 1) InVars {~M_E~0=v_~M_E~0_15} OutVars{~M_E~0=v_~M_E~0_15} AuxVars[] AssignedVars[] 10471#L733-1 [3722] L733-1-->L738-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 10864#L738-1 [3723] L738-1-->L743-1: Formula: (< 1 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 10597#L743-1 [3726] L743-1-->L748-1: Formula: (< 1 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 10598#L748-1 [3727] L748-1-->L753-1: Formula: (< v_~T4_E~0_10 1) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 10478#L753-1 [2407] L753-1-->L758-1: Formula: (and (= v_~T5_E~0_8 2) (= v_~T5_E~0_9 1)) InVars {~T5_E~0=v_~T5_E~0_9} OutVars{~T5_E~0=v_~T5_E~0_8} AuxVars[] AssignedVars[~T5_E~0] 10479#L758-1 [3732] L758-1-->L763-1: Formula: (< v_~T6_E~0_10 1) InVars {~T6_E~0=v_~T6_E~0_10} OutVars{~T6_E~0=v_~T6_E~0_10} AuxVars[] AssignedVars[] 10550#L763-1 [2475] L763-1-->L768-1: Formula: (and (= v_~E_1~0_12 2) (= 1 v_~E_1~0_13)) InVars {~E_1~0=v_~E_1~0_13} OutVars{~E_1~0=v_~E_1~0_12} AuxVars[] AssignedVars[~E_1~0] 10551#L768-1 [3736] L768-1-->L773-1: Formula: (< 1 v_~E_2~0_14) InVars {~E_2~0=v_~E_2~0_14} OutVars{~E_2~0=v_~E_2~0_14} AuxVars[] AssignedVars[] 10759#L773-1 [2767] L773-1-->L778-1: Formula: (and (= 1 v_~E_3~0_13) (= v_~E_3~0_12 2)) InVars {~E_3~0=v_~E_3~0_13} OutVars{~E_3~0=v_~E_3~0_12} AuxVars[] AssignedVars[~E_3~0] 10760#L778-1 [3740] L778-1-->L783-1: Formula: (< 1 v_~E_4~0_14) InVars {~E_4~0=v_~E_4~0_14} OutVars{~E_4~0=v_~E_4~0_14} AuxVars[] AssignedVars[] 10653#L783-1 [3742] L783-1-->L788-1: Formula: (> 1 v_~E_5~0_14) InVars {~E_5~0=v_~E_5~0_14} OutVars{~E_5~0=v_~E_5~0_14} AuxVars[] AssignedVars[] 10654#L788-1 [3743] L788-1-->L1014-1: Formula: (> 1 v_~E_6~0_14) InVars {~E_6~0=v_~E_6~0_14} OutVars{~E_6~0=v_~E_6~0_14} AuxVars[] AssignedVars[] 10488#L1014-1 [2020-06-22 00:13:06,243 INFO L796 eck$LassoCheckResult]: Loop: 10488#L1014-1 [4274] L1014-1-->L635: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp_ndt_7~0=v_ULTIMATE.start_eval_~tmp_ndt_7~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp_ndt_7~0] 10453#L635 [4275] L635-->L494: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_37} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 10826#L494 [2876] L494-->L531: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21 1) (= v_~m_st~0_8 0)) InVars {~m_st~0=v_~m_st~0_8} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21, ~m_st~0=v_~m_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 10522#L531 [4276] L531-->L546: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 10748#L546 [4278] L546-->L660-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 10891#L660-2 [3747] L660-2-->L660-4: Formula: (> v_~M_E~0_30 0) InVars {~M_E~0=v_~M_E~0_30} OutVars{~M_E~0=v_~M_E~0_30} AuxVars[] AssignedVars[] 10892#L660-4 [3058] L660-4-->L665-3: Formula: (and (= v_~T1_E~0_11 1) (= v_~T1_E~0_12 0)) InVars {~T1_E~0=v_~T1_E~0_12} OutVars{~T1_E~0=v_~T1_E~0_11} AuxVars[] AssignedVars[~T1_E~0] 10465#L665-3 [3756] L665-3-->L670-3: Formula: (< 0 v_~T2_E~0_13) InVars {~T2_E~0=v_~T2_E~0_13} OutVars{~T2_E~0=v_~T2_E~0_13} AuxVars[] AssignedVars[] 10466#L670-3 [3761] L670-3-->L675-3: Formula: (> 0 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 10540#L675-3 [2467] L675-3-->L680-3: Formula: (and (= v_~T4_E~0_11 1) (= v_~T4_E~0_12 0)) InVars {~T4_E~0=v_~T4_E~0_12} OutVars{~T4_E~0=v_~T4_E~0_11} AuxVars[] AssignedVars[~T4_E~0] 10541#L680-3 [3776] L680-3-->L685-3: Formula: (< 0 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 10767#L685-3 [3785] L685-3-->L690-3: Formula: (> v_~T6_E~0_13 0) InVars {~T6_E~0=v_~T6_E~0_13} OutVars{~T6_E~0=v_~T6_E~0_13} AuxVars[] AssignedVars[] 10768#L690-3 [3795] L690-3-->L695-3: Formula: (< 0 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 10646#L695-3 [2609] L695-3-->L700-3: Formula: (and (= 0 v_~E_2~0_30) (= v_~E_2~0_29 1)) InVars {~E_2~0=v_~E_2~0_30} OutVars{~E_2~0=v_~E_2~0_29} AuxVars[] AssignedVars[~E_2~0] 10647#L700-3 [3155] L700-3-->L705-3: Formula: (and (= v_~E_3~0_29 1) (= 0 v_~E_3~0_30)) InVars {~E_3~0=v_~E_3~0_30} OutVars{~E_3~0=v_~E_3~0_29} AuxVars[] AssignedVars[~E_3~0] 10709#L705-3 [2688] L705-3-->L710-3: Formula: (and (= v_~E_4~0_29 1) (= 0 v_~E_4~0_30)) InVars {~E_4~0=v_~E_4~0_30} OutVars{~E_4~0=v_~E_4~0_29} AuxVars[] AssignedVars[~E_4~0] 10591#L710-3 [2515] L710-3-->L715-3: Formula: (and (= 0 v_~E_5~0_30) (= v_~E_5~0_29 1)) InVars {~E_5~0=v_~E_5~0_30} OutVars{~E_5~0=v_~E_5~0_29} AuxVars[] AssignedVars[~E_5~0] 10592#L715-3 [3048] L715-3-->L720-3: Formula: (and (= v_~E_6~0_29 1) (= 0 v_~E_6~0_30)) InVars {~E_6~0=v_~E_6~0_30} OutVars{~E_6~0=v_~E_6~0_29} AuxVars[] AssignedVars[~E_6~0] 10454#L720-3 [2388] L720-3-->L310-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_43, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_43, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_25|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_25|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_25|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_43, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_43, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_43, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_25|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_25|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_25|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_25|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_43, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_25|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_43, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_43} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 10455#L310-21 [2779] L310-21-->L311-7: Formula: (= v_~m_pc~0_23 1) InVars {~m_pc~0=v_~m_pc~0_23} OutVars{~m_pc~0=v_~m_pc~0_23} AuxVars[] AssignedVars[] 10732#L311-7 [2720] L311-7-->L321-7: Formula: (and (= v_~M_E~0_31 1) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_46 1)) InVars {~M_E~0=v_~M_E~0_31} OutVars{~M_E~0=v_~M_E~0_31, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_46} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 10733#L321-7 [4303] L321-7-->L815-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 10694#L815-21 [3897] L815-21-->L815-23: Formula: (and (> 0 v_ULTIMATE.start_activate_threads_~tmp~1_47) (= v_~m_st~0_20 0)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_47} OutVars{~m_st~0=v_~m_st~0_20, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_47} AuxVars[] AssignedVars[~m_st~0] 10675#L815-23 [2638] L815-23-->L329-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 10676#L329-21 [3038] L329-21-->L330-7: Formula: (= v_~t1_pc~0_23 1) InVars {~t1_pc~0=v_~t1_pc~0_23} OutVars{~t1_pc~0=v_~t1_pc~0_23} AuxVars[] AssignedVars[] 10871#L330-7 [2981] L330-7-->L340-7: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_52 1) (= 1 v_~E_1~0_32)) InVars {~E_1~0=v_~E_1~0_32} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_52, ~E_1~0=v_~E_1~0_32} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 10786#L340-7 [4310] L340-7-->L823-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 10787#L823-21 [2931] L823-21-->L823-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} AuxVars[] AssignedVars[] 10846#L823-23 [2934] L823-23-->L348-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_25|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 10848#L348-21 [3306] L348-21-->L349-7: Formula: (= 1 v_~t2_pc~0_23) InVars {~t2_pc~0=v_~t2_pc~0_23} OutVars{~t2_pc~0=v_~t2_pc~0_23} AuxVars[] AssignedVars[] 10952#L349-7 [3255] L349-7-->L359-7: Formula: (and (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_52 1) (= 1 v_~E_2~0_32)) InVars {~E_2~0=v_~E_2~0_32} OutVars{~E_2~0=v_~E_2~0_32, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_52} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 10928#L359-7 [4317] L359-7-->L831-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 10569#L831-21 [2490] L831-21-->L831-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} AuxVars[] AssignedVars[] 10570#L831-23 [3197] L831-23-->L367-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_25|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 10480#L367-21 [2409] L367-21-->L368-7: Formula: (= v_~t3_pc~0_23 1) InVars {~t3_pc~0=v_~t3_pc~0_23} OutVars{~t3_pc~0=v_~t3_pc~0_23} AuxVars[] AssignedVars[] 10481#L368-7 [2539] L368-7-->L378-7: Formula: (and (= 1 v_~E_3~0_32) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_52 1)) InVars {~E_3~0=v_~E_3~0_32} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_52, ~E_3~0=v_~E_3~0_32} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 10448#L378-7 [4324] L378-7-->L839-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 10504#L839-21 [4023] L839-21-->L839-23: Formula: (and (= v_~t3_st~0_21 0) (> v_ULTIMATE.start_activate_threads_~tmp___2~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} OutVars{~t3_st~0=v_~t3_st~0_21, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} AuxVars[] AssignedVars[~t3_st~0] 10725#L839-23 [2722] L839-23-->L386-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_49, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 10655#L386-21 [4037] L386-21-->L386-23: Formula: (< 1 v_~t4_pc~0_24) InVars {~t4_pc~0=v_~t4_pc~0_24} OutVars{~t4_pc~0=v_~t4_pc~0_24} AuxVars[] AssignedVars[] 10656#L386-23 [2623] L386-23-->L397-7: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 10662#L397-7 [4331] L397-7-->L847-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 10691#L847-21 [4065] L847-21-->L847-23: Formula: (and (= v_~t4_st~0_22 0) (< v_ULTIMATE.start_activate_threads_~tmp___3~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47, ~t4_st~0=v_~t4_st~0_22} AuxVars[] AssignedVars[~t4_st~0] 10873#L847-23 [2983] L847-23-->L405-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_25|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 10837#L405-21 [2911] L405-21-->L406-7: Formula: (= v_~t5_pc~0_23 1) InVars {~t5_pc~0=v_~t5_pc~0_23} OutVars{~t5_pc~0=v_~t5_pc~0_23} AuxVars[] AssignedVars[] 10821#L406-7 [2874] L406-7-->L416-7: Formula: (and (= 1 v_~E_5~0_32) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_52 1)) InVars {~E_5~0=v_~E_5~0_32} OutVars{~E_5~0=v_~E_5~0_32, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_52} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 10823#L416-7 [4338] L416-7-->L855-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 10842#L855-21 [3251] L855-21-->L855-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} AuxVars[] AssignedVars[] 10951#L855-23 [3257] L855-23-->L424-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_25|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 10938#L424-21 [3173] L424-21-->L425-7: Formula: (= 1 v_~t6_pc~0_23) InVars {~t6_pc~0=v_~t6_pc~0_23} OutVars{~t6_pc~0=v_~t6_pc~0_23} AuxVars[] AssignedVars[] 10920#L425-7 [3114] L425-7-->L435-7: Formula: (and (= 1 v_~E_6~0_32) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_52 1)) InVars {~E_6~0=v_~E_6~0_32} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_52, ~E_6~0=v_~E_6~0_32} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 10564#L435-7 [4340] L435-7-->L863-21: Formula: (and (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___5~0_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_35|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_41|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 10565#L863-21 [4135] L863-21-->L863-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___5~0_47 0) (= v_~t6_st~0_22 0)) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} OutVars{~t6_st~0=v_~t6_st~0_22, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} AuxVars[] AssignedVars[~t6_st~0] 10607#L863-23 [4137] L863-23-->L733-3: Formula: (< v_~M_E~0_35 1) InVars {~M_E~0=v_~M_E~0_35} OutVars{~M_E~0=v_~M_E~0_35} AuxVars[] AssignedVars[] 10608#L733-3 [3184] L733-3-->L738-3: Formula: (and (= v_~T1_E~0_15 1) (= v_~T1_E~0_14 2)) InVars {~T1_E~0=v_~T1_E~0_15} OutVars{~T1_E~0=v_~T1_E~0_14} AuxVars[] AssignedVars[~T1_E~0] 10867#L738-3 [4142] L738-3-->L743-3: Formula: (< 1 v_~T2_E~0_16) InVars {~T2_E~0=v_~T2_E~0_16} OutVars{~T2_E~0=v_~T2_E~0_16} AuxVars[] AssignedVars[] 10587#L743-3 [4144] L743-3-->L748-3: Formula: (> 1 v_~T3_E~0_16) InVars {~T3_E~0=v_~T3_E~0_16} OutVars{~T3_E~0=v_~T3_E~0_16} AuxVars[] AssignedVars[] 10588#L748-3 [4145] L748-3-->L753-3: Formula: (> v_~T4_E~0_16 1) InVars {~T4_E~0=v_~T4_E~0_16} OutVars{~T4_E~0=v_~T4_E~0_16} AuxVars[] AssignedVars[] 10445#L753-3 [4147] L753-3-->L758-3: Formula: (> 1 v_~T5_E~0_16) InVars {~T5_E~0=v_~T5_E~0_16} OutVars{~T5_E~0=v_~T5_E~0_16} AuxVars[] AssignedVars[] 10446#L758-3 [4149] L758-3-->L763-3: Formula: (> v_~T6_E~0_16 1) InVars {~T6_E~0=v_~T6_E~0_16} OutVars{~T6_E~0=v_~T6_E~0_16} AuxVars[] AssignedVars[] 10536#L763-3 [4151] L763-3-->L768-3: Formula: (< 1 v_~E_1~0_36) InVars {~E_1~0=v_~E_1~0_36} OutVars{~E_1~0=v_~E_1~0_36} AuxVars[] AssignedVars[] 10537#L768-3 [3219] L768-3-->L773-3: Formula: (and (= 1 v_~E_2~0_35) (= v_~E_2~0_34 2)) InVars {~E_2~0=v_~E_2~0_35} OutVars{~E_2~0=v_~E_2~0_34} AuxVars[] AssignedVars[~E_2~0] 10762#L773-3 [2775] L773-3-->L778-3: Formula: (and (= 1 v_~E_3~0_35) (= v_~E_3~0_34 2)) InVars {~E_3~0=v_~E_3~0_35} OutVars{~E_3~0=v_~E_3~0_34} AuxVars[] AssignedVars[~E_3~0] 10763#L778-3 [3308] L778-3-->L783-3: Formula: (and (= 1 v_~E_4~0_35) (= v_~E_4~0_34 2)) InVars {~E_4~0=v_~E_4~0_35} OutVars{~E_4~0=v_~E_4~0_34} AuxVars[] AssignedVars[~E_4~0] 10658#L783-3 [4160] L783-3-->L788-3: Formula: (< 1 v_~E_5~0_36) InVars {~E_5~0=v_~E_5~0_36} OutVars{~E_5~0=v_~E_5~0_36} AuxVars[] AssignedVars[] 10659#L788-3 [4161] L788-3-->L793-3: Formula: (> 1 v_~E_6~0_36) InVars {~E_6~0=v_~E_6~0_36} OutVars{~E_6~0=v_~E_6~0_36} AuxVars[] AssignedVars[] 10865#L793-3 [2966] L793-3-->L494-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_30} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 10827#L494-1 [2878] L494-1-->L531-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33 1) (= 0 v_~m_st~0_21)) InVars {~m_st~0=v_~m_st~0_21} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33, ~m_st~0=v_~m_st~0_21} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 10524#L531-1 [4341] L531-1-->L1033: Formula: (and (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp~3] 10749#L1033 [4169] L1033-->L1033-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_6) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} AuxVars[] AssignedVars[] 10494#L1033-1 [2919] L1033-1-->L494-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_3|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_6, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_exists_runnable_thread_~__retres1~7, ULTIMATE.start_stop_simulation_#res] 10828#L494-2 [2882] L494-2-->L531-2: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9 1) (= v_~m_st~0_6 0)) InVars {~m_st~0=v_~m_st~0_6} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9, ~m_st~0=v_~m_st~0_6} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 10528#L531-2 [4343] L531-2-->L988: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 10754#L988 [3240] L988-->L995: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 10487#L995 [4354] L995-->L1014-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_6|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_#t~ret17, ULTIMATE.start_stop_simulation_#res] 10488#L1014-1 [2020-06-22 00:13:06,243 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:06,243 INFO L82 PathProgramCache]: Analyzing trace with hash -1919532465, now seen corresponding path program 1 times [2020-06-22 00:13:06,243 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:06,243 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:06,244 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:06,244 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2020-06-22 00:13:06,245 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:06,250 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:06,266 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:06,266 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:06,266 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-06-22 00:13:06,267 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-06-22 00:13:06,267 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:06,267 INFO L82 PathProgramCache]: Analyzing trace with hash -454034527, now seen corresponding path program 1 times [2020-06-22 00:13:06,267 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:06,267 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:06,268 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:06,268 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:06,268 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:06,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:06,293 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:06,294 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:06,294 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2020-06-22 00:13:06,294 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-06-22 00:13:06,295 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-06-22 00:13:06,295 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-06-22 00:13:06,295 INFO L87 Difference]: Start difference. First operand 518 states and 1124 transitions. cyclomatic complexity: 607 Second operand 3 states. [2020-06-22 00:13:06,845 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-06-22 00:13:06,845 INFO L93 Difference]: Finished difference Result 518 states and 1114 transitions. [2020-06-22 00:13:06,845 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-06-22 00:13:06,845 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 518 states and 1114 transitions. [2020-06-22 00:13:06,849 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 442 [2020-06-22 00:13:06,852 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 518 states to 518 states and 1114 transitions. [2020-06-22 00:13:06,852 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 518 [2020-06-22 00:13:06,853 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 518 [2020-06-22 00:13:06,853 INFO L73 IsDeterministic]: Start isDeterministic. Operand 518 states and 1114 transitions. [2020-06-22 00:13:06,853 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-06-22 00:13:06,854 INFO L706 BuchiCegarLoop]: Abstraction has 518 states and 1114 transitions. [2020-06-22 00:13:06,854 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 518 states and 1114 transitions. [2020-06-22 00:13:06,860 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 518 to 518. [2020-06-22 00:13:06,860 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 518 states. [2020-06-22 00:13:06,862 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 518 states to 518 states and 1114 transitions. [2020-06-22 00:13:06,862 INFO L729 BuchiCegarLoop]: Abstraction has 518 states and 1114 transitions. [2020-06-22 00:13:06,862 INFO L609 BuchiCegarLoop]: Abstraction has 518 states and 1114 transitions. [2020-06-22 00:13:06,862 INFO L442 BuchiCegarLoop]: ======== Iteration 12============ [2020-06-22 00:13:06,862 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 518 states and 1114 transitions. [2020-06-22 00:13:06,865 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 442 [2020-06-22 00:13:06,865 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-06-22 00:13:06,865 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-06-22 00:13:06,866 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:06,866 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:06,867 INFO L794 eck$LassoCheckResult]: Stem: 11923#ULTIMATE.startENTRY [4266] ULTIMATE.startENTRY-->L444: Formula: (and (= 1 v_~t6_i~0_7) (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~M_E~0_37 2) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 0 v_~t6_pc~0_26) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_6~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= v_~T6_E~0_18 2) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~t6_st~0_24) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t6_pc~0=v_~t6_pc~0_26, ~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~T6_E~0=v_~T6_E~0_18, ~M_E~0=v_~M_E~0_37, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ~T4_E~0=v_~T4_E~0_18, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_4|, ~t6_i~0=v_~t6_i~0_7, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ULTIMATE.start_main_~__retres1~8=v_ULTIMATE.start_main_~__retres1~8_6, ~T2_E~0=v_~T2_E~0_18, ~t6_st~0=v_~t6_st~0_24, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_6~0=v_~E_6~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t6_pc~0, ~t5_i~0, ~t1_pc~0, ~t5_st~0, ~T6_E~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ~T4_E~0, ULTIMATE.start_start_simulation_#t~ret17, ~t6_i~0, ~t2_st~0, ~t2_pc~0, ULTIMATE.start_main_~__retres1~8, ~T2_E~0, ~t6_st~0, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_6~0, ULTIMATE.start_main_#res, ~E_2~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 11573#L444 [2453] L444-->L451-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 11574#L451-1 [3030] L451-1-->L456-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 11659#L456-1 [2574] L456-1-->L461-1: Formula: (and (= v_~t2_st~0_2 0) (= 1 v_~t2_i~0_3)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_2} AuxVars[] AssignedVars[~t2_st~0] 11660#L461-1 [2880] L461-1-->L466-1: Formula: (and (= v_~t3_st~0_3 0) (= v_~t3_i~0_3 1)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_3, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 11575#L466-1 [2457] L466-1-->L471-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 11576#L471-1 [3209] L471-1-->L476-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 11799#L476-1 [2761] L476-1-->L481-1: Formula: (and (= 1 v_~t6_i~0_3) (= v_~t6_st~0_4 0)) InVars {~t6_i~0=v_~t6_i~0_3} OutVars{~t6_st~0=v_~t6_st~0_4, ~t6_i~0=v_~t6_i~0_3} AuxVars[] AssignedVars[~t6_st~0] 11800#L481-1 [3652] L481-1-->L660-1: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 11934#L660-1 [3654] L660-1-->L665-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 11493#L665-1 [3655] L665-1-->L670-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 11494#L670-1 [3658] L670-1-->L675-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 11582#L675-1 [3660] L675-1-->L680-1: Formula: (< v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 11583#L680-1 [3662] L680-1-->L685-1: Formula: (< v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 11808#L685-1 [3663] L685-1-->L690-1: Formula: (< 0 v_~T6_E~0_4) InVars {~T6_E~0=v_~T6_E~0_4} OutVars{~T6_E~0=v_~T6_E~0_4} AuxVars[] AssignedVars[] 11809#L690-1 [3310] L690-1-->L695-1: Formula: (and (= v_~E_1~0_5 0) (= v_~E_1~0_4 1)) InVars {~E_1~0=v_~E_1~0_5} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[~E_1~0] 11704#L695-1 [2621] L695-1-->L700-1: Formula: (and (= v_~E_2~0_4 1) (= v_~E_2~0_5 0)) InVars {~E_2~0=v_~E_2~0_5} OutVars{~E_2~0=v_~E_2~0_4} AuxVars[] AssignedVars[~E_2~0] 11705#L700-1 [3180] L700-1-->L705-1: Formula: (and (= v_~E_3~0_5 0) (= v_~E_3~0_4 1)) InVars {~E_3~0=v_~E_3~0_5} OutVars{~E_3~0=v_~E_3~0_4} AuxVars[] AssignedVars[~E_3~0] 11910#L705-1 [3672] L705-1-->L710-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 11643#L710-1 [2525] L710-1-->L715-1: Formula: (and (= v_~E_5~0_3 0) (= v_~E_5~0_2 1)) InVars {~E_5~0=v_~E_5~0_3} OutVars{~E_5~0=v_~E_5~0_2} AuxVars[] AssignedVars[~E_5~0] 11644#L715-1 [3676] L715-1-->L720-1: Formula: (< v_~E_6~0_4 0) InVars {~E_6~0=v_~E_6~0_4} OutVars{~E_6~0=v_~E_6~0_4} AuxVars[] AssignedVars[] 11527#L720-1 [2412] L720-1-->L310: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_7, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_4|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_4|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_7, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_4, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_4, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_2|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_2|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_4|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_4|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_7, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_2|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_4} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 11528#L310 [2597] L310-->L311: Formula: (= v_~m_pc~0_4 1) InVars {~m_pc~0=v_~m_pc~0_4} OutVars{~m_pc~0=v_~m_pc~0_4} AuxVars[] AssignedVars[] 11675#L311 [2732] L311-->L321: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_10 1) (= 1 v_~M_E~0_8)) InVars {~M_E~0=v_~M_E~0_8} OutVars{~M_E~0=v_~M_E~0_8, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_10} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 11673#L321 [4267] L321-->L815: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 11674#L815 [3682] L815-->L815-2: Formula: (and (= v_~m_st~0_5 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_11)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} OutVars{~m_st~0=v_~m_st~0_5, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} AuxVars[] AssignedVars[~m_st~0] 11906#L815-2 [2961] L815-2-->L329: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 11842#L329 [2848] L329-->L330: Formula: (= v_~t1_pc~0_4 1) InVars {~t1_pc~0=v_~t1_pc~0_4} OutVars{~t1_pc~0=v_~t1_pc~0_4} AuxVars[] AssignedVars[] 11843#L330 [3036] L330-->L340: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_10 1) (= v_~E_1~0_7 1)) InVars {~E_1~0=v_~E_1~0_7} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_10, ~E_1~0=v_~E_1~0_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 11840#L340 [4268] L340-->L823: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 11841#L823 [3688] L823-->L823-2: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___0~0_11 0) (= v_~t1_st~0_5 0)) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_11} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_11, ~t1_st~0=v_~t1_st~0_5} AuxVars[] AssignedVars[~t1_st~0] 11992#L823-2 [3235] L823-2-->L348: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_4|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 11976#L348 [3143] L348-->L349: Formula: (= v_~t2_pc~0_4 1) InVars {~t2_pc~0=v_~t2_pc~0_4} OutVars{~t2_pc~0=v_~t2_pc~0_4} AuxVars[] AssignedVars[] 11977#L349 [3267] L349-->L359: Formula: (and (= v_~E_2~0_7 1) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_10 1)) InVars {~E_2~0=v_~E_2~0_7} OutVars{~E_2~0=v_~E_2~0_7, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_10} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 11975#L359 [4269] L359-->L831: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 11650#L831 [3694] L831-->L831-2: Formula: (and (= v_~t2_st~0_5 0) (> v_ULTIMATE.start_activate_threads_~tmp___1~0_11 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_11} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_11, ~t2_st~0=v_~t2_st~0_5} AuxVars[] AssignedVars[~t2_st~0] 11638#L831-2 [2520] L831-2-->L367: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_4|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 11578#L367 [3695] L367-->L367-2: Formula: (> 1 v_~t3_pc~0_5) InVars {~t3_pc~0=v_~t3_pc~0_5} OutVars{~t3_pc~0=v_~t3_pc~0_5} AuxVars[] AssignedVars[] 11556#L367-2 [2438] L367-2-->L378: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 11557#L378 [4270] L378-->L839: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 11577#L839 [2791] L839-->L839-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} AuxVars[] AssignedVars[] 11815#L839-2 [2794] L839-2-->L386: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_7, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 11745#L386 [2675] L386-->L387: Formula: (= v_~t4_pc~0_4 1) InVars {~t4_pc~0=v_~t4_pc~0_4} OutVars{~t4_pc~0=v_~t4_pc~0_4} AuxVars[] AssignedVars[] 11664#L387 [2588] L387-->L397: Formula: (and (= v_~E_4~0_7 1) (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_10 1)) InVars {~E_4~0=v_~E_4~0_7} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_10, ~E_4~0=v_~E_4~0_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 11666#L397 [4271] L397-->L847: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 11744#L847 [3084] L847-->L847-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} AuxVars[] AssignedVars[] 11938#L847-2 [3064] L847-2-->L405: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_4|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 11939#L405 [3708] L405-->L405-2: Formula: (> 1 v_~t5_pc~0_5) InVars {~t5_pc~0=v_~t5_pc~0_5} OutVars{~t5_pc~0=v_~t5_pc~0_5} AuxVars[] AssignedVars[] 11875#L405-2 [2940] L405-2-->L416: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 11874#L416 [4272] L416-->L855: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 11945#L855 [3711] L855-->L855-2: Formula: (and (> v_ULTIMATE.start_activate_threads_~tmp___4~0_11 0) (= v_~t5_st~0_7 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_11} OutVars{~t5_st~0=v_~t5_st~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_11} AuxVars[] AssignedVars[~t5_st~0] 11946#L855-2 [3093] L855-2-->L424: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_4|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 11622#L424 [3714] L424-->L424-2: Formula: (> v_~t6_pc~0_5 1) InVars {~t6_pc~0=v_~t6_pc~0_5} OutVars{~t6_pc~0=v_~t6_pc~0_5} AuxVars[] AssignedVars[] 11623#L424-2 [2503] L424-2-->L435: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 11619#L435 [4273] L435-->L863: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___5~0_49 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_28|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_28|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 11543#L863 [2425] L863-->L863-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___5~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} AuxVars[] AssignedVars[] 11514#L863-2 [3720] L863-2-->L733-1: Formula: (< v_~M_E~0_15 1) InVars {~M_E~0=v_~M_E~0_15} OutVars{~M_E~0=v_~M_E~0_15} AuxVars[] AssignedVars[] 11515#L733-1 [3722] L733-1-->L738-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 11908#L738-1 [3723] L738-1-->L743-1: Formula: (< 1 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 11641#L743-1 [3726] L743-1-->L748-1: Formula: (< 1 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 11642#L748-1 [3727] L748-1-->L753-1: Formula: (< v_~T4_E~0_10 1) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 11522#L753-1 [2407] L753-1-->L758-1: Formula: (and (= v_~T5_E~0_8 2) (= v_~T5_E~0_9 1)) InVars {~T5_E~0=v_~T5_E~0_9} OutVars{~T5_E~0=v_~T5_E~0_8} AuxVars[] AssignedVars[~T5_E~0] 11523#L758-1 [3732] L758-1-->L763-1: Formula: (< v_~T6_E~0_10 1) InVars {~T6_E~0=v_~T6_E~0_10} OutVars{~T6_E~0=v_~T6_E~0_10} AuxVars[] AssignedVars[] 11594#L763-1 [2475] L763-1-->L768-1: Formula: (and (= v_~E_1~0_12 2) (= 1 v_~E_1~0_13)) InVars {~E_1~0=v_~E_1~0_13} OutVars{~E_1~0=v_~E_1~0_12} AuxVars[] AssignedVars[~E_1~0] 11595#L768-1 [3736] L768-1-->L773-1: Formula: (< 1 v_~E_2~0_14) InVars {~E_2~0=v_~E_2~0_14} OutVars{~E_2~0=v_~E_2~0_14} AuxVars[] AssignedVars[] 11803#L773-1 [2767] L773-1-->L778-1: Formula: (and (= 1 v_~E_3~0_13) (= v_~E_3~0_12 2)) InVars {~E_3~0=v_~E_3~0_13} OutVars{~E_3~0=v_~E_3~0_12} AuxVars[] AssignedVars[~E_3~0] 11804#L778-1 [3740] L778-1-->L783-1: Formula: (< 1 v_~E_4~0_14) InVars {~E_4~0=v_~E_4~0_14} OutVars{~E_4~0=v_~E_4~0_14} AuxVars[] AssignedVars[] 11697#L783-1 [3742] L783-1-->L788-1: Formula: (> 1 v_~E_5~0_14) InVars {~E_5~0=v_~E_5~0_14} OutVars{~E_5~0=v_~E_5~0_14} AuxVars[] AssignedVars[] 11698#L788-1 [3743] L788-1-->L1014-1: Formula: (> 1 v_~E_6~0_14) InVars {~E_6~0=v_~E_6~0_14} OutVars{~E_6~0=v_~E_6~0_14} AuxVars[] AssignedVars[] 11532#L1014-1 [2020-06-22 00:13:06,868 INFO L796 eck$LassoCheckResult]: Loop: 11532#L1014-1 [4274] L1014-1-->L635: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp_ndt_7~0=v_ULTIMATE.start_eval_~tmp_ndt_7~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp_ndt_7~0] 11497#L635 [4275] L635-->L494: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_37} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 11870#L494 [2876] L494-->L531: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21 1) (= v_~m_st~0_8 0)) InVars {~m_st~0=v_~m_st~0_8} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21, ~m_st~0=v_~m_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 11566#L531 [4276] L531-->L546: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 11792#L546 [4278] L546-->L660-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 11935#L660-2 [3747] L660-2-->L660-4: Formula: (> v_~M_E~0_30 0) InVars {~M_E~0=v_~M_E~0_30} OutVars{~M_E~0=v_~M_E~0_30} AuxVars[] AssignedVars[] 11936#L660-4 [3058] L660-4-->L665-3: Formula: (and (= v_~T1_E~0_11 1) (= v_~T1_E~0_12 0)) InVars {~T1_E~0=v_~T1_E~0_12} OutVars{~T1_E~0=v_~T1_E~0_11} AuxVars[] AssignedVars[~T1_E~0] 11509#L665-3 [3756] L665-3-->L670-3: Formula: (< 0 v_~T2_E~0_13) InVars {~T2_E~0=v_~T2_E~0_13} OutVars{~T2_E~0=v_~T2_E~0_13} AuxVars[] AssignedVars[] 11510#L670-3 [3762] L670-3-->L675-3: Formula: (< 0 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 11584#L675-3 [2467] L675-3-->L680-3: Formula: (and (= v_~T4_E~0_11 1) (= v_~T4_E~0_12 0)) InVars {~T4_E~0=v_~T4_E~0_12} OutVars{~T4_E~0=v_~T4_E~0_11} AuxVars[] AssignedVars[~T4_E~0] 11585#L680-3 [3776] L680-3-->L685-3: Formula: (< 0 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 11811#L685-3 [3785] L685-3-->L690-3: Formula: (> v_~T6_E~0_13 0) InVars {~T6_E~0=v_~T6_E~0_13} OutVars{~T6_E~0=v_~T6_E~0_13} AuxVars[] AssignedVars[] 11812#L690-3 [3795] L690-3-->L695-3: Formula: (< 0 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 11690#L695-3 [2609] L695-3-->L700-3: Formula: (and (= 0 v_~E_2~0_30) (= v_~E_2~0_29 1)) InVars {~E_2~0=v_~E_2~0_30} OutVars{~E_2~0=v_~E_2~0_29} AuxVars[] AssignedVars[~E_2~0] 11691#L700-3 [3155] L700-3-->L705-3: Formula: (and (= v_~E_3~0_29 1) (= 0 v_~E_3~0_30)) InVars {~E_3~0=v_~E_3~0_30} OutVars{~E_3~0=v_~E_3~0_29} AuxVars[] AssignedVars[~E_3~0] 11753#L705-3 [2688] L705-3-->L710-3: Formula: (and (= v_~E_4~0_29 1) (= 0 v_~E_4~0_30)) InVars {~E_4~0=v_~E_4~0_30} OutVars{~E_4~0=v_~E_4~0_29} AuxVars[] AssignedVars[~E_4~0] 11635#L710-3 [2515] L710-3-->L715-3: Formula: (and (= 0 v_~E_5~0_30) (= v_~E_5~0_29 1)) InVars {~E_5~0=v_~E_5~0_30} OutVars{~E_5~0=v_~E_5~0_29} AuxVars[] AssignedVars[~E_5~0] 11636#L715-3 [3048] L715-3-->L720-3: Formula: (and (= v_~E_6~0_29 1) (= 0 v_~E_6~0_30)) InVars {~E_6~0=v_~E_6~0_30} OutVars{~E_6~0=v_~E_6~0_29} AuxVars[] AssignedVars[~E_6~0] 11498#L720-3 [2388] L720-3-->L310-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_43, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_43, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_25|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_25|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_25|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_43, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_43, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_43, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_25|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_25|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_25|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_25|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_43, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_25|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_43, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_43} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 11499#L310-21 [2779] L310-21-->L311-7: Formula: (= v_~m_pc~0_23 1) InVars {~m_pc~0=v_~m_pc~0_23} OutVars{~m_pc~0=v_~m_pc~0_23} AuxVars[] AssignedVars[] 11776#L311-7 [2720] L311-7-->L321-7: Formula: (and (= v_~M_E~0_31 1) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_46 1)) InVars {~M_E~0=v_~M_E~0_31} OutVars{~M_E~0=v_~M_E~0_31, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_46} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 11777#L321-7 [4303] L321-7-->L815-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 11738#L815-21 [3897] L815-21-->L815-23: Formula: (and (> 0 v_ULTIMATE.start_activate_threads_~tmp~1_47) (= v_~m_st~0_20 0)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_47} OutVars{~m_st~0=v_~m_st~0_20, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_47} AuxVars[] AssignedVars[~m_st~0] 11719#L815-23 [2638] L815-23-->L329-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 11720#L329-21 [3038] L329-21-->L330-7: Formula: (= v_~t1_pc~0_23 1) InVars {~t1_pc~0=v_~t1_pc~0_23} OutVars{~t1_pc~0=v_~t1_pc~0_23} AuxVars[] AssignedVars[] 11915#L330-7 [2981] L330-7-->L340-7: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_52 1) (= 1 v_~E_1~0_32)) InVars {~E_1~0=v_~E_1~0_32} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_52, ~E_1~0=v_~E_1~0_32} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 11830#L340-7 [4310] L340-7-->L823-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 11831#L823-21 [2931] L823-21-->L823-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} AuxVars[] AssignedVars[] 11890#L823-23 [2934] L823-23-->L348-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_25|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 11892#L348-21 [3306] L348-21-->L349-7: Formula: (= 1 v_~t2_pc~0_23) InVars {~t2_pc~0=v_~t2_pc~0_23} OutVars{~t2_pc~0=v_~t2_pc~0_23} AuxVars[] AssignedVars[] 11996#L349-7 [3255] L349-7-->L359-7: Formula: (and (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_52 1) (= 1 v_~E_2~0_32)) InVars {~E_2~0=v_~E_2~0_32} OutVars{~E_2~0=v_~E_2~0_32, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_52} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 11972#L359-7 [4317] L359-7-->L831-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 11613#L831-21 [2490] L831-21-->L831-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} AuxVars[] AssignedVars[] 11614#L831-23 [3197] L831-23-->L367-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_25|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 11524#L367-21 [3995] L367-21-->L367-23: Formula: (> v_~t3_pc~0_24 1) InVars {~t3_pc~0=v_~t3_pc~0_24} OutVars{~t3_pc~0=v_~t3_pc~0_24} AuxVars[] AssignedVars[] 11491#L367-23 [2385] L367-23-->L378-7: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 11492#L378-7 [4324] L378-7-->L839-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 11548#L839-21 [4023] L839-21-->L839-23: Formula: (and (= v_~t3_st~0_21 0) (> v_ULTIMATE.start_activate_threads_~tmp___2~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} OutVars{~t3_st~0=v_~t3_st~0_21, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} AuxVars[] AssignedVars[~t3_st~0] 11769#L839-23 [2722] L839-23-->L386-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_49, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 11699#L386-21 [4037] L386-21-->L386-23: Formula: (< 1 v_~t4_pc~0_24) InVars {~t4_pc~0=v_~t4_pc~0_24} OutVars{~t4_pc~0=v_~t4_pc~0_24} AuxVars[] AssignedVars[] 11700#L386-23 [2623] L386-23-->L397-7: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 11706#L397-7 [4331] L397-7-->L847-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 11735#L847-21 [4065] L847-21-->L847-23: Formula: (and (= v_~t4_st~0_22 0) (< v_ULTIMATE.start_activate_threads_~tmp___3~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47, ~t4_st~0=v_~t4_st~0_22} AuxVars[] AssignedVars[~t4_st~0] 11917#L847-23 [2983] L847-23-->L405-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_25|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 11881#L405-21 [2911] L405-21-->L406-7: Formula: (= v_~t5_pc~0_23 1) InVars {~t5_pc~0=v_~t5_pc~0_23} OutVars{~t5_pc~0=v_~t5_pc~0_23} AuxVars[] AssignedVars[] 11865#L406-7 [2874] L406-7-->L416-7: Formula: (and (= 1 v_~E_5~0_32) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_52 1)) InVars {~E_5~0=v_~E_5~0_32} OutVars{~E_5~0=v_~E_5~0_32, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_52} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 11867#L416-7 [4338] L416-7-->L855-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 11886#L855-21 [3251] L855-21-->L855-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} AuxVars[] AssignedVars[] 11995#L855-23 [3257] L855-23-->L424-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_25|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 11982#L424-21 [3173] L424-21-->L425-7: Formula: (= 1 v_~t6_pc~0_23) InVars {~t6_pc~0=v_~t6_pc~0_23} OutVars{~t6_pc~0=v_~t6_pc~0_23} AuxVars[] AssignedVars[] 11964#L425-7 [3114] L425-7-->L435-7: Formula: (and (= 1 v_~E_6~0_32) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_52 1)) InVars {~E_6~0=v_~E_6~0_32} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_52, ~E_6~0=v_~E_6~0_32} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 11608#L435-7 [4340] L435-7-->L863-21: Formula: (and (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___5~0_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_35|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_41|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 11609#L863-21 [4135] L863-21-->L863-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___5~0_47 0) (= v_~t6_st~0_22 0)) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} OutVars{~t6_st~0=v_~t6_st~0_22, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} AuxVars[] AssignedVars[~t6_st~0] 11651#L863-23 [4137] L863-23-->L733-3: Formula: (< v_~M_E~0_35 1) InVars {~M_E~0=v_~M_E~0_35} OutVars{~M_E~0=v_~M_E~0_35} AuxVars[] AssignedVars[] 11652#L733-3 [3184] L733-3-->L738-3: Formula: (and (= v_~T1_E~0_15 1) (= v_~T1_E~0_14 2)) InVars {~T1_E~0=v_~T1_E~0_15} OutVars{~T1_E~0=v_~T1_E~0_14} AuxVars[] AssignedVars[~T1_E~0] 11911#L738-3 [4142] L738-3-->L743-3: Formula: (< 1 v_~T2_E~0_16) InVars {~T2_E~0=v_~T2_E~0_16} OutVars{~T2_E~0=v_~T2_E~0_16} AuxVars[] AssignedVars[] 11631#L743-3 [4143] L743-3-->L748-3: Formula: (< 1 v_~T3_E~0_16) InVars {~T3_E~0=v_~T3_E~0_16} OutVars{~T3_E~0=v_~T3_E~0_16} AuxVars[] AssignedVars[] 11632#L748-3 [4145] L748-3-->L753-3: Formula: (> v_~T4_E~0_16 1) InVars {~T4_E~0=v_~T4_E~0_16} OutVars{~T4_E~0=v_~T4_E~0_16} AuxVars[] AssignedVars[] 11489#L753-3 [4147] L753-3-->L758-3: Formula: (> 1 v_~T5_E~0_16) InVars {~T5_E~0=v_~T5_E~0_16} OutVars{~T5_E~0=v_~T5_E~0_16} AuxVars[] AssignedVars[] 11490#L758-3 [4149] L758-3-->L763-3: Formula: (> v_~T6_E~0_16 1) InVars {~T6_E~0=v_~T6_E~0_16} OutVars{~T6_E~0=v_~T6_E~0_16} AuxVars[] AssignedVars[] 11580#L763-3 [4151] L763-3-->L768-3: Formula: (< 1 v_~E_1~0_36) InVars {~E_1~0=v_~E_1~0_36} OutVars{~E_1~0=v_~E_1~0_36} AuxVars[] AssignedVars[] 11581#L768-3 [3219] L768-3-->L773-3: Formula: (and (= 1 v_~E_2~0_35) (= v_~E_2~0_34 2)) InVars {~E_2~0=v_~E_2~0_35} OutVars{~E_2~0=v_~E_2~0_34} AuxVars[] AssignedVars[~E_2~0] 11806#L773-3 [2775] L773-3-->L778-3: Formula: (and (= 1 v_~E_3~0_35) (= v_~E_3~0_34 2)) InVars {~E_3~0=v_~E_3~0_35} OutVars{~E_3~0=v_~E_3~0_34} AuxVars[] AssignedVars[~E_3~0] 11807#L778-3 [3308] L778-3-->L783-3: Formula: (and (= 1 v_~E_4~0_35) (= v_~E_4~0_34 2)) InVars {~E_4~0=v_~E_4~0_35} OutVars{~E_4~0=v_~E_4~0_34} AuxVars[] AssignedVars[~E_4~0] 11702#L783-3 [4160] L783-3-->L788-3: Formula: (< 1 v_~E_5~0_36) InVars {~E_5~0=v_~E_5~0_36} OutVars{~E_5~0=v_~E_5~0_36} AuxVars[] AssignedVars[] 11703#L788-3 [4161] L788-3-->L793-3: Formula: (> 1 v_~E_6~0_36) InVars {~E_6~0=v_~E_6~0_36} OutVars{~E_6~0=v_~E_6~0_36} AuxVars[] AssignedVars[] 11909#L793-3 [2966] L793-3-->L494-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_30} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 11871#L494-1 [2878] L494-1-->L531-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33 1) (= 0 v_~m_st~0_21)) InVars {~m_st~0=v_~m_st~0_21} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33, ~m_st~0=v_~m_st~0_21} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 11568#L531-1 [4341] L531-1-->L1033: Formula: (and (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp~3] 11793#L1033 [4169] L1033-->L1033-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_6) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} AuxVars[] AssignedVars[] 11538#L1033-1 [2919] L1033-1-->L494-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_3|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_6, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_exists_runnable_thread_~__retres1~7, ULTIMATE.start_stop_simulation_#res] 11872#L494-2 [2882] L494-2-->L531-2: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9 1) (= v_~m_st~0_6 0)) InVars {~m_st~0=v_~m_st~0_6} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9, ~m_st~0=v_~m_st~0_6} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 11572#L531-2 [4343] L531-2-->L988: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 11798#L988 [3240] L988-->L995: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 11531#L995 [4354] L995-->L1014-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_6|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_#t~ret17, ULTIMATE.start_stop_simulation_#res] 11532#L1014-1 [2020-06-22 00:13:06,869 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:06,869 INFO L82 PathProgramCache]: Analyzing trace with hash 556221139, now seen corresponding path program 1 times [2020-06-22 00:13:06,869 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:06,869 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:06,870 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:06,870 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:06,870 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:06,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:06,891 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:06,892 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:06,892 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-06-22 00:13:06,892 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-06-22 00:13:06,892 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:06,893 INFO L82 PathProgramCache]: Analyzing trace with hash -1018258515, now seen corresponding path program 1 times [2020-06-22 00:13:06,893 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:06,893 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:06,894 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:06,894 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:06,894 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:06,897 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:06,919 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:06,920 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:06,920 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2020-06-22 00:13:06,920 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-06-22 00:13:06,921 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-06-22 00:13:06,921 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-06-22 00:13:06,921 INFO L87 Difference]: Start difference. First operand 518 states and 1114 transitions. cyclomatic complexity: 597 Second operand 3 states. [2020-06-22 00:13:07,423 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-06-22 00:13:07,423 INFO L93 Difference]: Finished difference Result 518 states and 1104 transitions. [2020-06-22 00:13:07,423 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-06-22 00:13:07,424 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 518 states and 1104 transitions. [2020-06-22 00:13:07,427 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 442 [2020-06-22 00:13:07,430 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 518 states to 518 states and 1104 transitions. [2020-06-22 00:13:07,430 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 518 [2020-06-22 00:13:07,431 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 518 [2020-06-22 00:13:07,431 INFO L73 IsDeterministic]: Start isDeterministic. Operand 518 states and 1104 transitions. [2020-06-22 00:13:07,431 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-06-22 00:13:07,432 INFO L706 BuchiCegarLoop]: Abstraction has 518 states and 1104 transitions. [2020-06-22 00:13:07,432 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 518 states and 1104 transitions. [2020-06-22 00:13:07,439 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 518 to 518. [2020-06-22 00:13:07,439 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 518 states. [2020-06-22 00:13:07,441 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 518 states to 518 states and 1104 transitions. [2020-06-22 00:13:07,441 INFO L729 BuchiCegarLoop]: Abstraction has 518 states and 1104 transitions. [2020-06-22 00:13:07,441 INFO L609 BuchiCegarLoop]: Abstraction has 518 states and 1104 transitions. [2020-06-22 00:13:07,441 INFO L442 BuchiCegarLoop]: ======== Iteration 13============ [2020-06-22 00:13:07,441 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 518 states and 1104 transitions. [2020-06-22 00:13:07,443 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 442 [2020-06-22 00:13:07,444 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-06-22 00:13:07,444 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-06-22 00:13:07,445 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:07,445 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:07,446 INFO L794 eck$LassoCheckResult]: Stem: 12967#ULTIMATE.startENTRY [4266] ULTIMATE.startENTRY-->L444: Formula: (and (= 1 v_~t6_i~0_7) (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~M_E~0_37 2) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 0 v_~t6_pc~0_26) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_6~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= v_~T6_E~0_18 2) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~t6_st~0_24) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t6_pc~0=v_~t6_pc~0_26, ~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~T6_E~0=v_~T6_E~0_18, ~M_E~0=v_~M_E~0_37, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ~T4_E~0=v_~T4_E~0_18, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_4|, ~t6_i~0=v_~t6_i~0_7, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ULTIMATE.start_main_~__retres1~8=v_ULTIMATE.start_main_~__retres1~8_6, ~T2_E~0=v_~T2_E~0_18, ~t6_st~0=v_~t6_st~0_24, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_6~0=v_~E_6~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t6_pc~0, ~t5_i~0, ~t1_pc~0, ~t5_st~0, ~T6_E~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ~T4_E~0, ULTIMATE.start_start_simulation_#t~ret17, ~t6_i~0, ~t2_st~0, ~t2_pc~0, ULTIMATE.start_main_~__retres1~8, ~T2_E~0, ~t6_st~0, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_6~0, ULTIMATE.start_main_#res, ~E_2~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 12617#L444 [2453] L444-->L451-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 12618#L451-1 [3030] L451-1-->L456-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 12703#L456-1 [2574] L456-1-->L461-1: Formula: (and (= v_~t2_st~0_2 0) (= 1 v_~t2_i~0_3)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_2} AuxVars[] AssignedVars[~t2_st~0] 12704#L461-1 [2880] L461-1-->L466-1: Formula: (and (= v_~t3_st~0_3 0) (= v_~t3_i~0_3 1)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_3, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 12619#L466-1 [2457] L466-1-->L471-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 12620#L471-1 [3209] L471-1-->L476-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 12843#L476-1 [2761] L476-1-->L481-1: Formula: (and (= 1 v_~t6_i~0_3) (= v_~t6_st~0_4 0)) InVars {~t6_i~0=v_~t6_i~0_3} OutVars{~t6_st~0=v_~t6_st~0_4, ~t6_i~0=v_~t6_i~0_3} AuxVars[] AssignedVars[~t6_st~0] 12844#L481-1 [3652] L481-1-->L660-1: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 12978#L660-1 [3654] L660-1-->L665-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 12537#L665-1 [3655] L665-1-->L670-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 12538#L670-1 [3658] L670-1-->L675-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 12626#L675-1 [3659] L675-1-->L680-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 12627#L680-1 [3662] L680-1-->L685-1: Formula: (< v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 12852#L685-1 [3663] L685-1-->L690-1: Formula: (< 0 v_~T6_E~0_4) InVars {~T6_E~0=v_~T6_E~0_4} OutVars{~T6_E~0=v_~T6_E~0_4} AuxVars[] AssignedVars[] 12853#L690-1 [3310] L690-1-->L695-1: Formula: (and (= v_~E_1~0_5 0) (= v_~E_1~0_4 1)) InVars {~E_1~0=v_~E_1~0_5} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[~E_1~0] 12748#L695-1 [2621] L695-1-->L700-1: Formula: (and (= v_~E_2~0_4 1) (= v_~E_2~0_5 0)) InVars {~E_2~0=v_~E_2~0_5} OutVars{~E_2~0=v_~E_2~0_4} AuxVars[] AssignedVars[~E_2~0] 12749#L700-1 [3180] L700-1-->L705-1: Formula: (and (= v_~E_3~0_5 0) (= v_~E_3~0_4 1)) InVars {~E_3~0=v_~E_3~0_5} OutVars{~E_3~0=v_~E_3~0_4} AuxVars[] AssignedVars[~E_3~0] 12954#L705-1 [3672] L705-1-->L710-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 12687#L710-1 [2525] L710-1-->L715-1: Formula: (and (= v_~E_5~0_3 0) (= v_~E_5~0_2 1)) InVars {~E_5~0=v_~E_5~0_3} OutVars{~E_5~0=v_~E_5~0_2} AuxVars[] AssignedVars[~E_5~0] 12688#L715-1 [3676] L715-1-->L720-1: Formula: (< v_~E_6~0_4 0) InVars {~E_6~0=v_~E_6~0_4} OutVars{~E_6~0=v_~E_6~0_4} AuxVars[] AssignedVars[] 12571#L720-1 [2412] L720-1-->L310: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_7, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_4|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_4|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_7, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_4, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_4, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_2|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_2|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_4|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_4|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_7, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_2|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_4} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 12572#L310 [2597] L310-->L311: Formula: (= v_~m_pc~0_4 1) InVars {~m_pc~0=v_~m_pc~0_4} OutVars{~m_pc~0=v_~m_pc~0_4} AuxVars[] AssignedVars[] 12719#L311 [2732] L311-->L321: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_10 1) (= 1 v_~M_E~0_8)) InVars {~M_E~0=v_~M_E~0_8} OutVars{~M_E~0=v_~M_E~0_8, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_10} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 12717#L321 [4267] L321-->L815: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 12718#L815 [3682] L815-->L815-2: Formula: (and (= v_~m_st~0_5 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_11)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} OutVars{~m_st~0=v_~m_st~0_5, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} AuxVars[] AssignedVars[~m_st~0] 12950#L815-2 [2961] L815-2-->L329: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 12886#L329 [2848] L329-->L330: Formula: (= v_~t1_pc~0_4 1) InVars {~t1_pc~0=v_~t1_pc~0_4} OutVars{~t1_pc~0=v_~t1_pc~0_4} AuxVars[] AssignedVars[] 12887#L330 [3036] L330-->L340: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_10 1) (= v_~E_1~0_7 1)) InVars {~E_1~0=v_~E_1~0_7} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_10, ~E_1~0=v_~E_1~0_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 12884#L340 [4268] L340-->L823: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 12885#L823 [3688] L823-->L823-2: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___0~0_11 0) (= v_~t1_st~0_5 0)) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_11} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_11, ~t1_st~0=v_~t1_st~0_5} AuxVars[] AssignedVars[~t1_st~0] 13036#L823-2 [3235] L823-2-->L348: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_4|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 13020#L348 [3143] L348-->L349: Formula: (= v_~t2_pc~0_4 1) InVars {~t2_pc~0=v_~t2_pc~0_4} OutVars{~t2_pc~0=v_~t2_pc~0_4} AuxVars[] AssignedVars[] 13021#L349 [3267] L349-->L359: Formula: (and (= v_~E_2~0_7 1) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_10 1)) InVars {~E_2~0=v_~E_2~0_7} OutVars{~E_2~0=v_~E_2~0_7, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_10} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 13019#L359 [4269] L359-->L831: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 12694#L831 [3694] L831-->L831-2: Formula: (and (= v_~t2_st~0_5 0) (> v_ULTIMATE.start_activate_threads_~tmp___1~0_11 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_11} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_11, ~t2_st~0=v_~t2_st~0_5} AuxVars[] AssignedVars[~t2_st~0] 12682#L831-2 [2520] L831-2-->L367: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_4|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 12622#L367 [3695] L367-->L367-2: Formula: (> 1 v_~t3_pc~0_5) InVars {~t3_pc~0=v_~t3_pc~0_5} OutVars{~t3_pc~0=v_~t3_pc~0_5} AuxVars[] AssignedVars[] 12600#L367-2 [2438] L367-2-->L378: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 12601#L378 [4270] L378-->L839: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 12621#L839 [2791] L839-->L839-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} AuxVars[] AssignedVars[] 12859#L839-2 [2794] L839-2-->L386: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_7, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 12789#L386 [2675] L386-->L387: Formula: (= v_~t4_pc~0_4 1) InVars {~t4_pc~0=v_~t4_pc~0_4} OutVars{~t4_pc~0=v_~t4_pc~0_4} AuxVars[] AssignedVars[] 12708#L387 [2588] L387-->L397: Formula: (and (= v_~E_4~0_7 1) (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_10 1)) InVars {~E_4~0=v_~E_4~0_7} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_10, ~E_4~0=v_~E_4~0_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 12710#L397 [4271] L397-->L847: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 12788#L847 [3084] L847-->L847-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} AuxVars[] AssignedVars[] 12982#L847-2 [3064] L847-2-->L405: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_4|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 12983#L405 [3708] L405-->L405-2: Formula: (> 1 v_~t5_pc~0_5) InVars {~t5_pc~0=v_~t5_pc~0_5} OutVars{~t5_pc~0=v_~t5_pc~0_5} AuxVars[] AssignedVars[] 12919#L405-2 [2940] L405-2-->L416: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 12918#L416 [4272] L416-->L855: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 12989#L855 [3711] L855-->L855-2: Formula: (and (> v_ULTIMATE.start_activate_threads_~tmp___4~0_11 0) (= v_~t5_st~0_7 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_11} OutVars{~t5_st~0=v_~t5_st~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_11} AuxVars[] AssignedVars[~t5_st~0] 12990#L855-2 [3093] L855-2-->L424: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_4|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 12666#L424 [3714] L424-->L424-2: Formula: (> v_~t6_pc~0_5 1) InVars {~t6_pc~0=v_~t6_pc~0_5} OutVars{~t6_pc~0=v_~t6_pc~0_5} AuxVars[] AssignedVars[] 12667#L424-2 [2503] L424-2-->L435: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 12663#L435 [4273] L435-->L863: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___5~0_49 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_28|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_28|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 12587#L863 [2425] L863-->L863-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___5~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} AuxVars[] AssignedVars[] 12561#L863-2 [3720] L863-2-->L733-1: Formula: (< v_~M_E~0_15 1) InVars {~M_E~0=v_~M_E~0_15} OutVars{~M_E~0=v_~M_E~0_15} AuxVars[] AssignedVars[] 12562#L733-1 [3722] L733-1-->L738-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 12952#L738-1 [3723] L738-1-->L743-1: Formula: (< 1 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 12685#L743-1 [3726] L743-1-->L748-1: Formula: (< 1 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 12686#L748-1 [3728] L748-1-->L753-1: Formula: (> v_~T4_E~0_10 1) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 12566#L753-1 [2407] L753-1-->L758-1: Formula: (and (= v_~T5_E~0_8 2) (= v_~T5_E~0_9 1)) InVars {~T5_E~0=v_~T5_E~0_9} OutVars{~T5_E~0=v_~T5_E~0_8} AuxVars[] AssignedVars[~T5_E~0] 12567#L758-1 [3732] L758-1-->L763-1: Formula: (< v_~T6_E~0_10 1) InVars {~T6_E~0=v_~T6_E~0_10} OutVars{~T6_E~0=v_~T6_E~0_10} AuxVars[] AssignedVars[] 12638#L763-1 [2475] L763-1-->L768-1: Formula: (and (= v_~E_1~0_12 2) (= 1 v_~E_1~0_13)) InVars {~E_1~0=v_~E_1~0_13} OutVars{~E_1~0=v_~E_1~0_12} AuxVars[] AssignedVars[~E_1~0] 12639#L768-1 [3736] L768-1-->L773-1: Formula: (< 1 v_~E_2~0_14) InVars {~E_2~0=v_~E_2~0_14} OutVars{~E_2~0=v_~E_2~0_14} AuxVars[] AssignedVars[] 12847#L773-1 [2767] L773-1-->L778-1: Formula: (and (= 1 v_~E_3~0_13) (= v_~E_3~0_12 2)) InVars {~E_3~0=v_~E_3~0_13} OutVars{~E_3~0=v_~E_3~0_12} AuxVars[] AssignedVars[~E_3~0] 12848#L778-1 [3740] L778-1-->L783-1: Formula: (< 1 v_~E_4~0_14) InVars {~E_4~0=v_~E_4~0_14} OutVars{~E_4~0=v_~E_4~0_14} AuxVars[] AssignedVars[] 12741#L783-1 [3742] L783-1-->L788-1: Formula: (> 1 v_~E_5~0_14) InVars {~E_5~0=v_~E_5~0_14} OutVars{~E_5~0=v_~E_5~0_14} AuxVars[] AssignedVars[] 12742#L788-1 [3743] L788-1-->L1014-1: Formula: (> 1 v_~E_6~0_14) InVars {~E_6~0=v_~E_6~0_14} OutVars{~E_6~0=v_~E_6~0_14} AuxVars[] AssignedVars[] 12576#L1014-1 [2020-06-22 00:13:07,447 INFO L796 eck$LassoCheckResult]: Loop: 12576#L1014-1 [4274] L1014-1-->L635: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp_ndt_7~0=v_ULTIMATE.start_eval_~tmp_ndt_7~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp_ndt_7~0] 12541#L635 [4275] L635-->L494: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_37} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 12914#L494 [2876] L494-->L531: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21 1) (= v_~m_st~0_8 0)) InVars {~m_st~0=v_~m_st~0_8} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21, ~m_st~0=v_~m_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 12610#L531 [4276] L531-->L546: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 12836#L546 [4278] L546-->L660-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 12979#L660-2 [3747] L660-2-->L660-4: Formula: (> v_~M_E~0_30 0) InVars {~M_E~0=v_~M_E~0_30} OutVars{~M_E~0=v_~M_E~0_30} AuxVars[] AssignedVars[] 12980#L660-4 [3058] L660-4-->L665-3: Formula: (and (= v_~T1_E~0_11 1) (= v_~T1_E~0_12 0)) InVars {~T1_E~0=v_~T1_E~0_12} OutVars{~T1_E~0=v_~T1_E~0_11} AuxVars[] AssignedVars[~T1_E~0] 12553#L665-3 [3756] L665-3-->L670-3: Formula: (< 0 v_~T2_E~0_13) InVars {~T2_E~0=v_~T2_E~0_13} OutVars{~T2_E~0=v_~T2_E~0_13} AuxVars[] AssignedVars[] 12554#L670-3 [3762] L670-3-->L675-3: Formula: (< 0 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 12628#L675-3 [3768] L675-3-->L680-3: Formula: (> v_~T4_E~0_13 0) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 12629#L680-3 [3776] L680-3-->L685-3: Formula: (< 0 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 12855#L685-3 [3785] L685-3-->L690-3: Formula: (> v_~T6_E~0_13 0) InVars {~T6_E~0=v_~T6_E~0_13} OutVars{~T6_E~0=v_~T6_E~0_13} AuxVars[] AssignedVars[] 12856#L690-3 [3795] L690-3-->L695-3: Formula: (< 0 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 12734#L695-3 [2609] L695-3-->L700-3: Formula: (and (= 0 v_~E_2~0_30) (= v_~E_2~0_29 1)) InVars {~E_2~0=v_~E_2~0_30} OutVars{~E_2~0=v_~E_2~0_29} AuxVars[] AssignedVars[~E_2~0] 12735#L700-3 [3155] L700-3-->L705-3: Formula: (and (= v_~E_3~0_29 1) (= 0 v_~E_3~0_30)) InVars {~E_3~0=v_~E_3~0_30} OutVars{~E_3~0=v_~E_3~0_29} AuxVars[] AssignedVars[~E_3~0] 12797#L705-3 [2688] L705-3-->L710-3: Formula: (and (= v_~E_4~0_29 1) (= 0 v_~E_4~0_30)) InVars {~E_4~0=v_~E_4~0_30} OutVars{~E_4~0=v_~E_4~0_29} AuxVars[] AssignedVars[~E_4~0] 12679#L710-3 [2515] L710-3-->L715-3: Formula: (and (= 0 v_~E_5~0_30) (= v_~E_5~0_29 1)) InVars {~E_5~0=v_~E_5~0_30} OutVars{~E_5~0=v_~E_5~0_29} AuxVars[] AssignedVars[~E_5~0] 12680#L715-3 [3048] L715-3-->L720-3: Formula: (and (= v_~E_6~0_29 1) (= 0 v_~E_6~0_30)) InVars {~E_6~0=v_~E_6~0_30} OutVars{~E_6~0=v_~E_6~0_29} AuxVars[] AssignedVars[~E_6~0] 12542#L720-3 [2388] L720-3-->L310-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_43, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_43, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_25|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_25|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_25|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_43, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_43, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_43, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_25|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_25|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_25|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_25|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_43, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_25|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_43, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_43} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 12543#L310-21 [2779] L310-21-->L311-7: Formula: (= v_~m_pc~0_23 1) InVars {~m_pc~0=v_~m_pc~0_23} OutVars{~m_pc~0=v_~m_pc~0_23} AuxVars[] AssignedVars[] 12820#L311-7 [2720] L311-7-->L321-7: Formula: (and (= v_~M_E~0_31 1) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_46 1)) InVars {~M_E~0=v_~M_E~0_31} OutVars{~M_E~0=v_~M_E~0_31, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_46} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 12821#L321-7 [4303] L321-7-->L815-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 12782#L815-21 [3897] L815-21-->L815-23: Formula: (and (> 0 v_ULTIMATE.start_activate_threads_~tmp~1_47) (= v_~m_st~0_20 0)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_47} OutVars{~m_st~0=v_~m_st~0_20, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_47} AuxVars[] AssignedVars[~m_st~0] 12763#L815-23 [2638] L815-23-->L329-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 12764#L329-21 [3911] L329-21-->L329-23: Formula: (< v_~t1_pc~0_24 1) InVars {~t1_pc~0=v_~t1_pc~0_24} OutVars{~t1_pc~0=v_~t1_pc~0_24} AuxVars[] AssignedVars[] 12960#L329-23 [3052] L329-23-->L340-7: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 12874#L340-7 [4310] L340-7-->L823-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 12875#L823-21 [2931] L823-21-->L823-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} AuxVars[] AssignedVars[] 12934#L823-23 [2934] L823-23-->L348-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_25|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 12936#L348-21 [3306] L348-21-->L349-7: Formula: (= 1 v_~t2_pc~0_23) InVars {~t2_pc~0=v_~t2_pc~0_23} OutVars{~t2_pc~0=v_~t2_pc~0_23} AuxVars[] AssignedVars[] 13040#L349-7 [3255] L349-7-->L359-7: Formula: (and (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_52 1) (= 1 v_~E_2~0_32)) InVars {~E_2~0=v_~E_2~0_32} OutVars{~E_2~0=v_~E_2~0_32, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_52} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 13016#L359-7 [4317] L359-7-->L831-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 12657#L831-21 [2490] L831-21-->L831-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} AuxVars[] AssignedVars[] 12658#L831-23 [3197] L831-23-->L367-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_25|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 12568#L367-21 [3995] L367-21-->L367-23: Formula: (> v_~t3_pc~0_24 1) InVars {~t3_pc~0=v_~t3_pc~0_24} OutVars{~t3_pc~0=v_~t3_pc~0_24} AuxVars[] AssignedVars[] 12535#L367-23 [2385] L367-23-->L378-7: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 12536#L378-7 [4324] L378-7-->L839-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 12592#L839-21 [4023] L839-21-->L839-23: Formula: (and (= v_~t3_st~0_21 0) (> v_ULTIMATE.start_activate_threads_~tmp___2~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} OutVars{~t3_st~0=v_~t3_st~0_21, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} AuxVars[] AssignedVars[~t3_st~0] 12813#L839-23 [2722] L839-23-->L386-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_49, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 12743#L386-21 [4037] L386-21-->L386-23: Formula: (< 1 v_~t4_pc~0_24) InVars {~t4_pc~0=v_~t4_pc~0_24} OutVars{~t4_pc~0=v_~t4_pc~0_24} AuxVars[] AssignedVars[] 12744#L386-23 [2623] L386-23-->L397-7: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 12750#L397-7 [4331] L397-7-->L847-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 12779#L847-21 [4065] L847-21-->L847-23: Formula: (and (= v_~t4_st~0_22 0) (< v_ULTIMATE.start_activate_threads_~tmp___3~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47, ~t4_st~0=v_~t4_st~0_22} AuxVars[] AssignedVars[~t4_st~0] 12961#L847-23 [2983] L847-23-->L405-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_25|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 12925#L405-21 [2911] L405-21-->L406-7: Formula: (= v_~t5_pc~0_23 1) InVars {~t5_pc~0=v_~t5_pc~0_23} OutVars{~t5_pc~0=v_~t5_pc~0_23} AuxVars[] AssignedVars[] 12909#L406-7 [2874] L406-7-->L416-7: Formula: (and (= 1 v_~E_5~0_32) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_52 1)) InVars {~E_5~0=v_~E_5~0_32} OutVars{~E_5~0=v_~E_5~0_32, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_52} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 12911#L416-7 [4338] L416-7-->L855-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 12930#L855-21 [3251] L855-21-->L855-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} AuxVars[] AssignedVars[] 13039#L855-23 [3257] L855-23-->L424-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_25|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 13026#L424-21 [3173] L424-21-->L425-7: Formula: (= 1 v_~t6_pc~0_23) InVars {~t6_pc~0=v_~t6_pc~0_23} OutVars{~t6_pc~0=v_~t6_pc~0_23} AuxVars[] AssignedVars[] 13008#L425-7 [3114] L425-7-->L435-7: Formula: (and (= 1 v_~E_6~0_32) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_52 1)) InVars {~E_6~0=v_~E_6~0_32} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_52, ~E_6~0=v_~E_6~0_32} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 12652#L435-7 [4340] L435-7-->L863-21: Formula: (and (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___5~0_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_35|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_41|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 12653#L863-21 [4135] L863-21-->L863-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___5~0_47 0) (= v_~t6_st~0_22 0)) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} OutVars{~t6_st~0=v_~t6_st~0_22, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} AuxVars[] AssignedVars[~t6_st~0] 12695#L863-23 [4137] L863-23-->L733-3: Formula: (< v_~M_E~0_35 1) InVars {~M_E~0=v_~M_E~0_35} OutVars{~M_E~0=v_~M_E~0_35} AuxVars[] AssignedVars[] 12696#L733-3 [3184] L733-3-->L738-3: Formula: (and (= v_~T1_E~0_15 1) (= v_~T1_E~0_14 2)) InVars {~T1_E~0=v_~T1_E~0_15} OutVars{~T1_E~0=v_~T1_E~0_14} AuxVars[] AssignedVars[~T1_E~0] 12955#L738-3 [4142] L738-3-->L743-3: Formula: (< 1 v_~T2_E~0_16) InVars {~T2_E~0=v_~T2_E~0_16} OutVars{~T2_E~0=v_~T2_E~0_16} AuxVars[] AssignedVars[] 12675#L743-3 [4143] L743-3-->L748-3: Formula: (< 1 v_~T3_E~0_16) InVars {~T3_E~0=v_~T3_E~0_16} OutVars{~T3_E~0=v_~T3_E~0_16} AuxVars[] AssignedVars[] 12676#L748-3 [4145] L748-3-->L753-3: Formula: (> v_~T4_E~0_16 1) InVars {~T4_E~0=v_~T4_E~0_16} OutVars{~T4_E~0=v_~T4_E~0_16} AuxVars[] AssignedVars[] 12533#L753-3 [4147] L753-3-->L758-3: Formula: (> 1 v_~T5_E~0_16) InVars {~T5_E~0=v_~T5_E~0_16} OutVars{~T5_E~0=v_~T5_E~0_16} AuxVars[] AssignedVars[] 12534#L758-3 [4149] L758-3-->L763-3: Formula: (> v_~T6_E~0_16 1) InVars {~T6_E~0=v_~T6_E~0_16} OutVars{~T6_E~0=v_~T6_E~0_16} AuxVars[] AssignedVars[] 12624#L763-3 [4151] L763-3-->L768-3: Formula: (< 1 v_~E_1~0_36) InVars {~E_1~0=v_~E_1~0_36} OutVars{~E_1~0=v_~E_1~0_36} AuxVars[] AssignedVars[] 12625#L768-3 [3219] L768-3-->L773-3: Formula: (and (= 1 v_~E_2~0_35) (= v_~E_2~0_34 2)) InVars {~E_2~0=v_~E_2~0_35} OutVars{~E_2~0=v_~E_2~0_34} AuxVars[] AssignedVars[~E_2~0] 12850#L773-3 [2775] L773-3-->L778-3: Formula: (and (= 1 v_~E_3~0_35) (= v_~E_3~0_34 2)) InVars {~E_3~0=v_~E_3~0_35} OutVars{~E_3~0=v_~E_3~0_34} AuxVars[] AssignedVars[~E_3~0] 12851#L778-3 [3308] L778-3-->L783-3: Formula: (and (= 1 v_~E_4~0_35) (= v_~E_4~0_34 2)) InVars {~E_4~0=v_~E_4~0_35} OutVars{~E_4~0=v_~E_4~0_34} AuxVars[] AssignedVars[~E_4~0] 12746#L783-3 [4160] L783-3-->L788-3: Formula: (< 1 v_~E_5~0_36) InVars {~E_5~0=v_~E_5~0_36} OutVars{~E_5~0=v_~E_5~0_36} AuxVars[] AssignedVars[] 12747#L788-3 [4161] L788-3-->L793-3: Formula: (> 1 v_~E_6~0_36) InVars {~E_6~0=v_~E_6~0_36} OutVars{~E_6~0=v_~E_6~0_36} AuxVars[] AssignedVars[] 12953#L793-3 [2966] L793-3-->L494-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_30} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 12915#L494-1 [2878] L494-1-->L531-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33 1) (= 0 v_~m_st~0_21)) InVars {~m_st~0=v_~m_st~0_21} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33, ~m_st~0=v_~m_st~0_21} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 12612#L531-1 [4341] L531-1-->L1033: Formula: (and (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp~3] 12837#L1033 [4169] L1033-->L1033-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_6) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} AuxVars[] AssignedVars[] 12582#L1033-1 [2919] L1033-1-->L494-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_3|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_6, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_exists_runnable_thread_~__retres1~7, ULTIMATE.start_stop_simulation_#res] 12916#L494-2 [2882] L494-2-->L531-2: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9 1) (= v_~m_st~0_6 0)) InVars {~m_st~0=v_~m_st~0_6} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9, ~m_st~0=v_~m_st~0_6} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 12616#L531-2 [4343] L531-2-->L988: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 12842#L988 [3240] L988-->L995: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 12575#L995 [4354] L995-->L1014-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_6|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_#t~ret17, ULTIMATE.start_stop_simulation_#res] 12576#L1014-1 [2020-06-22 00:13:07,448 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:07,448 INFO L82 PathProgramCache]: Analyzing trace with hash -1881691949, now seen corresponding path program 1 times [2020-06-22 00:13:07,448 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:07,448 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:07,449 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:07,449 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:07,449 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:07,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:07,470 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:07,470 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:07,470 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-06-22 00:13:07,470 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-06-22 00:13:07,471 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:07,471 INFO L82 PathProgramCache]: Analyzing trace with hash -1034753286, now seen corresponding path program 1 times [2020-06-22 00:13:07,471 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:07,471 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:07,472 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:07,472 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:07,472 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:07,475 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:07,497 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:07,497 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:07,497 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2020-06-22 00:13:07,497 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-06-22 00:13:07,498 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-06-22 00:13:07,498 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-06-22 00:13:07,498 INFO L87 Difference]: Start difference. First operand 518 states and 1104 transitions. cyclomatic complexity: 587 Second operand 3 states. [2020-06-22 00:13:07,988 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-06-22 00:13:07,988 INFO L93 Difference]: Finished difference Result 518 states and 1094 transitions. [2020-06-22 00:13:07,989 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-06-22 00:13:07,989 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 518 states and 1094 transitions. [2020-06-22 00:13:07,992 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 442 [2020-06-22 00:13:07,996 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 518 states to 518 states and 1094 transitions. [2020-06-22 00:13:07,997 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 518 [2020-06-22 00:13:07,997 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 518 [2020-06-22 00:13:07,997 INFO L73 IsDeterministic]: Start isDeterministic. Operand 518 states and 1094 transitions. [2020-06-22 00:13:07,998 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-06-22 00:13:07,998 INFO L706 BuchiCegarLoop]: Abstraction has 518 states and 1094 transitions. [2020-06-22 00:13:07,999 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 518 states and 1094 transitions. [2020-06-22 00:13:08,005 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 518 to 518. [2020-06-22 00:13:08,006 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 518 states. [2020-06-22 00:13:08,007 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 518 states to 518 states and 1094 transitions. [2020-06-22 00:13:08,007 INFO L729 BuchiCegarLoop]: Abstraction has 518 states and 1094 transitions. [2020-06-22 00:13:08,007 INFO L609 BuchiCegarLoop]: Abstraction has 518 states and 1094 transitions. [2020-06-22 00:13:08,007 INFO L442 BuchiCegarLoop]: ======== Iteration 14============ [2020-06-22 00:13:08,007 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 518 states and 1094 transitions. [2020-06-22 00:13:08,010 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 442 [2020-06-22 00:13:08,010 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-06-22 00:13:08,010 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-06-22 00:13:08,012 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:08,012 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:08,013 INFO L794 eck$LassoCheckResult]: Stem: 14011#ULTIMATE.startENTRY [4266] ULTIMATE.startENTRY-->L444: Formula: (and (= 1 v_~t6_i~0_7) (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~M_E~0_37 2) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 0 v_~t6_pc~0_26) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_6~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= v_~T6_E~0_18 2) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~t6_st~0_24) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t6_pc~0=v_~t6_pc~0_26, ~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~T6_E~0=v_~T6_E~0_18, ~M_E~0=v_~M_E~0_37, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ~T4_E~0=v_~T4_E~0_18, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_4|, ~t6_i~0=v_~t6_i~0_7, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ULTIMATE.start_main_~__retres1~8=v_ULTIMATE.start_main_~__retres1~8_6, ~T2_E~0=v_~T2_E~0_18, ~t6_st~0=v_~t6_st~0_24, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_6~0=v_~E_6~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t6_pc~0, ~t5_i~0, ~t1_pc~0, ~t5_st~0, ~T6_E~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ~T4_E~0, ULTIMATE.start_start_simulation_#t~ret17, ~t6_i~0, ~t2_st~0, ~t2_pc~0, ULTIMATE.start_main_~__retres1~8, ~T2_E~0, ~t6_st~0, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_6~0, ULTIMATE.start_main_#res, ~E_2~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 13661#L444 [2453] L444-->L451-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 13662#L451-1 [3030] L451-1-->L456-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 13747#L456-1 [2574] L456-1-->L461-1: Formula: (and (= v_~t2_st~0_2 0) (= 1 v_~t2_i~0_3)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_2} AuxVars[] AssignedVars[~t2_st~0] 13748#L461-1 [2880] L461-1-->L466-1: Formula: (and (= v_~t3_st~0_3 0) (= v_~t3_i~0_3 1)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_3, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 13663#L466-1 [2457] L466-1-->L471-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 13664#L471-1 [3209] L471-1-->L476-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 13887#L476-1 [2761] L476-1-->L481-1: Formula: (and (= 1 v_~t6_i~0_3) (= v_~t6_st~0_4 0)) InVars {~t6_i~0=v_~t6_i~0_3} OutVars{~t6_st~0=v_~t6_st~0_4, ~t6_i~0=v_~t6_i~0_3} AuxVars[] AssignedVars[~t6_st~0] 13888#L481-1 [3652] L481-1-->L660-1: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 14022#L660-1 [3654] L660-1-->L665-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 13581#L665-1 [3655] L665-1-->L670-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 13582#L670-1 [3658] L670-1-->L675-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 13670#L675-1 [3659] L675-1-->L680-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 13671#L680-1 [3661] L680-1-->L685-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 13896#L685-1 [3663] L685-1-->L690-1: Formula: (< 0 v_~T6_E~0_4) InVars {~T6_E~0=v_~T6_E~0_4} OutVars{~T6_E~0=v_~T6_E~0_4} AuxVars[] AssignedVars[] 13897#L690-1 [3310] L690-1-->L695-1: Formula: (and (= v_~E_1~0_5 0) (= v_~E_1~0_4 1)) InVars {~E_1~0=v_~E_1~0_5} OutVars{~E_1~0=v_~E_1~0_4} AuxVars[] AssignedVars[~E_1~0] 13792#L695-1 [2621] L695-1-->L700-1: Formula: (and (= v_~E_2~0_4 1) (= v_~E_2~0_5 0)) InVars {~E_2~0=v_~E_2~0_5} OutVars{~E_2~0=v_~E_2~0_4} AuxVars[] AssignedVars[~E_2~0] 13793#L700-1 [3180] L700-1-->L705-1: Formula: (and (= v_~E_3~0_5 0) (= v_~E_3~0_4 1)) InVars {~E_3~0=v_~E_3~0_5} OutVars{~E_3~0=v_~E_3~0_4} AuxVars[] AssignedVars[~E_3~0] 13998#L705-1 [3672] L705-1-->L710-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 13731#L710-1 [2525] L710-1-->L715-1: Formula: (and (= v_~E_5~0_3 0) (= v_~E_5~0_2 1)) InVars {~E_5~0=v_~E_5~0_3} OutVars{~E_5~0=v_~E_5~0_2} AuxVars[] AssignedVars[~E_5~0] 13732#L715-1 [3676] L715-1-->L720-1: Formula: (< v_~E_6~0_4 0) InVars {~E_6~0=v_~E_6~0_4} OutVars{~E_6~0=v_~E_6~0_4} AuxVars[] AssignedVars[] 13615#L720-1 [2412] L720-1-->L310: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_7, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_4|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_4|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_7, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_4, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_4, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_2|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_2|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_4|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_4|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_7, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_2|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_4} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 13616#L310 [2597] L310-->L311: Formula: (= v_~m_pc~0_4 1) InVars {~m_pc~0=v_~m_pc~0_4} OutVars{~m_pc~0=v_~m_pc~0_4} AuxVars[] AssignedVars[] 13763#L311 [2732] L311-->L321: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_10 1) (= 1 v_~M_E~0_8)) InVars {~M_E~0=v_~M_E~0_8} OutVars{~M_E~0=v_~M_E~0_8, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_10} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 13761#L321 [4267] L321-->L815: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 13762#L815 [3682] L815-->L815-2: Formula: (and (= v_~m_st~0_5 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_11)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} OutVars{~m_st~0=v_~m_st~0_5, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} AuxVars[] AssignedVars[~m_st~0] 13994#L815-2 [2961] L815-2-->L329: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 13930#L329 [2848] L329-->L330: Formula: (= v_~t1_pc~0_4 1) InVars {~t1_pc~0=v_~t1_pc~0_4} OutVars{~t1_pc~0=v_~t1_pc~0_4} AuxVars[] AssignedVars[] 13931#L330 [3036] L330-->L340: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_10 1) (= v_~E_1~0_7 1)) InVars {~E_1~0=v_~E_1~0_7} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_10, ~E_1~0=v_~E_1~0_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 13928#L340 [4268] L340-->L823: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 13929#L823 [3688] L823-->L823-2: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___0~0_11 0) (= v_~t1_st~0_5 0)) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_11} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_11, ~t1_st~0=v_~t1_st~0_5} AuxVars[] AssignedVars[~t1_st~0] 14080#L823-2 [3235] L823-2-->L348: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_4|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 14064#L348 [3143] L348-->L349: Formula: (= v_~t2_pc~0_4 1) InVars {~t2_pc~0=v_~t2_pc~0_4} OutVars{~t2_pc~0=v_~t2_pc~0_4} AuxVars[] AssignedVars[] 14065#L349 [3267] L349-->L359: Formula: (and (= v_~E_2~0_7 1) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_10 1)) InVars {~E_2~0=v_~E_2~0_7} OutVars{~E_2~0=v_~E_2~0_7, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_10} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 14063#L359 [4269] L359-->L831: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 13738#L831 [3694] L831-->L831-2: Formula: (and (= v_~t2_st~0_5 0) (> v_ULTIMATE.start_activate_threads_~tmp___1~0_11 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_11} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_11, ~t2_st~0=v_~t2_st~0_5} AuxVars[] AssignedVars[~t2_st~0] 13726#L831-2 [2520] L831-2-->L367: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_4|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 13666#L367 [3695] L367-->L367-2: Formula: (> 1 v_~t3_pc~0_5) InVars {~t3_pc~0=v_~t3_pc~0_5} OutVars{~t3_pc~0=v_~t3_pc~0_5} AuxVars[] AssignedVars[] 13644#L367-2 [2438] L367-2-->L378: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 13645#L378 [4270] L378-->L839: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 13665#L839 [2791] L839-->L839-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} AuxVars[] AssignedVars[] 13903#L839-2 [2794] L839-2-->L386: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_7, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 13833#L386 [2675] L386-->L387: Formula: (= v_~t4_pc~0_4 1) InVars {~t4_pc~0=v_~t4_pc~0_4} OutVars{~t4_pc~0=v_~t4_pc~0_4} AuxVars[] AssignedVars[] 13752#L387 [2588] L387-->L397: Formula: (and (= v_~E_4~0_7 1) (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_10 1)) InVars {~E_4~0=v_~E_4~0_7} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_10, ~E_4~0=v_~E_4~0_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 13754#L397 [4271] L397-->L847: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 13832#L847 [3084] L847-->L847-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} AuxVars[] AssignedVars[] 14026#L847-2 [3064] L847-2-->L405: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_4|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 14027#L405 [3708] L405-->L405-2: Formula: (> 1 v_~t5_pc~0_5) InVars {~t5_pc~0=v_~t5_pc~0_5} OutVars{~t5_pc~0=v_~t5_pc~0_5} AuxVars[] AssignedVars[] 13963#L405-2 [2940] L405-2-->L416: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 13962#L416 [4272] L416-->L855: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 14033#L855 [3711] L855-->L855-2: Formula: (and (> v_ULTIMATE.start_activate_threads_~tmp___4~0_11 0) (= v_~t5_st~0_7 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_11} OutVars{~t5_st~0=v_~t5_st~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_11} AuxVars[] AssignedVars[~t5_st~0] 14034#L855-2 [3093] L855-2-->L424: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_4|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 13710#L424 [3714] L424-->L424-2: Formula: (> v_~t6_pc~0_5 1) InVars {~t6_pc~0=v_~t6_pc~0_5} OutVars{~t6_pc~0=v_~t6_pc~0_5} AuxVars[] AssignedVars[] 13711#L424-2 [2503] L424-2-->L435: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 13707#L435 [4273] L435-->L863: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___5~0_49 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_28|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_28|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 13631#L863 [2425] L863-->L863-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___5~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} AuxVars[] AssignedVars[] 13605#L863-2 [3720] L863-2-->L733-1: Formula: (< v_~M_E~0_15 1) InVars {~M_E~0=v_~M_E~0_15} OutVars{~M_E~0=v_~M_E~0_15} AuxVars[] AssignedVars[] 13606#L733-1 [3722] L733-1-->L738-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 13996#L738-1 [3723] L738-1-->L743-1: Formula: (< 1 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 13729#L743-1 [3726] L743-1-->L748-1: Formula: (< 1 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 13730#L748-1 [3728] L748-1-->L753-1: Formula: (> v_~T4_E~0_10 1) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 13610#L753-1 [3729] L753-1-->L758-1: Formula: (< 1 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 13611#L758-1 [3732] L758-1-->L763-1: Formula: (< v_~T6_E~0_10 1) InVars {~T6_E~0=v_~T6_E~0_10} OutVars{~T6_E~0=v_~T6_E~0_10} AuxVars[] AssignedVars[] 13682#L763-1 [2475] L763-1-->L768-1: Formula: (and (= v_~E_1~0_12 2) (= 1 v_~E_1~0_13)) InVars {~E_1~0=v_~E_1~0_13} OutVars{~E_1~0=v_~E_1~0_12} AuxVars[] AssignedVars[~E_1~0] 13683#L768-1 [3736] L768-1-->L773-1: Formula: (< 1 v_~E_2~0_14) InVars {~E_2~0=v_~E_2~0_14} OutVars{~E_2~0=v_~E_2~0_14} AuxVars[] AssignedVars[] 13892#L773-1 [2767] L773-1-->L778-1: Formula: (and (= 1 v_~E_3~0_13) (= v_~E_3~0_12 2)) InVars {~E_3~0=v_~E_3~0_13} OutVars{~E_3~0=v_~E_3~0_12} AuxVars[] AssignedVars[~E_3~0] 13893#L778-1 [3740] L778-1-->L783-1: Formula: (< 1 v_~E_4~0_14) InVars {~E_4~0=v_~E_4~0_14} OutVars{~E_4~0=v_~E_4~0_14} AuxVars[] AssignedVars[] 13785#L783-1 [3742] L783-1-->L788-1: Formula: (> 1 v_~E_5~0_14) InVars {~E_5~0=v_~E_5~0_14} OutVars{~E_5~0=v_~E_5~0_14} AuxVars[] AssignedVars[] 13786#L788-1 [3743] L788-1-->L1014-1: Formula: (> 1 v_~E_6~0_14) InVars {~E_6~0=v_~E_6~0_14} OutVars{~E_6~0=v_~E_6~0_14} AuxVars[] AssignedVars[] 13623#L1014-1 [2020-06-22 00:13:08,014 INFO L796 eck$LassoCheckResult]: Loop: 13623#L1014-1 [4274] L1014-1-->L635: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp_ndt_7~0=v_ULTIMATE.start_eval_~tmp_ndt_7~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp_ndt_7~0] 13585#L635 [4275] L635-->L494: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_37} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 13958#L494 [2876] L494-->L531: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21 1) (= v_~m_st~0_8 0)) InVars {~m_st~0=v_~m_st~0_8} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21, ~m_st~0=v_~m_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 13654#L531 [4276] L531-->L546: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 13880#L546 [4278] L546-->L660-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 14023#L660-2 [3747] L660-2-->L660-4: Formula: (> v_~M_E~0_30 0) InVars {~M_E~0=v_~M_E~0_30} OutVars{~M_E~0=v_~M_E~0_30} AuxVars[] AssignedVars[] 14024#L660-4 [3058] L660-4-->L665-3: Formula: (and (= v_~T1_E~0_11 1) (= v_~T1_E~0_12 0)) InVars {~T1_E~0=v_~T1_E~0_12} OutVars{~T1_E~0=v_~T1_E~0_11} AuxVars[] AssignedVars[~T1_E~0] 13597#L665-3 [3756] L665-3-->L670-3: Formula: (< 0 v_~T2_E~0_13) InVars {~T2_E~0=v_~T2_E~0_13} OutVars{~T2_E~0=v_~T2_E~0_13} AuxVars[] AssignedVars[] 13598#L670-3 [3762] L670-3-->L675-3: Formula: (< 0 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 13672#L675-3 [3768] L675-3-->L680-3: Formula: (> v_~T4_E~0_13 0) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 13673#L680-3 [3776] L680-3-->L685-3: Formula: (< 0 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 13899#L685-3 [3785] L685-3-->L690-3: Formula: (> v_~T6_E~0_13 0) InVars {~T6_E~0=v_~T6_E~0_13} OutVars{~T6_E~0=v_~T6_E~0_13} AuxVars[] AssignedVars[] 13900#L690-3 [3795] L690-3-->L695-3: Formula: (< 0 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 13778#L695-3 [2609] L695-3-->L700-3: Formula: (and (= 0 v_~E_2~0_30) (= v_~E_2~0_29 1)) InVars {~E_2~0=v_~E_2~0_30} OutVars{~E_2~0=v_~E_2~0_29} AuxVars[] AssignedVars[~E_2~0] 13779#L700-3 [3155] L700-3-->L705-3: Formula: (and (= v_~E_3~0_29 1) (= 0 v_~E_3~0_30)) InVars {~E_3~0=v_~E_3~0_30} OutVars{~E_3~0=v_~E_3~0_29} AuxVars[] AssignedVars[~E_3~0] 13841#L705-3 [2688] L705-3-->L710-3: Formula: (and (= v_~E_4~0_29 1) (= 0 v_~E_4~0_30)) InVars {~E_4~0=v_~E_4~0_30} OutVars{~E_4~0=v_~E_4~0_29} AuxVars[] AssignedVars[~E_4~0] 13723#L710-3 [2515] L710-3-->L715-3: Formula: (and (= 0 v_~E_5~0_30) (= v_~E_5~0_29 1)) InVars {~E_5~0=v_~E_5~0_30} OutVars{~E_5~0=v_~E_5~0_29} AuxVars[] AssignedVars[~E_5~0] 13724#L715-3 [3048] L715-3-->L720-3: Formula: (and (= v_~E_6~0_29 1) (= 0 v_~E_6~0_30)) InVars {~E_6~0=v_~E_6~0_30} OutVars{~E_6~0=v_~E_6~0_29} AuxVars[] AssignedVars[~E_6~0] 13586#L720-3 [2388] L720-3-->L310-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_43, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_43, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_25|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_25|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_25|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_43, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_43, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_43, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_25|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_25|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_25|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_25|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_43, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_25|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_43, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_43} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 13587#L310-21 [2779] L310-21-->L311-7: Formula: (= v_~m_pc~0_23 1) InVars {~m_pc~0=v_~m_pc~0_23} OutVars{~m_pc~0=v_~m_pc~0_23} AuxVars[] AssignedVars[] 13864#L311-7 [2720] L311-7-->L321-7: Formula: (and (= v_~M_E~0_31 1) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_46 1)) InVars {~M_E~0=v_~M_E~0_31} OutVars{~M_E~0=v_~M_E~0_31, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_46} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 13865#L321-7 [4303] L321-7-->L815-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 13826#L815-21 [3897] L815-21-->L815-23: Formula: (and (> 0 v_ULTIMATE.start_activate_threads_~tmp~1_47) (= v_~m_st~0_20 0)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_47} OutVars{~m_st~0=v_~m_st~0_20, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_47} AuxVars[] AssignedVars[~m_st~0] 13807#L815-23 [2638] L815-23-->L329-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 13808#L329-21 [3038] L329-21-->L330-7: Formula: (= v_~t1_pc~0_23 1) InVars {~t1_pc~0=v_~t1_pc~0_23} OutVars{~t1_pc~0=v_~t1_pc~0_23} AuxVars[] AssignedVars[] 14003#L330-7 [2981] L330-7-->L340-7: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_52 1) (= 1 v_~E_1~0_32)) InVars {~E_1~0=v_~E_1~0_32} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_52, ~E_1~0=v_~E_1~0_32} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 13918#L340-7 [4310] L340-7-->L823-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 13919#L823-21 [2931] L823-21-->L823-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} AuxVars[] AssignedVars[] 13978#L823-23 [2934] L823-23-->L348-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_25|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 13980#L348-21 [3306] L348-21-->L349-7: Formula: (= 1 v_~t2_pc~0_23) InVars {~t2_pc~0=v_~t2_pc~0_23} OutVars{~t2_pc~0=v_~t2_pc~0_23} AuxVars[] AssignedVars[] 14084#L349-7 [3255] L349-7-->L359-7: Formula: (and (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_52 1) (= 1 v_~E_2~0_32)) InVars {~E_2~0=v_~E_2~0_32} OutVars{~E_2~0=v_~E_2~0_32, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_52} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 14060#L359-7 [4317] L359-7-->L831-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 13701#L831-21 [2490] L831-21-->L831-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} AuxVars[] AssignedVars[] 13702#L831-23 [3197] L831-23-->L367-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_25|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 13612#L367-21 [3995] L367-21-->L367-23: Formula: (> v_~t3_pc~0_24 1) InVars {~t3_pc~0=v_~t3_pc~0_24} OutVars{~t3_pc~0=v_~t3_pc~0_24} AuxVars[] AssignedVars[] 13579#L367-23 [2385] L367-23-->L378-7: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 13580#L378-7 [4324] L378-7-->L839-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 13636#L839-21 [4023] L839-21-->L839-23: Formula: (and (= v_~t3_st~0_21 0) (> v_ULTIMATE.start_activate_threads_~tmp___2~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} OutVars{~t3_st~0=v_~t3_st~0_21, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} AuxVars[] AssignedVars[~t3_st~0] 13857#L839-23 [2722] L839-23-->L386-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_49, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 13787#L386-21 [4037] L386-21-->L386-23: Formula: (< 1 v_~t4_pc~0_24) InVars {~t4_pc~0=v_~t4_pc~0_24} OutVars{~t4_pc~0=v_~t4_pc~0_24} AuxVars[] AssignedVars[] 13788#L386-23 [2623] L386-23-->L397-7: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 13794#L397-7 [4331] L397-7-->L847-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 13823#L847-21 [4065] L847-21-->L847-23: Formula: (and (= v_~t4_st~0_22 0) (< v_ULTIMATE.start_activate_threads_~tmp___3~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47, ~t4_st~0=v_~t4_st~0_22} AuxVars[] AssignedVars[~t4_st~0] 14005#L847-23 [2983] L847-23-->L405-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_25|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 13969#L405-21 [2911] L405-21-->L406-7: Formula: (= v_~t5_pc~0_23 1) InVars {~t5_pc~0=v_~t5_pc~0_23} OutVars{~t5_pc~0=v_~t5_pc~0_23} AuxVars[] AssignedVars[] 13953#L406-7 [2874] L406-7-->L416-7: Formula: (and (= 1 v_~E_5~0_32) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_52 1)) InVars {~E_5~0=v_~E_5~0_32} OutVars{~E_5~0=v_~E_5~0_32, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_52} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 13955#L416-7 [4338] L416-7-->L855-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 13974#L855-21 [3251] L855-21-->L855-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} AuxVars[] AssignedVars[] 14083#L855-23 [3257] L855-23-->L424-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_25|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 14070#L424-21 [3173] L424-21-->L425-7: Formula: (= 1 v_~t6_pc~0_23) InVars {~t6_pc~0=v_~t6_pc~0_23} OutVars{~t6_pc~0=v_~t6_pc~0_23} AuxVars[] AssignedVars[] 14052#L425-7 [3114] L425-7-->L435-7: Formula: (and (= 1 v_~E_6~0_32) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_52 1)) InVars {~E_6~0=v_~E_6~0_32} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_52, ~E_6~0=v_~E_6~0_32} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 13696#L435-7 [4340] L435-7-->L863-21: Formula: (and (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___5~0_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_35|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_41|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 13697#L863-21 [4135] L863-21-->L863-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___5~0_47 0) (= v_~t6_st~0_22 0)) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} OutVars{~t6_st~0=v_~t6_st~0_22, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} AuxVars[] AssignedVars[~t6_st~0] 13739#L863-23 [4137] L863-23-->L733-3: Formula: (< v_~M_E~0_35 1) InVars {~M_E~0=v_~M_E~0_35} OutVars{~M_E~0=v_~M_E~0_35} AuxVars[] AssignedVars[] 13740#L733-3 [3184] L733-3-->L738-3: Formula: (and (= v_~T1_E~0_15 1) (= v_~T1_E~0_14 2)) InVars {~T1_E~0=v_~T1_E~0_15} OutVars{~T1_E~0=v_~T1_E~0_14} AuxVars[] AssignedVars[~T1_E~0] 13999#L738-3 [4142] L738-3-->L743-3: Formula: (< 1 v_~T2_E~0_16) InVars {~T2_E~0=v_~T2_E~0_16} OutVars{~T2_E~0=v_~T2_E~0_16} AuxVars[] AssignedVars[] 13719#L743-3 [4143] L743-3-->L748-3: Formula: (< 1 v_~T3_E~0_16) InVars {~T3_E~0=v_~T3_E~0_16} OutVars{~T3_E~0=v_~T3_E~0_16} AuxVars[] AssignedVars[] 13720#L748-3 [4145] L748-3-->L753-3: Formula: (> v_~T4_E~0_16 1) InVars {~T4_E~0=v_~T4_E~0_16} OutVars{~T4_E~0=v_~T4_E~0_16} AuxVars[] AssignedVars[] 13577#L753-3 [4148] L753-3-->L758-3: Formula: (< 1 v_~T5_E~0_16) InVars {~T5_E~0=v_~T5_E~0_16} OutVars{~T5_E~0=v_~T5_E~0_16} AuxVars[] AssignedVars[] 13578#L758-3 [4149] L758-3-->L763-3: Formula: (> v_~T6_E~0_16 1) InVars {~T6_E~0=v_~T6_E~0_16} OutVars{~T6_E~0=v_~T6_E~0_16} AuxVars[] AssignedVars[] 13668#L763-3 [4151] L763-3-->L768-3: Formula: (< 1 v_~E_1~0_36) InVars {~E_1~0=v_~E_1~0_36} OutVars{~E_1~0=v_~E_1~0_36} AuxVars[] AssignedVars[] 13669#L768-3 [3219] L768-3-->L773-3: Formula: (and (= 1 v_~E_2~0_35) (= v_~E_2~0_34 2)) InVars {~E_2~0=v_~E_2~0_35} OutVars{~E_2~0=v_~E_2~0_34} AuxVars[] AssignedVars[~E_2~0] 13894#L773-3 [2775] L773-3-->L778-3: Formula: (and (= 1 v_~E_3~0_35) (= v_~E_3~0_34 2)) InVars {~E_3~0=v_~E_3~0_35} OutVars{~E_3~0=v_~E_3~0_34} AuxVars[] AssignedVars[~E_3~0] 13895#L778-3 [3308] L778-3-->L783-3: Formula: (and (= 1 v_~E_4~0_35) (= v_~E_4~0_34 2)) InVars {~E_4~0=v_~E_4~0_35} OutVars{~E_4~0=v_~E_4~0_34} AuxVars[] AssignedVars[~E_4~0] 13790#L783-3 [4160] L783-3-->L788-3: Formula: (< 1 v_~E_5~0_36) InVars {~E_5~0=v_~E_5~0_36} OutVars{~E_5~0=v_~E_5~0_36} AuxVars[] AssignedVars[] 13791#L788-3 [4161] L788-3-->L793-3: Formula: (> 1 v_~E_6~0_36) InVars {~E_6~0=v_~E_6~0_36} OutVars{~E_6~0=v_~E_6~0_36} AuxVars[] AssignedVars[] 13997#L793-3 [2966] L793-3-->L494-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_30} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 13959#L494-1 [2878] L494-1-->L531-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33 1) (= 0 v_~m_st~0_21)) InVars {~m_st~0=v_~m_st~0_21} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33, ~m_st~0=v_~m_st~0_21} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 13656#L531-1 [4341] L531-1-->L1033: Formula: (and (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp~3] 13881#L1033 [4169] L1033-->L1033-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_6) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} AuxVars[] AssignedVars[] 13626#L1033-1 [2919] L1033-1-->L494-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_3|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_6, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_exists_runnable_thread_~__retres1~7, ULTIMATE.start_stop_simulation_#res] 13960#L494-2 [2882] L494-2-->L531-2: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9 1) (= v_~m_st~0_6 0)) InVars {~m_st~0=v_~m_st~0_6} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9, ~m_st~0=v_~m_st~0_6} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 13660#L531-2 [4343] L531-2-->L988: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 13886#L988 [3240] L988-->L995: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 13622#L995 [4354] L995-->L1014-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_6|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_#t~ret17, ULTIMATE.start_stop_simulation_#res] 13623#L1014-1 [2020-06-22 00:13:08,015 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:08,015 INFO L82 PathProgramCache]: Analyzing trace with hash -9237110, now seen corresponding path program 1 times [2020-06-22 00:13:08,015 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:08,015 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:08,016 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:08,016 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:08,016 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:08,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:08,046 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:08,046 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:08,046 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-06-22 00:13:08,047 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-06-22 00:13:08,047 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:08,047 INFO L82 PathProgramCache]: Analyzing trace with hash -1215873223, now seen corresponding path program 1 times [2020-06-22 00:13:08,048 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:08,048 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:08,048 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:08,064 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:08,064 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:08,068 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:08,093 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:08,094 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:08,094 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2020-06-22 00:13:08,094 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-06-22 00:13:08,095 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-06-22 00:13:08,095 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-06-22 00:13:08,095 INFO L87 Difference]: Start difference. First operand 518 states and 1094 transitions. cyclomatic complexity: 577 Second operand 3 states. [2020-06-22 00:13:08,660 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-06-22 00:13:08,661 INFO L93 Difference]: Finished difference Result 552 states and 1134 transitions. [2020-06-22 00:13:08,661 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-06-22 00:13:08,661 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 552 states and 1134 transitions. [2020-06-22 00:13:08,664 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 476 [2020-06-22 00:13:08,668 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 552 states to 552 states and 1134 transitions. [2020-06-22 00:13:08,668 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 552 [2020-06-22 00:13:08,668 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 552 [2020-06-22 00:13:08,668 INFO L73 IsDeterministic]: Start isDeterministic. Operand 552 states and 1134 transitions. [2020-06-22 00:13:08,669 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-06-22 00:13:08,669 INFO L706 BuchiCegarLoop]: Abstraction has 552 states and 1134 transitions. [2020-06-22 00:13:08,670 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 552 states and 1134 transitions. [2020-06-22 00:13:08,676 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 552 to 518. [2020-06-22 00:13:08,676 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 518 states. [2020-06-22 00:13:08,678 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 518 states to 518 states and 1068 transitions. [2020-06-22 00:13:08,678 INFO L729 BuchiCegarLoop]: Abstraction has 518 states and 1068 transitions. [2020-06-22 00:13:08,678 INFO L609 BuchiCegarLoop]: Abstraction has 518 states and 1068 transitions. [2020-06-22 00:13:08,678 INFO L442 BuchiCegarLoop]: ======== Iteration 15============ [2020-06-22 00:13:08,678 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 518 states and 1068 transitions. [2020-06-22 00:13:08,680 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 442 [2020-06-22 00:13:08,680 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-06-22 00:13:08,680 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-06-22 00:13:08,681 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:08,682 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:08,683 INFO L794 eck$LassoCheckResult]: Stem: 15089#ULTIMATE.startENTRY [4266] ULTIMATE.startENTRY-->L444: Formula: (and (= 1 v_~t6_i~0_7) (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~M_E~0_37 2) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 0 v_~t6_pc~0_26) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_6~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= v_~T6_E~0_18 2) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~t6_st~0_24) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t6_pc~0=v_~t6_pc~0_26, ~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~T6_E~0=v_~T6_E~0_18, ~M_E~0=v_~M_E~0_37, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ~T4_E~0=v_~T4_E~0_18, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_4|, ~t6_i~0=v_~t6_i~0_7, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ULTIMATE.start_main_~__retres1~8=v_ULTIMATE.start_main_~__retres1~8_6, ~T2_E~0=v_~T2_E~0_18, ~t6_st~0=v_~t6_st~0_24, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_6~0=v_~E_6~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t6_pc~0, ~t5_i~0, ~t1_pc~0, ~t5_st~0, ~T6_E~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ~T4_E~0, ULTIMATE.start_start_simulation_#t~ret17, ~t6_i~0, ~t2_st~0, ~t2_pc~0, ULTIMATE.start_main_~__retres1~8, ~T2_E~0, ~t6_st~0, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_6~0, ULTIMATE.start_main_#res, ~E_2~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 14739#L444 [2453] L444-->L451-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 14740#L451-1 [3030] L451-1-->L456-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 14825#L456-1 [2574] L456-1-->L461-1: Formula: (and (= v_~t2_st~0_2 0) (= 1 v_~t2_i~0_3)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_2} AuxVars[] AssignedVars[~t2_st~0] 14826#L461-1 [2880] L461-1-->L466-1: Formula: (and (= v_~t3_st~0_3 0) (= v_~t3_i~0_3 1)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_3, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 14741#L466-1 [2457] L466-1-->L471-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 14742#L471-1 [3209] L471-1-->L476-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 14965#L476-1 [2761] L476-1-->L481-1: Formula: (and (= 1 v_~t6_i~0_3) (= v_~t6_st~0_4 0)) InVars {~t6_i~0=v_~t6_i~0_3} OutVars{~t6_st~0=v_~t6_st~0_4, ~t6_i~0=v_~t6_i~0_3} AuxVars[] AssignedVars[~t6_st~0] 14966#L481-1 [3652] L481-1-->L660-1: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 15100#L660-1 [3654] L660-1-->L665-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 14659#L665-1 [3655] L665-1-->L670-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 14660#L670-1 [3658] L670-1-->L675-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 14748#L675-1 [3659] L675-1-->L680-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 14749#L680-1 [3661] L680-1-->L685-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 14974#L685-1 [3663] L685-1-->L690-1: Formula: (< 0 v_~T6_E~0_4) InVars {~T6_E~0=v_~T6_E~0_4} OutVars{~T6_E~0=v_~T6_E~0_4} AuxVars[] AssignedVars[] 14975#L690-1 [3665] L690-1-->L695-1: Formula: (> v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 14870#L695-1 [2621] L695-1-->L700-1: Formula: (and (= v_~E_2~0_4 1) (= v_~E_2~0_5 0)) InVars {~E_2~0=v_~E_2~0_5} OutVars{~E_2~0=v_~E_2~0_4} AuxVars[] AssignedVars[~E_2~0] 14871#L700-1 [3180] L700-1-->L705-1: Formula: (and (= v_~E_3~0_5 0) (= v_~E_3~0_4 1)) InVars {~E_3~0=v_~E_3~0_5} OutVars{~E_3~0=v_~E_3~0_4} AuxVars[] AssignedVars[~E_3~0] 15076#L705-1 [3672] L705-1-->L710-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 14809#L710-1 [2525] L710-1-->L715-1: Formula: (and (= v_~E_5~0_3 0) (= v_~E_5~0_2 1)) InVars {~E_5~0=v_~E_5~0_3} OutVars{~E_5~0=v_~E_5~0_2} AuxVars[] AssignedVars[~E_5~0] 14810#L715-1 [3676] L715-1-->L720-1: Formula: (< v_~E_6~0_4 0) InVars {~E_6~0=v_~E_6~0_4} OutVars{~E_6~0=v_~E_6~0_4} AuxVars[] AssignedVars[] 14693#L720-1 [2412] L720-1-->L310: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_7, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_4|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_4|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_7, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_4, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_4, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_2|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_2|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_4|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_4|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_7, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_2|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_4} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 14694#L310 [2597] L310-->L311: Formula: (= v_~m_pc~0_4 1) InVars {~m_pc~0=v_~m_pc~0_4} OutVars{~m_pc~0=v_~m_pc~0_4} AuxVars[] AssignedVars[] 14841#L311 [2732] L311-->L321: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_10 1) (= 1 v_~M_E~0_8)) InVars {~M_E~0=v_~M_E~0_8} OutVars{~M_E~0=v_~M_E~0_8, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_10} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 14839#L321 [4267] L321-->L815: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 14840#L815 [3682] L815-->L815-2: Formula: (and (= v_~m_st~0_5 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_11)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} OutVars{~m_st~0=v_~m_st~0_5, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} AuxVars[] AssignedVars[~m_st~0] 15072#L815-2 [2961] L815-2-->L329: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 15008#L329 [3684] L329-->L329-2: Formula: (> v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 15010#L329-2 [2861] L329-2-->L340: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 15006#L340 [4268] L340-->L823: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 15007#L823 [3688] L823-->L823-2: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___0~0_11 0) (= v_~t1_st~0_5 0)) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_11} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_11, ~t1_st~0=v_~t1_st~0_5} AuxVars[] AssignedVars[~t1_st~0] 15158#L823-2 [3235] L823-2-->L348: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_4|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 15142#L348 [3143] L348-->L349: Formula: (= v_~t2_pc~0_4 1) InVars {~t2_pc~0=v_~t2_pc~0_4} OutVars{~t2_pc~0=v_~t2_pc~0_4} AuxVars[] AssignedVars[] 15143#L349 [3267] L349-->L359: Formula: (and (= v_~E_2~0_7 1) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_10 1)) InVars {~E_2~0=v_~E_2~0_7} OutVars{~E_2~0=v_~E_2~0_7, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_10} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 15141#L359 [4269] L359-->L831: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 14816#L831 [3694] L831-->L831-2: Formula: (and (= v_~t2_st~0_5 0) (> v_ULTIMATE.start_activate_threads_~tmp___1~0_11 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_11} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_11, ~t2_st~0=v_~t2_st~0_5} AuxVars[] AssignedVars[~t2_st~0] 14804#L831-2 [2520] L831-2-->L367: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_4|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 14744#L367 [3695] L367-->L367-2: Formula: (> 1 v_~t3_pc~0_5) InVars {~t3_pc~0=v_~t3_pc~0_5} OutVars{~t3_pc~0=v_~t3_pc~0_5} AuxVars[] AssignedVars[] 14722#L367-2 [2438] L367-2-->L378: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 14723#L378 [4270] L378-->L839: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 14743#L839 [2791] L839-->L839-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} AuxVars[] AssignedVars[] 14981#L839-2 [2794] L839-2-->L386: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_7, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 14911#L386 [2675] L386-->L387: Formula: (= v_~t4_pc~0_4 1) InVars {~t4_pc~0=v_~t4_pc~0_4} OutVars{~t4_pc~0=v_~t4_pc~0_4} AuxVars[] AssignedVars[] 14830#L387 [2588] L387-->L397: Formula: (and (= v_~E_4~0_7 1) (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_10 1)) InVars {~E_4~0=v_~E_4~0_7} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_10, ~E_4~0=v_~E_4~0_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 14832#L397 [4271] L397-->L847: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 14910#L847 [3084] L847-->L847-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} AuxVars[] AssignedVars[] 15104#L847-2 [3064] L847-2-->L405: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_4|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 15105#L405 [3708] L405-->L405-2: Formula: (> 1 v_~t5_pc~0_5) InVars {~t5_pc~0=v_~t5_pc~0_5} OutVars{~t5_pc~0=v_~t5_pc~0_5} AuxVars[] AssignedVars[] 15041#L405-2 [2940] L405-2-->L416: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 15040#L416 [4272] L416-->L855: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 15111#L855 [3711] L855-->L855-2: Formula: (and (> v_ULTIMATE.start_activate_threads_~tmp___4~0_11 0) (= v_~t5_st~0_7 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_11} OutVars{~t5_st~0=v_~t5_st~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_11} AuxVars[] AssignedVars[~t5_st~0] 15112#L855-2 [3093] L855-2-->L424: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_4|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 14788#L424 [3714] L424-->L424-2: Formula: (> v_~t6_pc~0_5 1) InVars {~t6_pc~0=v_~t6_pc~0_5} OutVars{~t6_pc~0=v_~t6_pc~0_5} AuxVars[] AssignedVars[] 14789#L424-2 [2503] L424-2-->L435: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 14787#L435 [4273] L435-->L863: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___5~0_49 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_28|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_28|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 14709#L863 [2425] L863-->L863-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___5~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} AuxVars[] AssignedVars[] 14683#L863-2 [3720] L863-2-->L733-1: Formula: (< v_~M_E~0_15 1) InVars {~M_E~0=v_~M_E~0_15} OutVars{~M_E~0=v_~M_E~0_15} AuxVars[] AssignedVars[] 14684#L733-1 [3722] L733-1-->L738-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 15074#L738-1 [3723] L738-1-->L743-1: Formula: (< 1 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 14807#L743-1 [3726] L743-1-->L748-1: Formula: (< 1 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 14808#L748-1 [3728] L748-1-->L753-1: Formula: (> v_~T4_E~0_10 1) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 14688#L753-1 [3729] L753-1-->L758-1: Formula: (< 1 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 14689#L758-1 [3732] L758-1-->L763-1: Formula: (< v_~T6_E~0_10 1) InVars {~T6_E~0=v_~T6_E~0_10} OutVars{~T6_E~0=v_~T6_E~0_10} AuxVars[] AssignedVars[] 14760#L763-1 [3733] L763-1-->L768-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 14761#L768-1 [3736] L768-1-->L773-1: Formula: (< 1 v_~E_2~0_14) InVars {~E_2~0=v_~E_2~0_14} OutVars{~E_2~0=v_~E_2~0_14} AuxVars[] AssignedVars[] 14970#L773-1 [2767] L773-1-->L778-1: Formula: (and (= 1 v_~E_3~0_13) (= v_~E_3~0_12 2)) InVars {~E_3~0=v_~E_3~0_13} OutVars{~E_3~0=v_~E_3~0_12} AuxVars[] AssignedVars[~E_3~0] 14971#L778-1 [3740] L778-1-->L783-1: Formula: (< 1 v_~E_4~0_14) InVars {~E_4~0=v_~E_4~0_14} OutVars{~E_4~0=v_~E_4~0_14} AuxVars[] AssignedVars[] 14863#L783-1 [3742] L783-1-->L788-1: Formula: (> 1 v_~E_5~0_14) InVars {~E_5~0=v_~E_5~0_14} OutVars{~E_5~0=v_~E_5~0_14} AuxVars[] AssignedVars[] 14864#L788-1 [3743] L788-1-->L1014-1: Formula: (> 1 v_~E_6~0_14) InVars {~E_6~0=v_~E_6~0_14} OutVars{~E_6~0=v_~E_6~0_14} AuxVars[] AssignedVars[] 14701#L1014-1 [2020-06-22 00:13:08,684 INFO L796 eck$LassoCheckResult]: Loop: 14701#L1014-1 [4274] L1014-1-->L635: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp_ndt_7~0=v_ULTIMATE.start_eval_~tmp_ndt_7~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp_ndt_7~0] 14663#L635 [4275] L635-->L494: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_37} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 15036#L494 [2876] L494-->L531: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21 1) (= v_~m_st~0_8 0)) InVars {~m_st~0=v_~m_st~0_8} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21, ~m_st~0=v_~m_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 14732#L531 [4276] L531-->L546: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 14958#L546 [4278] L546-->L660-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 15101#L660-2 [3747] L660-2-->L660-4: Formula: (> v_~M_E~0_30 0) InVars {~M_E~0=v_~M_E~0_30} OutVars{~M_E~0=v_~M_E~0_30} AuxVars[] AssignedVars[] 15102#L660-4 [3058] L660-4-->L665-3: Formula: (and (= v_~T1_E~0_11 1) (= v_~T1_E~0_12 0)) InVars {~T1_E~0=v_~T1_E~0_12} OutVars{~T1_E~0=v_~T1_E~0_11} AuxVars[] AssignedVars[~T1_E~0] 14675#L665-3 [3756] L665-3-->L670-3: Formula: (< 0 v_~T2_E~0_13) InVars {~T2_E~0=v_~T2_E~0_13} OutVars{~T2_E~0=v_~T2_E~0_13} AuxVars[] AssignedVars[] 14676#L670-3 [3762] L670-3-->L675-3: Formula: (< 0 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 14750#L675-3 [3768] L675-3-->L680-3: Formula: (> v_~T4_E~0_13 0) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 14751#L680-3 [3776] L680-3-->L685-3: Formula: (< 0 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 14977#L685-3 [3785] L685-3-->L690-3: Formula: (> v_~T6_E~0_13 0) InVars {~T6_E~0=v_~T6_E~0_13} OutVars{~T6_E~0=v_~T6_E~0_13} AuxVars[] AssignedVars[] 14978#L690-3 [3795] L690-3-->L695-3: Formula: (< 0 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 14856#L695-3 [2609] L695-3-->L700-3: Formula: (and (= 0 v_~E_2~0_30) (= v_~E_2~0_29 1)) InVars {~E_2~0=v_~E_2~0_30} OutVars{~E_2~0=v_~E_2~0_29} AuxVars[] AssignedVars[~E_2~0] 14857#L700-3 [3155] L700-3-->L705-3: Formula: (and (= v_~E_3~0_29 1) (= 0 v_~E_3~0_30)) InVars {~E_3~0=v_~E_3~0_30} OutVars{~E_3~0=v_~E_3~0_29} AuxVars[] AssignedVars[~E_3~0] 14919#L705-3 [2688] L705-3-->L710-3: Formula: (and (= v_~E_4~0_29 1) (= 0 v_~E_4~0_30)) InVars {~E_4~0=v_~E_4~0_30} OutVars{~E_4~0=v_~E_4~0_29} AuxVars[] AssignedVars[~E_4~0] 14801#L710-3 [2515] L710-3-->L715-3: Formula: (and (= 0 v_~E_5~0_30) (= v_~E_5~0_29 1)) InVars {~E_5~0=v_~E_5~0_30} OutVars{~E_5~0=v_~E_5~0_29} AuxVars[] AssignedVars[~E_5~0] 14802#L715-3 [3048] L715-3-->L720-3: Formula: (and (= v_~E_6~0_29 1) (= 0 v_~E_6~0_30)) InVars {~E_6~0=v_~E_6~0_30} OutVars{~E_6~0=v_~E_6~0_29} AuxVars[] AssignedVars[~E_6~0] 14664#L720-3 [2388] L720-3-->L310-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_43, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_43, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_25|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_25|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_25|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_43, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_43, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_43, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_25|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_25|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_25|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_25|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_43, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_25|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_43, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_43} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 14665#L310-21 [3869] L310-21-->L310-23: Formula: (> v_~m_pc~0_24 1) InVars {~m_pc~0=v_~m_pc~0_24} OutVars{~m_pc~0=v_~m_pc~0_24} AuxVars[] AssignedVars[] 14944#L310-23 [2785] L310-23-->L321-7: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_47 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_47} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 14943#L321-7 [4303] L321-7-->L815-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 14904#L815-21 [3897] L815-21-->L815-23: Formula: (and (> 0 v_ULTIMATE.start_activate_threads_~tmp~1_47) (= v_~m_st~0_20 0)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_47} OutVars{~m_st~0=v_~m_st~0_20, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_47} AuxVars[] AssignedVars[~m_st~0] 14885#L815-23 [2638] L815-23-->L329-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 14886#L329-21 [3911] L329-21-->L329-23: Formula: (< v_~t1_pc~0_24 1) InVars {~t1_pc~0=v_~t1_pc~0_24} OutVars{~t1_pc~0=v_~t1_pc~0_24} AuxVars[] AssignedVars[] 15082#L329-23 [3052] L329-23-->L340-7: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 14996#L340-7 [4310] L340-7-->L823-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 14997#L823-21 [2931] L823-21-->L823-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} AuxVars[] AssignedVars[] 15056#L823-23 [2934] L823-23-->L348-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_25|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 15058#L348-21 [3306] L348-21-->L349-7: Formula: (= 1 v_~t2_pc~0_23) InVars {~t2_pc~0=v_~t2_pc~0_23} OutVars{~t2_pc~0=v_~t2_pc~0_23} AuxVars[] AssignedVars[] 15162#L349-7 [3255] L349-7-->L359-7: Formula: (and (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_52 1) (= 1 v_~E_2~0_32)) InVars {~E_2~0=v_~E_2~0_32} OutVars{~E_2~0=v_~E_2~0_32, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_52} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 15138#L359-7 [4317] L359-7-->L831-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 14779#L831-21 [2490] L831-21-->L831-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} AuxVars[] AssignedVars[] 14780#L831-23 [3197] L831-23-->L367-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_25|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 14690#L367-21 [3995] L367-21-->L367-23: Formula: (> v_~t3_pc~0_24 1) InVars {~t3_pc~0=v_~t3_pc~0_24} OutVars{~t3_pc~0=v_~t3_pc~0_24} AuxVars[] AssignedVars[] 14657#L367-23 [2385] L367-23-->L378-7: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 14658#L378-7 [4324] L378-7-->L839-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 14714#L839-21 [4023] L839-21-->L839-23: Formula: (and (= v_~t3_st~0_21 0) (> v_ULTIMATE.start_activate_threads_~tmp___2~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} OutVars{~t3_st~0=v_~t3_st~0_21, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} AuxVars[] AssignedVars[~t3_st~0] 14935#L839-23 [2722] L839-23-->L386-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_49, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 14865#L386-21 [4037] L386-21-->L386-23: Formula: (< 1 v_~t4_pc~0_24) InVars {~t4_pc~0=v_~t4_pc~0_24} OutVars{~t4_pc~0=v_~t4_pc~0_24} AuxVars[] AssignedVars[] 14866#L386-23 [2623] L386-23-->L397-7: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 14872#L397-7 [4331] L397-7-->L847-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 14901#L847-21 [4065] L847-21-->L847-23: Formula: (and (= v_~t4_st~0_22 0) (< v_ULTIMATE.start_activate_threads_~tmp___3~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47, ~t4_st~0=v_~t4_st~0_22} AuxVars[] AssignedVars[~t4_st~0] 15083#L847-23 [2983] L847-23-->L405-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_25|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 15047#L405-21 [2911] L405-21-->L406-7: Formula: (= v_~t5_pc~0_23 1) InVars {~t5_pc~0=v_~t5_pc~0_23} OutVars{~t5_pc~0=v_~t5_pc~0_23} AuxVars[] AssignedVars[] 15031#L406-7 [2874] L406-7-->L416-7: Formula: (and (= 1 v_~E_5~0_32) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_52 1)) InVars {~E_5~0=v_~E_5~0_32} OutVars{~E_5~0=v_~E_5~0_32, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_52} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 15033#L416-7 [4338] L416-7-->L855-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 15052#L855-21 [3251] L855-21-->L855-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} AuxVars[] AssignedVars[] 15161#L855-23 [3257] L855-23-->L424-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_25|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 15148#L424-21 [3173] L424-21-->L425-7: Formula: (= 1 v_~t6_pc~0_23) InVars {~t6_pc~0=v_~t6_pc~0_23} OutVars{~t6_pc~0=v_~t6_pc~0_23} AuxVars[] AssignedVars[] 15130#L425-7 [3114] L425-7-->L435-7: Formula: (and (= 1 v_~E_6~0_32) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_52 1)) InVars {~E_6~0=v_~E_6~0_32} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_52, ~E_6~0=v_~E_6~0_32} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 14774#L435-7 [4340] L435-7-->L863-21: Formula: (and (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___5~0_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_35|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_41|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 14775#L863-21 [4135] L863-21-->L863-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___5~0_47 0) (= v_~t6_st~0_22 0)) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} OutVars{~t6_st~0=v_~t6_st~0_22, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} AuxVars[] AssignedVars[~t6_st~0] 14817#L863-23 [4137] L863-23-->L733-3: Formula: (< v_~M_E~0_35 1) InVars {~M_E~0=v_~M_E~0_35} OutVars{~M_E~0=v_~M_E~0_35} AuxVars[] AssignedVars[] 14818#L733-3 [3184] L733-3-->L738-3: Formula: (and (= v_~T1_E~0_15 1) (= v_~T1_E~0_14 2)) InVars {~T1_E~0=v_~T1_E~0_15} OutVars{~T1_E~0=v_~T1_E~0_14} AuxVars[] AssignedVars[~T1_E~0] 15077#L738-3 [4142] L738-3-->L743-3: Formula: (< 1 v_~T2_E~0_16) InVars {~T2_E~0=v_~T2_E~0_16} OutVars{~T2_E~0=v_~T2_E~0_16} AuxVars[] AssignedVars[] 14797#L743-3 [4143] L743-3-->L748-3: Formula: (< 1 v_~T3_E~0_16) InVars {~T3_E~0=v_~T3_E~0_16} OutVars{~T3_E~0=v_~T3_E~0_16} AuxVars[] AssignedVars[] 14798#L748-3 [4145] L748-3-->L753-3: Formula: (> v_~T4_E~0_16 1) InVars {~T4_E~0=v_~T4_E~0_16} OutVars{~T4_E~0=v_~T4_E~0_16} AuxVars[] AssignedVars[] 14655#L753-3 [4148] L753-3-->L758-3: Formula: (< 1 v_~T5_E~0_16) InVars {~T5_E~0=v_~T5_E~0_16} OutVars{~T5_E~0=v_~T5_E~0_16} AuxVars[] AssignedVars[] 14656#L758-3 [4149] L758-3-->L763-3: Formula: (> v_~T6_E~0_16 1) InVars {~T6_E~0=v_~T6_E~0_16} OutVars{~T6_E~0=v_~T6_E~0_16} AuxVars[] AssignedVars[] 14746#L763-3 [4151] L763-3-->L768-3: Formula: (< 1 v_~E_1~0_36) InVars {~E_1~0=v_~E_1~0_36} OutVars{~E_1~0=v_~E_1~0_36} AuxVars[] AssignedVars[] 14747#L768-3 [3219] L768-3-->L773-3: Formula: (and (= 1 v_~E_2~0_35) (= v_~E_2~0_34 2)) InVars {~E_2~0=v_~E_2~0_35} OutVars{~E_2~0=v_~E_2~0_34} AuxVars[] AssignedVars[~E_2~0] 14972#L773-3 [2775] L773-3-->L778-3: Formula: (and (= 1 v_~E_3~0_35) (= v_~E_3~0_34 2)) InVars {~E_3~0=v_~E_3~0_35} OutVars{~E_3~0=v_~E_3~0_34} AuxVars[] AssignedVars[~E_3~0] 14973#L778-3 [3308] L778-3-->L783-3: Formula: (and (= 1 v_~E_4~0_35) (= v_~E_4~0_34 2)) InVars {~E_4~0=v_~E_4~0_35} OutVars{~E_4~0=v_~E_4~0_34} AuxVars[] AssignedVars[~E_4~0] 14868#L783-3 [4160] L783-3-->L788-3: Formula: (< 1 v_~E_5~0_36) InVars {~E_5~0=v_~E_5~0_36} OutVars{~E_5~0=v_~E_5~0_36} AuxVars[] AssignedVars[] 14869#L788-3 [4161] L788-3-->L793-3: Formula: (> 1 v_~E_6~0_36) InVars {~E_6~0=v_~E_6~0_36} OutVars{~E_6~0=v_~E_6~0_36} AuxVars[] AssignedVars[] 15075#L793-3 [2966] L793-3-->L494-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_30} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 15037#L494-1 [2878] L494-1-->L531-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33 1) (= 0 v_~m_st~0_21)) InVars {~m_st~0=v_~m_st~0_21} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33, ~m_st~0=v_~m_st~0_21} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 14734#L531-1 [4341] L531-1-->L1033: Formula: (and (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp~3] 14959#L1033 [4169] L1033-->L1033-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_6) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} AuxVars[] AssignedVars[] 14704#L1033-1 [2919] L1033-1-->L494-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_3|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_6, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_exists_runnable_thread_~__retres1~7, ULTIMATE.start_stop_simulation_#res] 15038#L494-2 [2882] L494-2-->L531-2: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9 1) (= v_~m_st~0_6 0)) InVars {~m_st~0=v_~m_st~0_6} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9, ~m_st~0=v_~m_st~0_6} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 14738#L531-2 [4343] L531-2-->L988: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 14964#L988 [3240] L988-->L995: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 14700#L995 [4354] L995-->L1014-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_6|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_#t~ret17, ULTIMATE.start_stop_simulation_#res] 14701#L1014-1 [2020-06-22 00:13:08,684 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:08,684 INFO L82 PathProgramCache]: Analyzing trace with hash -1689766678, now seen corresponding path program 1 times [2020-06-22 00:13:08,684 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:08,684 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:08,685 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:08,686 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:08,686 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:08,692 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:08,708 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:08,709 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:08,709 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-06-22 00:13:08,709 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-06-22 00:13:08,709 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:08,709 INFO L82 PathProgramCache]: Analyzing trace with hash -1162655750, now seen corresponding path program 1 times [2020-06-22 00:13:08,709 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:08,710 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:08,710 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:08,710 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:08,711 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:08,713 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:08,741 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:08,742 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:08,742 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2020-06-22 00:13:08,742 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-06-22 00:13:08,742 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-06-22 00:13:08,742 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-06-22 00:13:08,743 INFO L87 Difference]: Start difference. First operand 518 states and 1068 transitions. cyclomatic complexity: 551 Second operand 3 states. [2020-06-22 00:13:09,488 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-06-22 00:13:09,488 INFO L93 Difference]: Finished difference Result 546 states and 1096 transitions. [2020-06-22 00:13:09,489 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-06-22 00:13:09,489 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 546 states and 1096 transitions. [2020-06-22 00:13:09,492 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 470 [2020-06-22 00:13:09,495 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 546 states to 546 states and 1096 transitions. [2020-06-22 00:13:09,496 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 546 [2020-06-22 00:13:09,496 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 546 [2020-06-22 00:13:09,496 INFO L73 IsDeterministic]: Start isDeterministic. Operand 546 states and 1096 transitions. [2020-06-22 00:13:09,497 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-06-22 00:13:09,497 INFO L706 BuchiCegarLoop]: Abstraction has 546 states and 1096 transitions. [2020-06-22 00:13:09,498 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 546 states and 1096 transitions. [2020-06-22 00:13:09,503 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 546 to 518. [2020-06-22 00:13:09,503 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 518 states. [2020-06-22 00:13:09,505 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 518 states to 518 states and 1042 transitions. [2020-06-22 00:13:09,505 INFO L729 BuchiCegarLoop]: Abstraction has 518 states and 1042 transitions. [2020-06-22 00:13:09,505 INFO L609 BuchiCegarLoop]: Abstraction has 518 states and 1042 transitions. [2020-06-22 00:13:09,505 INFO L442 BuchiCegarLoop]: ======== Iteration 16============ [2020-06-22 00:13:09,505 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 518 states and 1042 transitions. [2020-06-22 00:13:09,507 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 442 [2020-06-22 00:13:09,507 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-06-22 00:13:09,507 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-06-22 00:13:09,508 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:09,508 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:09,509 INFO L794 eck$LassoCheckResult]: Stem: 16161#ULTIMATE.startENTRY [4266] ULTIMATE.startENTRY-->L444: Formula: (and (= 1 v_~t6_i~0_7) (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~M_E~0_37 2) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 0 v_~t6_pc~0_26) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_6~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= v_~T6_E~0_18 2) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~t6_st~0_24) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t6_pc~0=v_~t6_pc~0_26, ~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~T6_E~0=v_~T6_E~0_18, ~M_E~0=v_~M_E~0_37, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ~T4_E~0=v_~T4_E~0_18, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_4|, ~t6_i~0=v_~t6_i~0_7, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ULTIMATE.start_main_~__retres1~8=v_ULTIMATE.start_main_~__retres1~8_6, ~T2_E~0=v_~T2_E~0_18, ~t6_st~0=v_~t6_st~0_24, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_6~0=v_~E_6~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t6_pc~0, ~t5_i~0, ~t1_pc~0, ~t5_st~0, ~T6_E~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ~T4_E~0, ULTIMATE.start_start_simulation_#t~ret17, ~t6_i~0, ~t2_st~0, ~t2_pc~0, ULTIMATE.start_main_~__retres1~8, ~T2_E~0, ~t6_st~0, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_6~0, ULTIMATE.start_main_#res, ~E_2~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 15811#L444 [2453] L444-->L451-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 15812#L451-1 [3030] L451-1-->L456-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 15897#L456-1 [2574] L456-1-->L461-1: Formula: (and (= v_~t2_st~0_2 0) (= 1 v_~t2_i~0_3)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_2} AuxVars[] AssignedVars[~t2_st~0] 15898#L461-1 [2880] L461-1-->L466-1: Formula: (and (= v_~t3_st~0_3 0) (= v_~t3_i~0_3 1)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_3, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 15813#L466-1 [2457] L466-1-->L471-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 15814#L471-1 [3209] L471-1-->L476-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 16037#L476-1 [2761] L476-1-->L481-1: Formula: (and (= 1 v_~t6_i~0_3) (= v_~t6_st~0_4 0)) InVars {~t6_i~0=v_~t6_i~0_3} OutVars{~t6_st~0=v_~t6_st~0_4, ~t6_i~0=v_~t6_i~0_3} AuxVars[] AssignedVars[~t6_st~0] 16038#L481-1 [3652] L481-1-->L660-1: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 16172#L660-1 [3654] L660-1-->L665-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 15731#L665-1 [3655] L665-1-->L670-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 15732#L670-1 [3658] L670-1-->L675-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 15820#L675-1 [3659] L675-1-->L680-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 15821#L680-1 [3661] L680-1-->L685-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 16046#L685-1 [3663] L685-1-->L690-1: Formula: (< 0 v_~T6_E~0_4) InVars {~T6_E~0=v_~T6_E~0_4} OutVars{~T6_E~0=v_~T6_E~0_4} AuxVars[] AssignedVars[] 16047#L690-1 [3665] L690-1-->L695-1: Formula: (> v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 15942#L695-1 [3668] L695-1-->L700-1: Formula: (> v_~E_2~0_6 0) InVars {~E_2~0=v_~E_2~0_6} OutVars{~E_2~0=v_~E_2~0_6} AuxVars[] AssignedVars[] 15943#L700-1 [3180] L700-1-->L705-1: Formula: (and (= v_~E_3~0_5 0) (= v_~E_3~0_4 1)) InVars {~E_3~0=v_~E_3~0_5} OutVars{~E_3~0=v_~E_3~0_4} AuxVars[] AssignedVars[~E_3~0] 16148#L705-1 [3672] L705-1-->L710-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 15881#L710-1 [2525] L710-1-->L715-1: Formula: (and (= v_~E_5~0_3 0) (= v_~E_5~0_2 1)) InVars {~E_5~0=v_~E_5~0_3} OutVars{~E_5~0=v_~E_5~0_2} AuxVars[] AssignedVars[~E_5~0] 15882#L715-1 [3676] L715-1-->L720-1: Formula: (< v_~E_6~0_4 0) InVars {~E_6~0=v_~E_6~0_4} OutVars{~E_6~0=v_~E_6~0_4} AuxVars[] AssignedVars[] 15765#L720-1 [2412] L720-1-->L310: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_7, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_4|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_4|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_7, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_4, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_4, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_2|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_2|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_4|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_4|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_7, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_2|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_4} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 15766#L310 [2597] L310-->L311: Formula: (= v_~m_pc~0_4 1) InVars {~m_pc~0=v_~m_pc~0_4} OutVars{~m_pc~0=v_~m_pc~0_4} AuxVars[] AssignedVars[] 15913#L311 [2732] L311-->L321: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_10 1) (= 1 v_~M_E~0_8)) InVars {~M_E~0=v_~M_E~0_8} OutVars{~M_E~0=v_~M_E~0_8, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_10} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 15911#L321 [4267] L321-->L815: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 15912#L815 [3682] L815-->L815-2: Formula: (and (= v_~m_st~0_5 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_11)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} OutVars{~m_st~0=v_~m_st~0_5, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} AuxVars[] AssignedVars[~m_st~0] 16144#L815-2 [2961] L815-2-->L329: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 16080#L329 [3684] L329-->L329-2: Formula: (> v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 16082#L329-2 [2861] L329-2-->L340: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 16078#L340 [4268] L340-->L823: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 16079#L823 [3688] L823-->L823-2: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___0~0_11 0) (= v_~t1_st~0_5 0)) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_11} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_11, ~t1_st~0=v_~t1_st~0_5} AuxVars[] AssignedVars[~t1_st~0] 16230#L823-2 [3235] L823-2-->L348: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_4|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 16214#L348 [3690] L348-->L348-2: Formula: (< v_~t2_pc~0_5 1) InVars {~t2_pc~0=v_~t2_pc~0_5} OutVars{~t2_pc~0=v_~t2_pc~0_5} AuxVars[] AssignedVars[] 16216#L348-2 [3153] L348-2-->L359: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 16213#L359 [4269] L359-->L831: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 15888#L831 [3694] L831-->L831-2: Formula: (and (= v_~t2_st~0_5 0) (> v_ULTIMATE.start_activate_threads_~tmp___1~0_11 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_11} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_11, ~t2_st~0=v_~t2_st~0_5} AuxVars[] AssignedVars[~t2_st~0] 15876#L831-2 [2520] L831-2-->L367: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_4|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 15816#L367 [3695] L367-->L367-2: Formula: (> 1 v_~t3_pc~0_5) InVars {~t3_pc~0=v_~t3_pc~0_5} OutVars{~t3_pc~0=v_~t3_pc~0_5} AuxVars[] AssignedVars[] 15794#L367-2 [2438] L367-2-->L378: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 15795#L378 [4270] L378-->L839: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 15815#L839 [2791] L839-->L839-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} AuxVars[] AssignedVars[] 16053#L839-2 [2794] L839-2-->L386: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_7, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 15983#L386 [2675] L386-->L387: Formula: (= v_~t4_pc~0_4 1) InVars {~t4_pc~0=v_~t4_pc~0_4} OutVars{~t4_pc~0=v_~t4_pc~0_4} AuxVars[] AssignedVars[] 15902#L387 [2588] L387-->L397: Formula: (and (= v_~E_4~0_7 1) (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_10 1)) InVars {~E_4~0=v_~E_4~0_7} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_10, ~E_4~0=v_~E_4~0_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 15904#L397 [4271] L397-->L847: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 15982#L847 [3084] L847-->L847-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} AuxVars[] AssignedVars[] 16176#L847-2 [3064] L847-2-->L405: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_4|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 16177#L405 [3708] L405-->L405-2: Formula: (> 1 v_~t5_pc~0_5) InVars {~t5_pc~0=v_~t5_pc~0_5} OutVars{~t5_pc~0=v_~t5_pc~0_5} AuxVars[] AssignedVars[] 16113#L405-2 [2940] L405-2-->L416: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 16112#L416 [4272] L416-->L855: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 16183#L855 [3711] L855-->L855-2: Formula: (and (> v_ULTIMATE.start_activate_threads_~tmp___4~0_11 0) (= v_~t5_st~0_7 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_11} OutVars{~t5_st~0=v_~t5_st~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_11} AuxVars[] AssignedVars[~t5_st~0] 16184#L855-2 [3093] L855-2-->L424: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_4|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 15860#L424 [3714] L424-->L424-2: Formula: (> v_~t6_pc~0_5 1) InVars {~t6_pc~0=v_~t6_pc~0_5} OutVars{~t6_pc~0=v_~t6_pc~0_5} AuxVars[] AssignedVars[] 15861#L424-2 [2503] L424-2-->L435: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 15859#L435 [4273] L435-->L863: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___5~0_49 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_28|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_28|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 15781#L863 [2425] L863-->L863-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___5~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} AuxVars[] AssignedVars[] 15755#L863-2 [3720] L863-2-->L733-1: Formula: (< v_~M_E~0_15 1) InVars {~M_E~0=v_~M_E~0_15} OutVars{~M_E~0=v_~M_E~0_15} AuxVars[] AssignedVars[] 15756#L733-1 [3722] L733-1-->L738-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 16146#L738-1 [3723] L738-1-->L743-1: Formula: (< 1 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 15879#L743-1 [3726] L743-1-->L748-1: Formula: (< 1 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 15880#L748-1 [3728] L748-1-->L753-1: Formula: (> v_~T4_E~0_10 1) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 15760#L753-1 [3729] L753-1-->L758-1: Formula: (< 1 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 15761#L758-1 [3732] L758-1-->L763-1: Formula: (< v_~T6_E~0_10 1) InVars {~T6_E~0=v_~T6_E~0_10} OutVars{~T6_E~0=v_~T6_E~0_10} AuxVars[] AssignedVars[] 15832#L763-1 [3733] L763-1-->L768-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 15833#L768-1 [3736] L768-1-->L773-1: Formula: (< 1 v_~E_2~0_14) InVars {~E_2~0=v_~E_2~0_14} OutVars{~E_2~0=v_~E_2~0_14} AuxVars[] AssignedVars[] 16042#L773-1 [2767] L773-1-->L778-1: Formula: (and (= 1 v_~E_3~0_13) (= v_~E_3~0_12 2)) InVars {~E_3~0=v_~E_3~0_13} OutVars{~E_3~0=v_~E_3~0_12} AuxVars[] AssignedVars[~E_3~0] 16043#L778-1 [3740] L778-1-->L783-1: Formula: (< 1 v_~E_4~0_14) InVars {~E_4~0=v_~E_4~0_14} OutVars{~E_4~0=v_~E_4~0_14} AuxVars[] AssignedVars[] 15935#L783-1 [3742] L783-1-->L788-1: Formula: (> 1 v_~E_5~0_14) InVars {~E_5~0=v_~E_5~0_14} OutVars{~E_5~0=v_~E_5~0_14} AuxVars[] AssignedVars[] 15936#L788-1 [3743] L788-1-->L1014-1: Formula: (> 1 v_~E_6~0_14) InVars {~E_6~0=v_~E_6~0_14} OutVars{~E_6~0=v_~E_6~0_14} AuxVars[] AssignedVars[] 15773#L1014-1 [2020-06-22 00:13:09,510 INFO L796 eck$LassoCheckResult]: Loop: 15773#L1014-1 [4274] L1014-1-->L635: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp_ndt_7~0=v_ULTIMATE.start_eval_~tmp_ndt_7~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp_ndt_7~0] 15737#L635 [4275] L635-->L494: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_37} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 16108#L494 [2876] L494-->L531: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21 1) (= v_~m_st~0_8 0)) InVars {~m_st~0=v_~m_st~0_8} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21, ~m_st~0=v_~m_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 15804#L531 [4276] L531-->L546: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 16030#L546 [4278] L546-->L660-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 16173#L660-2 [3747] L660-2-->L660-4: Formula: (> v_~M_E~0_30 0) InVars {~M_E~0=v_~M_E~0_30} OutVars{~M_E~0=v_~M_E~0_30} AuxVars[] AssignedVars[] 16174#L660-4 [3058] L660-4-->L665-3: Formula: (and (= v_~T1_E~0_11 1) (= v_~T1_E~0_12 0)) InVars {~T1_E~0=v_~T1_E~0_12} OutVars{~T1_E~0=v_~T1_E~0_11} AuxVars[] AssignedVars[~T1_E~0] 15747#L665-3 [3756] L665-3-->L670-3: Formula: (< 0 v_~T2_E~0_13) InVars {~T2_E~0=v_~T2_E~0_13} OutVars{~T2_E~0=v_~T2_E~0_13} AuxVars[] AssignedVars[] 15748#L670-3 [3762] L670-3-->L675-3: Formula: (< 0 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 15822#L675-3 [3768] L675-3-->L680-3: Formula: (> v_~T4_E~0_13 0) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 15823#L680-3 [3776] L680-3-->L685-3: Formula: (< 0 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 16049#L685-3 [3785] L685-3-->L690-3: Formula: (> v_~T6_E~0_13 0) InVars {~T6_E~0=v_~T6_E~0_13} OutVars{~T6_E~0=v_~T6_E~0_13} AuxVars[] AssignedVars[] 16050#L690-3 [3795] L690-3-->L695-3: Formula: (< 0 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 15928#L695-3 [3805] L695-3-->L700-3: Formula: (< 0 v_~E_2~0_31) InVars {~E_2~0=v_~E_2~0_31} OutVars{~E_2~0=v_~E_2~0_31} AuxVars[] AssignedVars[] 15929#L700-3 [3155] L700-3-->L705-3: Formula: (and (= v_~E_3~0_29 1) (= 0 v_~E_3~0_30)) InVars {~E_3~0=v_~E_3~0_30} OutVars{~E_3~0=v_~E_3~0_29} AuxVars[] AssignedVars[~E_3~0] 15991#L705-3 [2688] L705-3-->L710-3: Formula: (and (= v_~E_4~0_29 1) (= 0 v_~E_4~0_30)) InVars {~E_4~0=v_~E_4~0_30} OutVars{~E_4~0=v_~E_4~0_29} AuxVars[] AssignedVars[~E_4~0] 15873#L710-3 [2515] L710-3-->L715-3: Formula: (and (= 0 v_~E_5~0_30) (= v_~E_5~0_29 1)) InVars {~E_5~0=v_~E_5~0_30} OutVars{~E_5~0=v_~E_5~0_29} AuxVars[] AssignedVars[~E_5~0] 15874#L715-3 [3048] L715-3-->L720-3: Formula: (and (= v_~E_6~0_29 1) (= 0 v_~E_6~0_30)) InVars {~E_6~0=v_~E_6~0_30} OutVars{~E_6~0=v_~E_6~0_29} AuxVars[] AssignedVars[~E_6~0] 15733#L720-3 [2388] L720-3-->L310-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_43, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_43, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_25|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_25|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_25|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_43, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_43, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_43, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_25|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_25|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_25|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_25|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_43, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_25|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_43, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_43} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 15734#L310-21 [3869] L310-21-->L310-23: Formula: (> v_~m_pc~0_24 1) InVars {~m_pc~0=v_~m_pc~0_24} OutVars{~m_pc~0=v_~m_pc~0_24} AuxVars[] AssignedVars[] 16016#L310-23 [2785] L310-23-->L321-7: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_47 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_47} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 16015#L321-7 [4303] L321-7-->L815-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 15976#L815-21 [3897] L815-21-->L815-23: Formula: (and (> 0 v_ULTIMATE.start_activate_threads_~tmp~1_47) (= v_~m_st~0_20 0)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_47} OutVars{~m_st~0=v_~m_st~0_20, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_47} AuxVars[] AssignedVars[~m_st~0] 15957#L815-23 [2638] L815-23-->L329-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 15958#L329-21 [3911] L329-21-->L329-23: Formula: (< v_~t1_pc~0_24 1) InVars {~t1_pc~0=v_~t1_pc~0_24} OutVars{~t1_pc~0=v_~t1_pc~0_24} AuxVars[] AssignedVars[] 16154#L329-23 [3052] L329-23-->L340-7: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 16068#L340-7 [4310] L340-7-->L823-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 16069#L823-21 [2931] L823-21-->L823-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} AuxVars[] AssignedVars[] 16128#L823-23 [2934] L823-23-->L348-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_25|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 16130#L348-21 [3953] L348-21-->L348-23: Formula: (> 1 v_~t2_pc~0_24) InVars {~t2_pc~0=v_~t2_pc~0_24} OutVars{~t2_pc~0=v_~t2_pc~0_24} AuxVars[] AssignedVars[] 16235#L348-23 [3319] L348-23-->L359-7: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 16210#L359-7 [4317] L359-7-->L831-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 15851#L831-21 [2490] L831-21-->L831-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} AuxVars[] AssignedVars[] 15852#L831-23 [3197] L831-23-->L367-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_25|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 15762#L367-21 [3995] L367-21-->L367-23: Formula: (> v_~t3_pc~0_24 1) InVars {~t3_pc~0=v_~t3_pc~0_24} OutVars{~t3_pc~0=v_~t3_pc~0_24} AuxVars[] AssignedVars[] 15729#L367-23 [2385] L367-23-->L378-7: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 15730#L378-7 [4324] L378-7-->L839-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 15786#L839-21 [4023] L839-21-->L839-23: Formula: (and (= v_~t3_st~0_21 0) (> v_ULTIMATE.start_activate_threads_~tmp___2~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} OutVars{~t3_st~0=v_~t3_st~0_21, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} AuxVars[] AssignedVars[~t3_st~0] 16007#L839-23 [2722] L839-23-->L386-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_49, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 15937#L386-21 [4037] L386-21-->L386-23: Formula: (< 1 v_~t4_pc~0_24) InVars {~t4_pc~0=v_~t4_pc~0_24} OutVars{~t4_pc~0=v_~t4_pc~0_24} AuxVars[] AssignedVars[] 15938#L386-23 [2623] L386-23-->L397-7: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 15944#L397-7 [4331] L397-7-->L847-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 15973#L847-21 [4065] L847-21-->L847-23: Formula: (and (= v_~t4_st~0_22 0) (< v_ULTIMATE.start_activate_threads_~tmp___3~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47, ~t4_st~0=v_~t4_st~0_22} AuxVars[] AssignedVars[~t4_st~0] 16155#L847-23 [2983] L847-23-->L405-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_25|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 16119#L405-21 [2911] L405-21-->L406-7: Formula: (= v_~t5_pc~0_23 1) InVars {~t5_pc~0=v_~t5_pc~0_23} OutVars{~t5_pc~0=v_~t5_pc~0_23} AuxVars[] AssignedVars[] 16105#L406-7 [2874] L406-7-->L416-7: Formula: (and (= 1 v_~E_5~0_32) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_52 1)) InVars {~E_5~0=v_~E_5~0_32} OutVars{~E_5~0=v_~E_5~0_32, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_52} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 16107#L416-7 [4338] L416-7-->L855-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 16124#L855-21 [3251] L855-21-->L855-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} AuxVars[] AssignedVars[] 16233#L855-23 [3257] L855-23-->L424-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_25|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 16220#L424-21 [3173] L424-21-->L425-7: Formula: (= 1 v_~t6_pc~0_23) InVars {~t6_pc~0=v_~t6_pc~0_23} OutVars{~t6_pc~0=v_~t6_pc~0_23} AuxVars[] AssignedVars[] 16202#L425-7 [3114] L425-7-->L435-7: Formula: (and (= 1 v_~E_6~0_32) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_52 1)) InVars {~E_6~0=v_~E_6~0_32} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_52, ~E_6~0=v_~E_6~0_32} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 15846#L435-7 [4340] L435-7-->L863-21: Formula: (and (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___5~0_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_35|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_41|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 15847#L863-21 [4135] L863-21-->L863-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___5~0_47 0) (= v_~t6_st~0_22 0)) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} OutVars{~t6_st~0=v_~t6_st~0_22, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} AuxVars[] AssignedVars[~t6_st~0] 15889#L863-23 [4137] L863-23-->L733-3: Formula: (< v_~M_E~0_35 1) InVars {~M_E~0=v_~M_E~0_35} OutVars{~M_E~0=v_~M_E~0_35} AuxVars[] AssignedVars[] 15890#L733-3 [3184] L733-3-->L738-3: Formula: (and (= v_~T1_E~0_15 1) (= v_~T1_E~0_14 2)) InVars {~T1_E~0=v_~T1_E~0_15} OutVars{~T1_E~0=v_~T1_E~0_14} AuxVars[] AssignedVars[~T1_E~0] 16149#L738-3 [4142] L738-3-->L743-3: Formula: (< 1 v_~T2_E~0_16) InVars {~T2_E~0=v_~T2_E~0_16} OutVars{~T2_E~0=v_~T2_E~0_16} AuxVars[] AssignedVars[] 15869#L743-3 [4143] L743-3-->L748-3: Formula: (< 1 v_~T3_E~0_16) InVars {~T3_E~0=v_~T3_E~0_16} OutVars{~T3_E~0=v_~T3_E~0_16} AuxVars[] AssignedVars[] 15870#L748-3 [4145] L748-3-->L753-3: Formula: (> v_~T4_E~0_16 1) InVars {~T4_E~0=v_~T4_E~0_16} OutVars{~T4_E~0=v_~T4_E~0_16} AuxVars[] AssignedVars[] 15727#L753-3 [4148] L753-3-->L758-3: Formula: (< 1 v_~T5_E~0_16) InVars {~T5_E~0=v_~T5_E~0_16} OutVars{~T5_E~0=v_~T5_E~0_16} AuxVars[] AssignedVars[] 15728#L758-3 [4149] L758-3-->L763-3: Formula: (> v_~T6_E~0_16 1) InVars {~T6_E~0=v_~T6_E~0_16} OutVars{~T6_E~0=v_~T6_E~0_16} AuxVars[] AssignedVars[] 15818#L763-3 [4151] L763-3-->L768-3: Formula: (< 1 v_~E_1~0_36) InVars {~E_1~0=v_~E_1~0_36} OutVars{~E_1~0=v_~E_1~0_36} AuxVars[] AssignedVars[] 15819#L768-3 [4154] L768-3-->L773-3: Formula: (< 1 v_~E_2~0_36) InVars {~E_2~0=v_~E_2~0_36} OutVars{~E_2~0=v_~E_2~0_36} AuxVars[] AssignedVars[] 16044#L773-3 [2775] L773-3-->L778-3: Formula: (and (= 1 v_~E_3~0_35) (= v_~E_3~0_34 2)) InVars {~E_3~0=v_~E_3~0_35} OutVars{~E_3~0=v_~E_3~0_34} AuxVars[] AssignedVars[~E_3~0] 16045#L778-3 [3308] L778-3-->L783-3: Formula: (and (= 1 v_~E_4~0_35) (= v_~E_4~0_34 2)) InVars {~E_4~0=v_~E_4~0_35} OutVars{~E_4~0=v_~E_4~0_34} AuxVars[] AssignedVars[~E_4~0] 15940#L783-3 [4160] L783-3-->L788-3: Formula: (< 1 v_~E_5~0_36) InVars {~E_5~0=v_~E_5~0_36} OutVars{~E_5~0=v_~E_5~0_36} AuxVars[] AssignedVars[] 15941#L788-3 [4161] L788-3-->L793-3: Formula: (> 1 v_~E_6~0_36) InVars {~E_6~0=v_~E_6~0_36} OutVars{~E_6~0=v_~E_6~0_36} AuxVars[] AssignedVars[] 16147#L793-3 [2966] L793-3-->L494-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_30} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 16109#L494-1 [2878] L494-1-->L531-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33 1) (= 0 v_~m_st~0_21)) InVars {~m_st~0=v_~m_st~0_21} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33, ~m_st~0=v_~m_st~0_21} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 15806#L531-1 [4341] L531-1-->L1033: Formula: (and (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp~3] 16031#L1033 [4169] L1033-->L1033-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_6) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} AuxVars[] AssignedVars[] 15776#L1033-1 [2919] L1033-1-->L494-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_3|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_6, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_exists_runnable_thread_~__retres1~7, ULTIMATE.start_stop_simulation_#res] 16110#L494-2 [2882] L494-2-->L531-2: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9 1) (= v_~m_st~0_6 0)) InVars {~m_st~0=v_~m_st~0_6} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9, ~m_st~0=v_~m_st~0_6} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 15810#L531-2 [4343] L531-2-->L988: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 16036#L988 [3240] L988-->L995: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 15772#L995 [4354] L995-->L1014-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_6|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_#t~ret17, ULTIMATE.start_stop_simulation_#res] 15773#L1014-1 [2020-06-22 00:13:09,510 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:09,511 INFO L82 PathProgramCache]: Analyzing trace with hash 1908800982, now seen corresponding path program 1 times [2020-06-22 00:13:09,511 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:09,511 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:09,512 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:09,512 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:09,512 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:09,517 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:09,536 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:09,536 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:09,537 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-06-22 00:13:09,537 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-06-22 00:13:09,537 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:09,537 INFO L82 PathProgramCache]: Analyzing trace with hash -1530416224, now seen corresponding path program 1 times [2020-06-22 00:13:09,537 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:09,537 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:09,538 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:09,538 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:09,539 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:09,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:09,564 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:09,564 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:09,564 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2020-06-22 00:13:09,565 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-06-22 00:13:09,565 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-06-22 00:13:09,565 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-06-22 00:13:09,565 INFO L87 Difference]: Start difference. First operand 518 states and 1042 transitions. cyclomatic complexity: 525 Second operand 3 states. [2020-06-22 00:13:10,283 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-06-22 00:13:10,283 INFO L93 Difference]: Finished difference Result 540 states and 1058 transitions. [2020-06-22 00:13:10,283 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-06-22 00:13:10,284 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 540 states and 1058 transitions. [2020-06-22 00:13:10,286 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 464 [2020-06-22 00:13:10,289 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 540 states to 540 states and 1058 transitions. [2020-06-22 00:13:10,289 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 540 [2020-06-22 00:13:10,290 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 540 [2020-06-22 00:13:10,290 INFO L73 IsDeterministic]: Start isDeterministic. Operand 540 states and 1058 transitions. [2020-06-22 00:13:10,290 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-06-22 00:13:10,291 INFO L706 BuchiCegarLoop]: Abstraction has 540 states and 1058 transitions. [2020-06-22 00:13:10,291 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 540 states and 1058 transitions. [2020-06-22 00:13:10,297 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 540 to 518. [2020-06-22 00:13:10,297 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 518 states. [2020-06-22 00:13:10,298 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 518 states to 518 states and 1016 transitions. [2020-06-22 00:13:10,298 INFO L729 BuchiCegarLoop]: Abstraction has 518 states and 1016 transitions. [2020-06-22 00:13:10,298 INFO L609 BuchiCegarLoop]: Abstraction has 518 states and 1016 transitions. [2020-06-22 00:13:10,299 INFO L442 BuchiCegarLoop]: ======== Iteration 17============ [2020-06-22 00:13:10,299 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 518 states and 1016 transitions. [2020-06-22 00:13:10,300 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 442 [2020-06-22 00:13:10,300 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-06-22 00:13:10,300 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-06-22 00:13:10,301 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:10,301 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:10,302 INFO L794 eck$LassoCheckResult]: Stem: 17227#ULTIMATE.startENTRY [4266] ULTIMATE.startENTRY-->L444: Formula: (and (= 1 v_~t6_i~0_7) (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~M_E~0_37 2) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 0 v_~t6_pc~0_26) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_6~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= v_~T6_E~0_18 2) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~t6_st~0_24) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t6_pc~0=v_~t6_pc~0_26, ~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~T6_E~0=v_~T6_E~0_18, ~M_E~0=v_~M_E~0_37, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ~T4_E~0=v_~T4_E~0_18, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_4|, ~t6_i~0=v_~t6_i~0_7, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ULTIMATE.start_main_~__retres1~8=v_ULTIMATE.start_main_~__retres1~8_6, ~T2_E~0=v_~T2_E~0_18, ~t6_st~0=v_~t6_st~0_24, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_6~0=v_~E_6~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t6_pc~0, ~t5_i~0, ~t1_pc~0, ~t5_st~0, ~T6_E~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ~T4_E~0, ULTIMATE.start_start_simulation_#t~ret17, ~t6_i~0, ~t2_st~0, ~t2_pc~0, ULTIMATE.start_main_~__retres1~8, ~T2_E~0, ~t6_st~0, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_6~0, ULTIMATE.start_main_#res, ~E_2~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 16877#L444 [2453] L444-->L451-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 16878#L451-1 [3030] L451-1-->L456-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 16963#L456-1 [2574] L456-1-->L461-1: Formula: (and (= v_~t2_st~0_2 0) (= 1 v_~t2_i~0_3)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_2} AuxVars[] AssignedVars[~t2_st~0] 16964#L461-1 [2880] L461-1-->L466-1: Formula: (and (= v_~t3_st~0_3 0) (= v_~t3_i~0_3 1)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_3, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 16879#L466-1 [2457] L466-1-->L471-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 16880#L471-1 [3209] L471-1-->L476-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 17103#L476-1 [2761] L476-1-->L481-1: Formula: (and (= 1 v_~t6_i~0_3) (= v_~t6_st~0_4 0)) InVars {~t6_i~0=v_~t6_i~0_3} OutVars{~t6_st~0=v_~t6_st~0_4, ~t6_i~0=v_~t6_i~0_3} AuxVars[] AssignedVars[~t6_st~0] 17104#L481-1 [3652] L481-1-->L660-1: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 17238#L660-1 [3654] L660-1-->L665-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 16797#L665-1 [3655] L665-1-->L670-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 16798#L670-1 [3658] L670-1-->L675-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 16886#L675-1 [3659] L675-1-->L680-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 16887#L680-1 [3661] L680-1-->L685-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 17112#L685-1 [3663] L685-1-->L690-1: Formula: (< 0 v_~T6_E~0_4) InVars {~T6_E~0=v_~T6_E~0_4} OutVars{~T6_E~0=v_~T6_E~0_4} AuxVars[] AssignedVars[] 17113#L690-1 [3665] L690-1-->L695-1: Formula: (> v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 17008#L695-1 [3668] L695-1-->L700-1: Formula: (> v_~E_2~0_6 0) InVars {~E_2~0=v_~E_2~0_6} OutVars{~E_2~0=v_~E_2~0_6} AuxVars[] AssignedVars[] 17009#L700-1 [3670] L700-1-->L705-1: Formula: (> v_~E_3~0_6 0) InVars {~E_3~0=v_~E_3~0_6} OutVars{~E_3~0=v_~E_3~0_6} AuxVars[] AssignedVars[] 17214#L705-1 [3672] L705-1-->L710-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 16947#L710-1 [2525] L710-1-->L715-1: Formula: (and (= v_~E_5~0_3 0) (= v_~E_5~0_2 1)) InVars {~E_5~0=v_~E_5~0_3} OutVars{~E_5~0=v_~E_5~0_2} AuxVars[] AssignedVars[~E_5~0] 16948#L715-1 [3676] L715-1-->L720-1: Formula: (< v_~E_6~0_4 0) InVars {~E_6~0=v_~E_6~0_4} OutVars{~E_6~0=v_~E_6~0_4} AuxVars[] AssignedVars[] 16831#L720-1 [2412] L720-1-->L310: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_7, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_4|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_4|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_7, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_4, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_4, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_2|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_2|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_4|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_4|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_7, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_2|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_4} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 16832#L310 [2597] L310-->L311: Formula: (= v_~m_pc~0_4 1) InVars {~m_pc~0=v_~m_pc~0_4} OutVars{~m_pc~0=v_~m_pc~0_4} AuxVars[] AssignedVars[] 16979#L311 [2732] L311-->L321: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_10 1) (= 1 v_~M_E~0_8)) InVars {~M_E~0=v_~M_E~0_8} OutVars{~M_E~0=v_~M_E~0_8, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_10} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 16977#L321 [4267] L321-->L815: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 16978#L815 [3682] L815-->L815-2: Formula: (and (= v_~m_st~0_5 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_11)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} OutVars{~m_st~0=v_~m_st~0_5, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} AuxVars[] AssignedVars[~m_st~0] 17210#L815-2 [2961] L815-2-->L329: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 17146#L329 [3684] L329-->L329-2: Formula: (> v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 17148#L329-2 [2861] L329-2-->L340: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 17144#L340 [4268] L340-->L823: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 17145#L823 [3688] L823-->L823-2: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___0~0_11 0) (= v_~t1_st~0_5 0)) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_11} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_11, ~t1_st~0=v_~t1_st~0_5} AuxVars[] AssignedVars[~t1_st~0] 17296#L823-2 [3235] L823-2-->L348: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_4|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 17280#L348 [3690] L348-->L348-2: Formula: (< v_~t2_pc~0_5 1) InVars {~t2_pc~0=v_~t2_pc~0_5} OutVars{~t2_pc~0=v_~t2_pc~0_5} AuxVars[] AssignedVars[] 17282#L348-2 [3153] L348-2-->L359: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 17279#L359 [4269] L359-->L831: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 16954#L831 [3694] L831-->L831-2: Formula: (and (= v_~t2_st~0_5 0) (> v_ULTIMATE.start_activate_threads_~tmp___1~0_11 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_11} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_11, ~t2_st~0=v_~t2_st~0_5} AuxVars[] AssignedVars[~t2_st~0] 16942#L831-2 [2520] L831-2-->L367: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_4|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 16882#L367 [3695] L367-->L367-2: Formula: (> 1 v_~t3_pc~0_5) InVars {~t3_pc~0=v_~t3_pc~0_5} OutVars{~t3_pc~0=v_~t3_pc~0_5} AuxVars[] AssignedVars[] 16860#L367-2 [2438] L367-2-->L378: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 16861#L378 [4270] L378-->L839: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 16881#L839 [2791] L839-->L839-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} AuxVars[] AssignedVars[] 17119#L839-2 [2794] L839-2-->L386: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_7, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 17049#L386 [2675] L386-->L387: Formula: (= v_~t4_pc~0_4 1) InVars {~t4_pc~0=v_~t4_pc~0_4} OutVars{~t4_pc~0=v_~t4_pc~0_4} AuxVars[] AssignedVars[] 16968#L387 [2588] L387-->L397: Formula: (and (= v_~E_4~0_7 1) (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_10 1)) InVars {~E_4~0=v_~E_4~0_7} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_10, ~E_4~0=v_~E_4~0_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 16970#L397 [4271] L397-->L847: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 17048#L847 [3084] L847-->L847-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} AuxVars[] AssignedVars[] 17242#L847-2 [3064] L847-2-->L405: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_4|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 17243#L405 [3708] L405-->L405-2: Formula: (> 1 v_~t5_pc~0_5) InVars {~t5_pc~0=v_~t5_pc~0_5} OutVars{~t5_pc~0=v_~t5_pc~0_5} AuxVars[] AssignedVars[] 17179#L405-2 [2940] L405-2-->L416: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 17178#L416 [4272] L416-->L855: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 17249#L855 [3711] L855-->L855-2: Formula: (and (> v_ULTIMATE.start_activate_threads_~tmp___4~0_11 0) (= v_~t5_st~0_7 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_11} OutVars{~t5_st~0=v_~t5_st~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_11} AuxVars[] AssignedVars[~t5_st~0] 17250#L855-2 [3093] L855-2-->L424: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_4|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 16926#L424 [3714] L424-->L424-2: Formula: (> v_~t6_pc~0_5 1) InVars {~t6_pc~0=v_~t6_pc~0_5} OutVars{~t6_pc~0=v_~t6_pc~0_5} AuxVars[] AssignedVars[] 16927#L424-2 [2503] L424-2-->L435: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 16925#L435 [4273] L435-->L863: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___5~0_49 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_28|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_28|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 16847#L863 [2425] L863-->L863-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___5~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} AuxVars[] AssignedVars[] 16821#L863-2 [3720] L863-2-->L733-1: Formula: (< v_~M_E~0_15 1) InVars {~M_E~0=v_~M_E~0_15} OutVars{~M_E~0=v_~M_E~0_15} AuxVars[] AssignedVars[] 16822#L733-1 [3722] L733-1-->L738-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 17212#L738-1 [3723] L738-1-->L743-1: Formula: (< 1 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 16945#L743-1 [3726] L743-1-->L748-1: Formula: (< 1 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 16946#L748-1 [3728] L748-1-->L753-1: Formula: (> v_~T4_E~0_10 1) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 16826#L753-1 [3729] L753-1-->L758-1: Formula: (< 1 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 16827#L758-1 [3732] L758-1-->L763-1: Formula: (< v_~T6_E~0_10 1) InVars {~T6_E~0=v_~T6_E~0_10} OutVars{~T6_E~0=v_~T6_E~0_10} AuxVars[] AssignedVars[] 16898#L763-1 [3733] L763-1-->L768-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 16899#L768-1 [3736] L768-1-->L773-1: Formula: (< 1 v_~E_2~0_14) InVars {~E_2~0=v_~E_2~0_14} OutVars{~E_2~0=v_~E_2~0_14} AuxVars[] AssignedVars[] 17108#L773-1 [3737] L773-1-->L778-1: Formula: (< 1 v_~E_3~0_14) InVars {~E_3~0=v_~E_3~0_14} OutVars{~E_3~0=v_~E_3~0_14} AuxVars[] AssignedVars[] 17109#L778-1 [3740] L778-1-->L783-1: Formula: (< 1 v_~E_4~0_14) InVars {~E_4~0=v_~E_4~0_14} OutVars{~E_4~0=v_~E_4~0_14} AuxVars[] AssignedVars[] 17001#L783-1 [3742] L783-1-->L788-1: Formula: (> 1 v_~E_5~0_14) InVars {~E_5~0=v_~E_5~0_14} OutVars{~E_5~0=v_~E_5~0_14} AuxVars[] AssignedVars[] 17002#L788-1 [3743] L788-1-->L1014-1: Formula: (> 1 v_~E_6~0_14) InVars {~E_6~0=v_~E_6~0_14} OutVars{~E_6~0=v_~E_6~0_14} AuxVars[] AssignedVars[] 16839#L1014-1 [2020-06-22 00:13:10,303 INFO L796 eck$LassoCheckResult]: Loop: 16839#L1014-1 [4274] L1014-1-->L635: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp_ndt_7~0=v_ULTIMATE.start_eval_~tmp_ndt_7~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp_ndt_7~0] 16803#L635 [4275] L635-->L494: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_37} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 17174#L494 [2876] L494-->L531: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21 1) (= v_~m_st~0_8 0)) InVars {~m_st~0=v_~m_st~0_8} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21, ~m_st~0=v_~m_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 16870#L531 [4276] L531-->L546: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 17096#L546 [4278] L546-->L660-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 17239#L660-2 [3747] L660-2-->L660-4: Formula: (> v_~M_E~0_30 0) InVars {~M_E~0=v_~M_E~0_30} OutVars{~M_E~0=v_~M_E~0_30} AuxVars[] AssignedVars[] 17240#L660-4 [3058] L660-4-->L665-3: Formula: (and (= v_~T1_E~0_11 1) (= v_~T1_E~0_12 0)) InVars {~T1_E~0=v_~T1_E~0_12} OutVars{~T1_E~0=v_~T1_E~0_11} AuxVars[] AssignedVars[~T1_E~0] 16813#L665-3 [3756] L665-3-->L670-3: Formula: (< 0 v_~T2_E~0_13) InVars {~T2_E~0=v_~T2_E~0_13} OutVars{~T2_E~0=v_~T2_E~0_13} AuxVars[] AssignedVars[] 16814#L670-3 [3762] L670-3-->L675-3: Formula: (< 0 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 16888#L675-3 [3768] L675-3-->L680-3: Formula: (> v_~T4_E~0_13 0) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 16889#L680-3 [3776] L680-3-->L685-3: Formula: (< 0 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 17115#L685-3 [3785] L685-3-->L690-3: Formula: (> v_~T6_E~0_13 0) InVars {~T6_E~0=v_~T6_E~0_13} OutVars{~T6_E~0=v_~T6_E~0_13} AuxVars[] AssignedVars[] 17116#L690-3 [3795] L690-3-->L695-3: Formula: (< 0 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 16991#L695-3 [3805] L695-3-->L700-3: Formula: (< 0 v_~E_2~0_31) InVars {~E_2~0=v_~E_2~0_31} OutVars{~E_2~0=v_~E_2~0_31} AuxVars[] AssignedVars[] 16992#L700-3 [3818] L700-3-->L705-3: Formula: (< 0 v_~E_3~0_31) InVars {~E_3~0=v_~E_3~0_31} OutVars{~E_3~0=v_~E_3~0_31} AuxVars[] AssignedVars[] 17057#L705-3 [2688] L705-3-->L710-3: Formula: (and (= v_~E_4~0_29 1) (= 0 v_~E_4~0_30)) InVars {~E_4~0=v_~E_4~0_30} OutVars{~E_4~0=v_~E_4~0_29} AuxVars[] AssignedVars[~E_4~0] 16939#L710-3 [2515] L710-3-->L715-3: Formula: (and (= 0 v_~E_5~0_30) (= v_~E_5~0_29 1)) InVars {~E_5~0=v_~E_5~0_30} OutVars{~E_5~0=v_~E_5~0_29} AuxVars[] AssignedVars[~E_5~0] 16940#L715-3 [3048] L715-3-->L720-3: Formula: (and (= v_~E_6~0_29 1) (= 0 v_~E_6~0_30)) InVars {~E_6~0=v_~E_6~0_30} OutVars{~E_6~0=v_~E_6~0_29} AuxVars[] AssignedVars[~E_6~0] 16799#L720-3 [2388] L720-3-->L310-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_43, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_43, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_25|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_25|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_25|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_43, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_43, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_43, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_25|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_25|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_25|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_25|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_43, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_25|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_43, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_43} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 16800#L310-21 [2779] L310-21-->L311-7: Formula: (= v_~m_pc~0_23 1) InVars {~m_pc~0=v_~m_pc~0_23} OutVars{~m_pc~0=v_~m_pc~0_23} AuxVars[] AssignedVars[] 17080#L311-7 [2720] L311-7-->L321-7: Formula: (and (= v_~M_E~0_31 1) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_46 1)) InVars {~M_E~0=v_~M_E~0_31} OutVars{~M_E~0=v_~M_E~0_31, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_46} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 17081#L321-7 [4303] L321-7-->L815-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 17042#L815-21 [3897] L815-21-->L815-23: Formula: (and (> 0 v_ULTIMATE.start_activate_threads_~tmp~1_47) (= v_~m_st~0_20 0)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_47} OutVars{~m_st~0=v_~m_st~0_20, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_47} AuxVars[] AssignedVars[~m_st~0] 17023#L815-23 [2638] L815-23-->L329-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 17024#L329-21 [3911] L329-21-->L329-23: Formula: (< v_~t1_pc~0_24 1) InVars {~t1_pc~0=v_~t1_pc~0_24} OutVars{~t1_pc~0=v_~t1_pc~0_24} AuxVars[] AssignedVars[] 17220#L329-23 [3052] L329-23-->L340-7: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 17134#L340-7 [4310] L340-7-->L823-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 17135#L823-21 [2931] L823-21-->L823-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} AuxVars[] AssignedVars[] 17194#L823-23 [2934] L823-23-->L348-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_25|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 17196#L348-21 [3953] L348-21-->L348-23: Formula: (> 1 v_~t2_pc~0_24) InVars {~t2_pc~0=v_~t2_pc~0_24} OutVars{~t2_pc~0=v_~t2_pc~0_24} AuxVars[] AssignedVars[] 17301#L348-23 [3319] L348-23-->L359-7: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 17276#L359-7 [4317] L359-7-->L831-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 16917#L831-21 [2490] L831-21-->L831-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} AuxVars[] AssignedVars[] 16918#L831-23 [3197] L831-23-->L367-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_25|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 16828#L367-21 [3995] L367-21-->L367-23: Formula: (> v_~t3_pc~0_24 1) InVars {~t3_pc~0=v_~t3_pc~0_24} OutVars{~t3_pc~0=v_~t3_pc~0_24} AuxVars[] AssignedVars[] 16795#L367-23 [2385] L367-23-->L378-7: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 16796#L378-7 [4324] L378-7-->L839-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 16852#L839-21 [4023] L839-21-->L839-23: Formula: (and (= v_~t3_st~0_21 0) (> v_ULTIMATE.start_activate_threads_~tmp___2~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} OutVars{~t3_st~0=v_~t3_st~0_21, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} AuxVars[] AssignedVars[~t3_st~0] 17076#L839-23 [2722] L839-23-->L386-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_49, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 17003#L386-21 [4037] L386-21-->L386-23: Formula: (< 1 v_~t4_pc~0_24) InVars {~t4_pc~0=v_~t4_pc~0_24} OutVars{~t4_pc~0=v_~t4_pc~0_24} AuxVars[] AssignedVars[] 17004#L386-23 [2623] L386-23-->L397-7: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 17010#L397-7 [4331] L397-7-->L847-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 17039#L847-21 [4065] L847-21-->L847-23: Formula: (and (= v_~t4_st~0_22 0) (< v_ULTIMATE.start_activate_threads_~tmp___3~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47, ~t4_st~0=v_~t4_st~0_22} AuxVars[] AssignedVars[~t4_st~0] 17221#L847-23 [2983] L847-23-->L405-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_25|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 17185#L405-21 [2911] L405-21-->L406-7: Formula: (= v_~t5_pc~0_23 1) InVars {~t5_pc~0=v_~t5_pc~0_23} OutVars{~t5_pc~0=v_~t5_pc~0_23} AuxVars[] AssignedVars[] 17171#L406-7 [2874] L406-7-->L416-7: Formula: (and (= 1 v_~E_5~0_32) (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_52 1)) InVars {~E_5~0=v_~E_5~0_32} OutVars{~E_5~0=v_~E_5~0_32, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_52} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 17173#L416-7 [4338] L416-7-->L855-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 17190#L855-21 [3251] L855-21-->L855-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} AuxVars[] AssignedVars[] 17299#L855-23 [3257] L855-23-->L424-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_25|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 17286#L424-21 [3173] L424-21-->L425-7: Formula: (= 1 v_~t6_pc~0_23) InVars {~t6_pc~0=v_~t6_pc~0_23} OutVars{~t6_pc~0=v_~t6_pc~0_23} AuxVars[] AssignedVars[] 17268#L425-7 [3114] L425-7-->L435-7: Formula: (and (= 1 v_~E_6~0_32) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_52 1)) InVars {~E_6~0=v_~E_6~0_32} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_52, ~E_6~0=v_~E_6~0_32} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 16912#L435-7 [4340] L435-7-->L863-21: Formula: (and (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___5~0_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_35|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_41|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 16913#L863-21 [4135] L863-21-->L863-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___5~0_47 0) (= v_~t6_st~0_22 0)) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} OutVars{~t6_st~0=v_~t6_st~0_22, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} AuxVars[] AssignedVars[~t6_st~0] 16955#L863-23 [4137] L863-23-->L733-3: Formula: (< v_~M_E~0_35 1) InVars {~M_E~0=v_~M_E~0_35} OutVars{~M_E~0=v_~M_E~0_35} AuxVars[] AssignedVars[] 16956#L733-3 [3184] L733-3-->L738-3: Formula: (and (= v_~T1_E~0_15 1) (= v_~T1_E~0_14 2)) InVars {~T1_E~0=v_~T1_E~0_15} OutVars{~T1_E~0=v_~T1_E~0_14} AuxVars[] AssignedVars[~T1_E~0] 17215#L738-3 [4142] L738-3-->L743-3: Formula: (< 1 v_~T2_E~0_16) InVars {~T2_E~0=v_~T2_E~0_16} OutVars{~T2_E~0=v_~T2_E~0_16} AuxVars[] AssignedVars[] 16935#L743-3 [4143] L743-3-->L748-3: Formula: (< 1 v_~T3_E~0_16) InVars {~T3_E~0=v_~T3_E~0_16} OutVars{~T3_E~0=v_~T3_E~0_16} AuxVars[] AssignedVars[] 16936#L748-3 [4145] L748-3-->L753-3: Formula: (> v_~T4_E~0_16 1) InVars {~T4_E~0=v_~T4_E~0_16} OutVars{~T4_E~0=v_~T4_E~0_16} AuxVars[] AssignedVars[] 16793#L753-3 [4148] L753-3-->L758-3: Formula: (< 1 v_~T5_E~0_16) InVars {~T5_E~0=v_~T5_E~0_16} OutVars{~T5_E~0=v_~T5_E~0_16} AuxVars[] AssignedVars[] 16794#L758-3 [4149] L758-3-->L763-3: Formula: (> v_~T6_E~0_16 1) InVars {~T6_E~0=v_~T6_E~0_16} OutVars{~T6_E~0=v_~T6_E~0_16} AuxVars[] AssignedVars[] 16884#L763-3 [4151] L763-3-->L768-3: Formula: (< 1 v_~E_1~0_36) InVars {~E_1~0=v_~E_1~0_36} OutVars{~E_1~0=v_~E_1~0_36} AuxVars[] AssignedVars[] 16885#L768-3 [4154] L768-3-->L773-3: Formula: (< 1 v_~E_2~0_36) InVars {~E_2~0=v_~E_2~0_36} OutVars{~E_2~0=v_~E_2~0_36} AuxVars[] AssignedVars[] 17110#L773-3 [4156] L773-3-->L778-3: Formula: (< 1 v_~E_3~0_36) InVars {~E_3~0=v_~E_3~0_36} OutVars{~E_3~0=v_~E_3~0_36} AuxVars[] AssignedVars[] 17111#L778-3 [3308] L778-3-->L783-3: Formula: (and (= 1 v_~E_4~0_35) (= v_~E_4~0_34 2)) InVars {~E_4~0=v_~E_4~0_35} OutVars{~E_4~0=v_~E_4~0_34} AuxVars[] AssignedVars[~E_4~0] 17006#L783-3 [4160] L783-3-->L788-3: Formula: (< 1 v_~E_5~0_36) InVars {~E_5~0=v_~E_5~0_36} OutVars{~E_5~0=v_~E_5~0_36} AuxVars[] AssignedVars[] 17007#L788-3 [4161] L788-3-->L793-3: Formula: (> 1 v_~E_6~0_36) InVars {~E_6~0=v_~E_6~0_36} OutVars{~E_6~0=v_~E_6~0_36} AuxVars[] AssignedVars[] 17213#L793-3 [2966] L793-3-->L494-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_30} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 17175#L494-1 [2878] L494-1-->L531-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33 1) (= 0 v_~m_st~0_21)) InVars {~m_st~0=v_~m_st~0_21} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33, ~m_st~0=v_~m_st~0_21} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 16872#L531-1 [4341] L531-1-->L1033: Formula: (and (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp~3] 17097#L1033 [4169] L1033-->L1033-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_6) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} AuxVars[] AssignedVars[] 16842#L1033-1 [2919] L1033-1-->L494-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_3|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_6, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_exists_runnable_thread_~__retres1~7, ULTIMATE.start_stop_simulation_#res] 17176#L494-2 [2882] L494-2-->L531-2: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9 1) (= v_~m_st~0_6 0)) InVars {~m_st~0=v_~m_st~0_6} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9, ~m_st~0=v_~m_st~0_6} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 16876#L531-2 [4343] L531-2-->L988: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 17102#L988 [3240] L988-->L995: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 16838#L995 [4354] L995-->L1014-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_6|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_#t~ret17, ULTIMATE.start_stop_simulation_#res] 16839#L1014-1 [2020-06-22 00:13:10,304 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:10,304 INFO L82 PathProgramCache]: Analyzing trace with hash 873883554, now seen corresponding path program 1 times [2020-06-22 00:13:10,304 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:10,304 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:10,305 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:10,305 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:10,305 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:10,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:10,327 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:10,328 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:10,328 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-06-22 00:13:10,328 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-06-22 00:13:10,328 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:10,328 INFO L82 PathProgramCache]: Analyzing trace with hash -1937377123, now seen corresponding path program 1 times [2020-06-22 00:13:10,328 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:10,329 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:10,329 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:10,329 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:10,330 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:10,332 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:10,355 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:10,355 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:10,356 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2020-06-22 00:13:10,356 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-06-22 00:13:10,356 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-06-22 00:13:10,356 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-06-22 00:13:10,356 INFO L87 Difference]: Start difference. First operand 518 states and 1016 transitions. cyclomatic complexity: 499 Second operand 3 states. [2020-06-22 00:13:11,021 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-06-22 00:13:11,021 INFO L93 Difference]: Finished difference Result 528 states and 1008 transitions. [2020-06-22 00:13:11,022 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-06-22 00:13:11,022 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 528 states and 1008 transitions. [2020-06-22 00:13:11,024 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2020-06-22 00:13:11,027 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 528 states to 528 states and 1008 transitions. [2020-06-22 00:13:11,027 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 528 [2020-06-22 00:13:11,028 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 528 [2020-06-22 00:13:11,028 INFO L73 IsDeterministic]: Start isDeterministic. Operand 528 states and 1008 transitions. [2020-06-22 00:13:11,028 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-06-22 00:13:11,028 INFO L706 BuchiCegarLoop]: Abstraction has 528 states and 1008 transitions. [2020-06-22 00:13:11,029 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 528 states and 1008 transitions. [2020-06-22 00:13:11,035 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 528 to 518. [2020-06-22 00:13:11,035 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 518 states. [2020-06-22 00:13:11,036 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 518 states to 518 states and 990 transitions. [2020-06-22 00:13:11,036 INFO L729 BuchiCegarLoop]: Abstraction has 518 states and 990 transitions. [2020-06-22 00:13:11,036 INFO L609 BuchiCegarLoop]: Abstraction has 518 states and 990 transitions. [2020-06-22 00:13:11,037 INFO L442 BuchiCegarLoop]: ======== Iteration 18============ [2020-06-22 00:13:11,037 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 518 states and 990 transitions. [2020-06-22 00:13:11,038 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 442 [2020-06-22 00:13:11,038 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-06-22 00:13:11,038 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-06-22 00:13:11,039 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:11,039 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:11,040 INFO L794 eck$LassoCheckResult]: Stem: 18281#ULTIMATE.startENTRY [4266] ULTIMATE.startENTRY-->L444: Formula: (and (= 1 v_~t6_i~0_7) (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~M_E~0_37 2) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 0 v_~t6_pc~0_26) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_6~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= v_~T6_E~0_18 2) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~t6_st~0_24) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t6_pc~0=v_~t6_pc~0_26, ~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~T6_E~0=v_~T6_E~0_18, ~M_E~0=v_~M_E~0_37, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ~T4_E~0=v_~T4_E~0_18, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_4|, ~t6_i~0=v_~t6_i~0_7, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ULTIMATE.start_main_~__retres1~8=v_ULTIMATE.start_main_~__retres1~8_6, ~T2_E~0=v_~T2_E~0_18, ~t6_st~0=v_~t6_st~0_24, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_6~0=v_~E_6~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t6_pc~0, ~t5_i~0, ~t1_pc~0, ~t5_st~0, ~T6_E~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ~T4_E~0, ULTIMATE.start_start_simulation_#t~ret17, ~t6_i~0, ~t2_st~0, ~t2_pc~0, ULTIMATE.start_main_~__retres1~8, ~T2_E~0, ~t6_st~0, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_6~0, ULTIMATE.start_main_#res, ~E_2~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 17931#L444 [2453] L444-->L451-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 17932#L451-1 [3030] L451-1-->L456-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 18017#L456-1 [2574] L456-1-->L461-1: Formula: (and (= v_~t2_st~0_2 0) (= 1 v_~t2_i~0_3)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_2} AuxVars[] AssignedVars[~t2_st~0] 18018#L461-1 [2880] L461-1-->L466-1: Formula: (and (= v_~t3_st~0_3 0) (= v_~t3_i~0_3 1)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_3, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 17933#L466-1 [2457] L466-1-->L471-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 17934#L471-1 [3209] L471-1-->L476-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 18157#L476-1 [2761] L476-1-->L481-1: Formula: (and (= 1 v_~t6_i~0_3) (= v_~t6_st~0_4 0)) InVars {~t6_i~0=v_~t6_i~0_3} OutVars{~t6_st~0=v_~t6_st~0_4, ~t6_i~0=v_~t6_i~0_3} AuxVars[] AssignedVars[~t6_st~0] 18158#L481-1 [3652] L481-1-->L660-1: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 18292#L660-1 [3654] L660-1-->L665-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 17851#L665-1 [3655] L665-1-->L670-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 17852#L670-1 [3658] L670-1-->L675-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 17940#L675-1 [3659] L675-1-->L680-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 17941#L680-1 [3661] L680-1-->L685-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 18166#L685-1 [3663] L685-1-->L690-1: Formula: (< 0 v_~T6_E~0_4) InVars {~T6_E~0=v_~T6_E~0_4} OutVars{~T6_E~0=v_~T6_E~0_4} AuxVars[] AssignedVars[] 18167#L690-1 [3665] L690-1-->L695-1: Formula: (> v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 18062#L695-1 [3668] L695-1-->L700-1: Formula: (> v_~E_2~0_6 0) InVars {~E_2~0=v_~E_2~0_6} OutVars{~E_2~0=v_~E_2~0_6} AuxVars[] AssignedVars[] 18063#L700-1 [3670] L700-1-->L705-1: Formula: (> v_~E_3~0_6 0) InVars {~E_3~0=v_~E_3~0_6} OutVars{~E_3~0=v_~E_3~0_6} AuxVars[] AssignedVars[] 18268#L705-1 [3672] L705-1-->L710-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 18001#L710-1 [3674] L710-1-->L715-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 18002#L715-1 [3676] L715-1-->L720-1: Formula: (< v_~E_6~0_4 0) InVars {~E_6~0=v_~E_6~0_4} OutVars{~E_6~0=v_~E_6~0_4} AuxVars[] AssignedVars[] 17885#L720-1 [2412] L720-1-->L310: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_7, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_4|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_4|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_7, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_4, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_4, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_2|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_2|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_4|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_4|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_7, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_2|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_4} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 17886#L310 [2597] L310-->L311: Formula: (= v_~m_pc~0_4 1) InVars {~m_pc~0=v_~m_pc~0_4} OutVars{~m_pc~0=v_~m_pc~0_4} AuxVars[] AssignedVars[] 18033#L311 [2732] L311-->L321: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_10 1) (= 1 v_~M_E~0_8)) InVars {~M_E~0=v_~M_E~0_8} OutVars{~M_E~0=v_~M_E~0_8, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_10} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 18031#L321 [4267] L321-->L815: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 18032#L815 [3682] L815-->L815-2: Formula: (and (= v_~m_st~0_5 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_11)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} OutVars{~m_st~0=v_~m_st~0_5, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} AuxVars[] AssignedVars[~m_st~0] 18264#L815-2 [2961] L815-2-->L329: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 18198#L329 [3684] L329-->L329-2: Formula: (> v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 18200#L329-2 [2861] L329-2-->L340: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 18196#L340 [4268] L340-->L823: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 18197#L823 [3688] L823-->L823-2: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___0~0_11 0) (= v_~t1_st~0_5 0)) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_11} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_11, ~t1_st~0=v_~t1_st~0_5} AuxVars[] AssignedVars[~t1_st~0] 18350#L823-2 [3235] L823-2-->L348: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_4|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 18334#L348 [3690] L348-->L348-2: Formula: (< v_~t2_pc~0_5 1) InVars {~t2_pc~0=v_~t2_pc~0_5} OutVars{~t2_pc~0=v_~t2_pc~0_5} AuxVars[] AssignedVars[] 18336#L348-2 [3153] L348-2-->L359: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 18333#L359 [4269] L359-->L831: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 18008#L831 [3694] L831-->L831-2: Formula: (and (= v_~t2_st~0_5 0) (> v_ULTIMATE.start_activate_threads_~tmp___1~0_11 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_11} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_11, ~t2_st~0=v_~t2_st~0_5} AuxVars[] AssignedVars[~t2_st~0] 17996#L831-2 [2520] L831-2-->L367: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_4|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 17936#L367 [3695] L367-->L367-2: Formula: (> 1 v_~t3_pc~0_5) InVars {~t3_pc~0=v_~t3_pc~0_5} OutVars{~t3_pc~0=v_~t3_pc~0_5} AuxVars[] AssignedVars[] 17914#L367-2 [2438] L367-2-->L378: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 17915#L378 [4270] L378-->L839: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 17935#L839 [2791] L839-->L839-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} AuxVars[] AssignedVars[] 18173#L839-2 [2794] L839-2-->L386: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_7, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 18103#L386 [2675] L386-->L387: Formula: (= v_~t4_pc~0_4 1) InVars {~t4_pc~0=v_~t4_pc~0_4} OutVars{~t4_pc~0=v_~t4_pc~0_4} AuxVars[] AssignedVars[] 18022#L387 [2588] L387-->L397: Formula: (and (= v_~E_4~0_7 1) (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_10 1)) InVars {~E_4~0=v_~E_4~0_7} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_10, ~E_4~0=v_~E_4~0_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 18024#L397 [4271] L397-->L847: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 18102#L847 [3084] L847-->L847-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} AuxVars[] AssignedVars[] 18296#L847-2 [3064] L847-2-->L405: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_4|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 18297#L405 [3708] L405-->L405-2: Formula: (> 1 v_~t5_pc~0_5) InVars {~t5_pc~0=v_~t5_pc~0_5} OutVars{~t5_pc~0=v_~t5_pc~0_5} AuxVars[] AssignedVars[] 18226#L405-2 [2940] L405-2-->L416: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 18254#L416 [4272] L416-->L855: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 18303#L855 [3711] L855-->L855-2: Formula: (and (> v_ULTIMATE.start_activate_threads_~tmp___4~0_11 0) (= v_~t5_st~0_7 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_11} OutVars{~t5_st~0=v_~t5_st~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_11} AuxVars[] AssignedVars[~t5_st~0] 18304#L855-2 [3093] L855-2-->L424: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_4|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 17980#L424 [3714] L424-->L424-2: Formula: (> v_~t6_pc~0_5 1) InVars {~t6_pc~0=v_~t6_pc~0_5} OutVars{~t6_pc~0=v_~t6_pc~0_5} AuxVars[] AssignedVars[] 17981#L424-2 [2503] L424-2-->L435: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 17979#L435 [4273] L435-->L863: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___5~0_49 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_28|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_28|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 17901#L863 [2425] L863-->L863-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___5~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} AuxVars[] AssignedVars[] 17875#L863-2 [3720] L863-2-->L733-1: Formula: (< v_~M_E~0_15 1) InVars {~M_E~0=v_~M_E~0_15} OutVars{~M_E~0=v_~M_E~0_15} AuxVars[] AssignedVars[] 17876#L733-1 [3722] L733-1-->L738-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 18266#L738-1 [3723] L738-1-->L743-1: Formula: (< 1 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 17999#L743-1 [3726] L743-1-->L748-1: Formula: (< 1 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 18000#L748-1 [3728] L748-1-->L753-1: Formula: (> v_~T4_E~0_10 1) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 17880#L753-1 [3729] L753-1-->L758-1: Formula: (< 1 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 17881#L758-1 [3732] L758-1-->L763-1: Formula: (< v_~T6_E~0_10 1) InVars {~T6_E~0=v_~T6_E~0_10} OutVars{~T6_E~0=v_~T6_E~0_10} AuxVars[] AssignedVars[] 17952#L763-1 [3733] L763-1-->L768-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 17953#L768-1 [3736] L768-1-->L773-1: Formula: (< 1 v_~E_2~0_14) InVars {~E_2~0=v_~E_2~0_14} OutVars{~E_2~0=v_~E_2~0_14} AuxVars[] AssignedVars[] 18162#L773-1 [3737] L773-1-->L778-1: Formula: (< 1 v_~E_3~0_14) InVars {~E_3~0=v_~E_3~0_14} OutVars{~E_3~0=v_~E_3~0_14} AuxVars[] AssignedVars[] 18163#L778-1 [3740] L778-1-->L783-1: Formula: (< 1 v_~E_4~0_14) InVars {~E_4~0=v_~E_4~0_14} OutVars{~E_4~0=v_~E_4~0_14} AuxVars[] AssignedVars[] 18055#L783-1 [3741] L783-1-->L788-1: Formula: (< 1 v_~E_5~0_14) InVars {~E_5~0=v_~E_5~0_14} OutVars{~E_5~0=v_~E_5~0_14} AuxVars[] AssignedVars[] 18056#L788-1 [3743] L788-1-->L1014-1: Formula: (> 1 v_~E_6~0_14) InVars {~E_6~0=v_~E_6~0_14} OutVars{~E_6~0=v_~E_6~0_14} AuxVars[] AssignedVars[] 17893#L1014-1 [2020-06-22 00:13:11,041 INFO L796 eck$LassoCheckResult]: Loop: 17893#L1014-1 [4274] L1014-1-->L635: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp_ndt_7~0=v_ULTIMATE.start_eval_~tmp_ndt_7~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp_ndt_7~0] 17855#L635 [4275] L635-->L494: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_37} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 18222#L494 [2876] L494-->L531: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21 1) (= v_~m_st~0_8 0)) InVars {~m_st~0=v_~m_st~0_8} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21, ~m_st~0=v_~m_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 17924#L531 [4276] L531-->L546: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 18150#L546 [4278] L546-->L660-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 18293#L660-2 [3747] L660-2-->L660-4: Formula: (> v_~M_E~0_30 0) InVars {~M_E~0=v_~M_E~0_30} OutVars{~M_E~0=v_~M_E~0_30} AuxVars[] AssignedVars[] 18294#L660-4 [3058] L660-4-->L665-3: Formula: (and (= v_~T1_E~0_11 1) (= v_~T1_E~0_12 0)) InVars {~T1_E~0=v_~T1_E~0_12} OutVars{~T1_E~0=v_~T1_E~0_11} AuxVars[] AssignedVars[~T1_E~0] 17865#L665-3 [3756] L665-3-->L670-3: Formula: (< 0 v_~T2_E~0_13) InVars {~T2_E~0=v_~T2_E~0_13} OutVars{~T2_E~0=v_~T2_E~0_13} AuxVars[] AssignedVars[] 17866#L670-3 [3762] L670-3-->L675-3: Formula: (< 0 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 17942#L675-3 [3768] L675-3-->L680-3: Formula: (> v_~T4_E~0_13 0) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 17943#L680-3 [3776] L680-3-->L685-3: Formula: (< 0 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 18169#L685-3 [3785] L685-3-->L690-3: Formula: (> v_~T6_E~0_13 0) InVars {~T6_E~0=v_~T6_E~0_13} OutVars{~T6_E~0=v_~T6_E~0_13} AuxVars[] AssignedVars[] 18170#L690-3 [3795] L690-3-->L695-3: Formula: (< 0 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 18048#L695-3 [3805] L695-3-->L700-3: Formula: (< 0 v_~E_2~0_31) InVars {~E_2~0=v_~E_2~0_31} OutVars{~E_2~0=v_~E_2~0_31} AuxVars[] AssignedVars[] 18049#L700-3 [3818] L700-3-->L705-3: Formula: (< 0 v_~E_3~0_31) InVars {~E_3~0=v_~E_3~0_31} OutVars{~E_3~0=v_~E_3~0_31} AuxVars[] AssignedVars[] 18111#L705-3 [2688] L705-3-->L710-3: Formula: (and (= v_~E_4~0_29 1) (= 0 v_~E_4~0_30)) InVars {~E_4~0=v_~E_4~0_30} OutVars{~E_4~0=v_~E_4~0_29} AuxVars[] AssignedVars[~E_4~0] 17993#L710-3 [3844] L710-3-->L715-3: Formula: (< 0 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 17994#L715-3 [3048] L715-3-->L720-3: Formula: (and (= v_~E_6~0_29 1) (= 0 v_~E_6~0_30)) InVars {~E_6~0=v_~E_6~0_30} OutVars{~E_6~0=v_~E_6~0_29} AuxVars[] AssignedVars[~E_6~0] 17856#L720-3 [2388] L720-3-->L310-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_43, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_43, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_25|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_25|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_25|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_43, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_43, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_43, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_25|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_25|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_25|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_25|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_43, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_25|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_43, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_43} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 17857#L310-21 [2779] L310-21-->L311-7: Formula: (= v_~m_pc~0_23 1) InVars {~m_pc~0=v_~m_pc~0_23} OutVars{~m_pc~0=v_~m_pc~0_23} AuxVars[] AssignedVars[] 18134#L311-7 [2720] L311-7-->L321-7: Formula: (and (= v_~M_E~0_31 1) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_46 1)) InVars {~M_E~0=v_~M_E~0_31} OutVars{~M_E~0=v_~M_E~0_31, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_46} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 18135#L321-7 [4303] L321-7-->L815-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 18096#L815-21 [3897] L815-21-->L815-23: Formula: (and (> 0 v_ULTIMATE.start_activate_threads_~tmp~1_47) (= v_~m_st~0_20 0)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_47} OutVars{~m_st~0=v_~m_st~0_20, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_47} AuxVars[] AssignedVars[~m_st~0] 18077#L815-23 [2638] L815-23-->L329-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 18078#L329-21 [3911] L329-21-->L329-23: Formula: (< v_~t1_pc~0_24 1) InVars {~t1_pc~0=v_~t1_pc~0_24} OutVars{~t1_pc~0=v_~t1_pc~0_24} AuxVars[] AssignedVars[] 18274#L329-23 [3052] L329-23-->L340-7: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 18187#L340-7 [4310] L340-7-->L823-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 18188#L823-21 [2931] L823-21-->L823-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} AuxVars[] AssignedVars[] 18245#L823-23 [2934] L823-23-->L348-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_25|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 18247#L348-21 [3953] L348-21-->L348-23: Formula: (> 1 v_~t2_pc~0_24) InVars {~t2_pc~0=v_~t2_pc~0_24} OutVars{~t2_pc~0=v_~t2_pc~0_24} AuxVars[] AssignedVars[] 18355#L348-23 [3319] L348-23-->L359-7: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 18330#L359-7 [4317] L359-7-->L831-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 17971#L831-21 [2490] L831-21-->L831-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} AuxVars[] AssignedVars[] 17972#L831-23 [3197] L831-23-->L367-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_25|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 17882#L367-21 [3995] L367-21-->L367-23: Formula: (> v_~t3_pc~0_24 1) InVars {~t3_pc~0=v_~t3_pc~0_24} OutVars{~t3_pc~0=v_~t3_pc~0_24} AuxVars[] AssignedVars[] 17849#L367-23 [2385] L367-23-->L378-7: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 17850#L378-7 [4324] L378-7-->L839-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 17906#L839-21 [4023] L839-21-->L839-23: Formula: (and (= v_~t3_st~0_21 0) (> v_ULTIMATE.start_activate_threads_~tmp___2~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} OutVars{~t3_st~0=v_~t3_st~0_21, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} AuxVars[] AssignedVars[~t3_st~0] 18130#L839-23 [2722] L839-23-->L386-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_49, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 18057#L386-21 [4037] L386-21-->L386-23: Formula: (< 1 v_~t4_pc~0_24) InVars {~t4_pc~0=v_~t4_pc~0_24} OutVars{~t4_pc~0=v_~t4_pc~0_24} AuxVars[] AssignedVars[] 18058#L386-23 [2623] L386-23-->L397-7: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 18064#L397-7 [4331] L397-7-->L847-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 18093#L847-21 [4065] L847-21-->L847-23: Formula: (and (= v_~t4_st~0_22 0) (< v_ULTIMATE.start_activate_threads_~tmp___3~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47, ~t4_st~0=v_~t4_st~0_22} AuxVars[] AssignedVars[~t4_st~0] 18275#L847-23 [2983] L847-23-->L405-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_25|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 18234#L405-21 [4080] L405-21-->L405-23: Formula: (> v_~t5_pc~0_24 1) InVars {~t5_pc~0=v_~t5_pc~0_24} OutVars{~t5_pc~0=v_~t5_pc~0_24} AuxVars[] AssignedVars[] 18221#L405-23 [2891] L405-23-->L416-7: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 18229#L416-7 [4338] L416-7-->L855-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 18240#L855-21 [3251] L855-21-->L855-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} AuxVars[] AssignedVars[] 18353#L855-23 [3257] L855-23-->L424-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_25|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 18340#L424-21 [3173] L424-21-->L425-7: Formula: (= 1 v_~t6_pc~0_23) InVars {~t6_pc~0=v_~t6_pc~0_23} OutVars{~t6_pc~0=v_~t6_pc~0_23} AuxVars[] AssignedVars[] 18322#L425-7 [3114] L425-7-->L435-7: Formula: (and (= 1 v_~E_6~0_32) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_52 1)) InVars {~E_6~0=v_~E_6~0_32} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_52, ~E_6~0=v_~E_6~0_32} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 17966#L435-7 [4340] L435-7-->L863-21: Formula: (and (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___5~0_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_35|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_41|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 17967#L863-21 [4135] L863-21-->L863-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___5~0_47 0) (= v_~t6_st~0_22 0)) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} OutVars{~t6_st~0=v_~t6_st~0_22, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} AuxVars[] AssignedVars[~t6_st~0] 18009#L863-23 [4137] L863-23-->L733-3: Formula: (< v_~M_E~0_35 1) InVars {~M_E~0=v_~M_E~0_35} OutVars{~M_E~0=v_~M_E~0_35} AuxVars[] AssignedVars[] 18010#L733-3 [3184] L733-3-->L738-3: Formula: (and (= v_~T1_E~0_15 1) (= v_~T1_E~0_14 2)) InVars {~T1_E~0=v_~T1_E~0_15} OutVars{~T1_E~0=v_~T1_E~0_14} AuxVars[] AssignedVars[~T1_E~0] 18269#L738-3 [4142] L738-3-->L743-3: Formula: (< 1 v_~T2_E~0_16) InVars {~T2_E~0=v_~T2_E~0_16} OutVars{~T2_E~0=v_~T2_E~0_16} AuxVars[] AssignedVars[] 17989#L743-3 [4143] L743-3-->L748-3: Formula: (< 1 v_~T3_E~0_16) InVars {~T3_E~0=v_~T3_E~0_16} OutVars{~T3_E~0=v_~T3_E~0_16} AuxVars[] AssignedVars[] 17990#L748-3 [4145] L748-3-->L753-3: Formula: (> v_~T4_E~0_16 1) InVars {~T4_E~0=v_~T4_E~0_16} OutVars{~T4_E~0=v_~T4_E~0_16} AuxVars[] AssignedVars[] 17847#L753-3 [4148] L753-3-->L758-3: Formula: (< 1 v_~T5_E~0_16) InVars {~T5_E~0=v_~T5_E~0_16} OutVars{~T5_E~0=v_~T5_E~0_16} AuxVars[] AssignedVars[] 17848#L758-3 [4149] L758-3-->L763-3: Formula: (> v_~T6_E~0_16 1) InVars {~T6_E~0=v_~T6_E~0_16} OutVars{~T6_E~0=v_~T6_E~0_16} AuxVars[] AssignedVars[] 17938#L763-3 [4151] L763-3-->L768-3: Formula: (< 1 v_~E_1~0_36) InVars {~E_1~0=v_~E_1~0_36} OutVars{~E_1~0=v_~E_1~0_36} AuxVars[] AssignedVars[] 17939#L768-3 [4154] L768-3-->L773-3: Formula: (< 1 v_~E_2~0_36) InVars {~E_2~0=v_~E_2~0_36} OutVars{~E_2~0=v_~E_2~0_36} AuxVars[] AssignedVars[] 18164#L773-3 [4156] L773-3-->L778-3: Formula: (< 1 v_~E_3~0_36) InVars {~E_3~0=v_~E_3~0_36} OutVars{~E_3~0=v_~E_3~0_36} AuxVars[] AssignedVars[] 18165#L778-3 [3308] L778-3-->L783-3: Formula: (and (= 1 v_~E_4~0_35) (= v_~E_4~0_34 2)) InVars {~E_4~0=v_~E_4~0_35} OutVars{~E_4~0=v_~E_4~0_34} AuxVars[] AssignedVars[~E_4~0] 18060#L783-3 [4160] L783-3-->L788-3: Formula: (< 1 v_~E_5~0_36) InVars {~E_5~0=v_~E_5~0_36} OutVars{~E_5~0=v_~E_5~0_36} AuxVars[] AssignedVars[] 18061#L788-3 [4161] L788-3-->L793-3: Formula: (> 1 v_~E_6~0_36) InVars {~E_6~0=v_~E_6~0_36} OutVars{~E_6~0=v_~E_6~0_36} AuxVars[] AssignedVars[] 18267#L793-3 [2966] L793-3-->L494-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_30} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 18223#L494-1 [2878] L494-1-->L531-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33 1) (= 0 v_~m_st~0_21)) InVars {~m_st~0=v_~m_st~0_21} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33, ~m_st~0=v_~m_st~0_21} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 17926#L531-1 [4341] L531-1-->L1033: Formula: (and (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp~3] 18151#L1033 [4169] L1033-->L1033-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_6) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} AuxVars[] AssignedVars[] 17896#L1033-1 [2919] L1033-1-->L494-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_3|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_6, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_exists_runnable_thread_~__retres1~7, ULTIMATE.start_stop_simulation_#res] 18224#L494-2 [2882] L494-2-->L531-2: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9 1) (= v_~m_st~0_6 0)) InVars {~m_st~0=v_~m_st~0_6} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9, ~m_st~0=v_~m_st~0_6} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 17930#L531-2 [4343] L531-2-->L988: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 18156#L988 [3240] L988-->L995: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 17892#L995 [4354] L995-->L1014-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_6|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_#t~ret17, ULTIMATE.start_stop_simulation_#res] 17893#L1014-1 [2020-06-22 00:13:11,042 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:11,042 INFO L82 PathProgramCache]: Analyzing trace with hash -628817754, now seen corresponding path program 1 times [2020-06-22 00:13:11,042 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:11,042 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:11,043 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:11,043 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:11,043 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:11,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:11,065 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:11,066 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:11,066 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-06-22 00:13:11,066 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-06-22 00:13:11,066 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:11,066 INFO L82 PathProgramCache]: Analyzing trace with hash -758922002, now seen corresponding path program 1 times [2020-06-22 00:13:11,066 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:11,067 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:11,067 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:11,067 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:11,068 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:11,070 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:11,104 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:11,105 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:11,105 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2020-06-22 00:13:11,105 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-06-22 00:13:11,105 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-06-22 00:13:11,105 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-06-22 00:13:11,106 INFO L87 Difference]: Start difference. First operand 518 states and 990 transitions. cyclomatic complexity: 473 Second operand 3 states. [2020-06-22 00:13:11,646 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-06-22 00:13:11,646 INFO L93 Difference]: Finished difference Result 522 states and 970 transitions. [2020-06-22 00:13:11,647 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-06-22 00:13:11,647 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 522 states and 970 transitions. [2020-06-22 00:13:11,649 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 446 [2020-06-22 00:13:11,652 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 522 states to 522 states and 970 transitions. [2020-06-22 00:13:11,652 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 522 [2020-06-22 00:13:11,652 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 522 [2020-06-22 00:13:11,653 INFO L73 IsDeterministic]: Start isDeterministic. Operand 522 states and 970 transitions. [2020-06-22 00:13:11,653 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-06-22 00:13:11,653 INFO L706 BuchiCegarLoop]: Abstraction has 522 states and 970 transitions. [2020-06-22 00:13:11,654 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 522 states and 970 transitions. [2020-06-22 00:13:11,659 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 522 to 518. [2020-06-22 00:13:11,660 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 518 states. [2020-06-22 00:13:11,661 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 518 states to 518 states and 964 transitions. [2020-06-22 00:13:11,661 INFO L729 BuchiCegarLoop]: Abstraction has 518 states and 964 transitions. [2020-06-22 00:13:11,661 INFO L609 BuchiCegarLoop]: Abstraction has 518 states and 964 transitions. [2020-06-22 00:13:11,661 INFO L442 BuchiCegarLoop]: ======== Iteration 19============ [2020-06-22 00:13:11,661 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 518 states and 964 transitions. [2020-06-22 00:13:11,662 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 442 [2020-06-22 00:13:11,662 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-06-22 00:13:11,663 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-06-22 00:13:11,663 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:11,664 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:11,665 INFO L794 eck$LassoCheckResult]: Stem: 19329#ULTIMATE.startENTRY [4266] ULTIMATE.startENTRY-->L444: Formula: (and (= 1 v_~t6_i~0_7) (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~M_E~0_37 2) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 0 v_~t6_pc~0_26) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_6~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= v_~T6_E~0_18 2) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~t6_st~0_24) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t6_pc~0=v_~t6_pc~0_26, ~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~T6_E~0=v_~T6_E~0_18, ~M_E~0=v_~M_E~0_37, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ~T4_E~0=v_~T4_E~0_18, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_4|, ~t6_i~0=v_~t6_i~0_7, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ULTIMATE.start_main_~__retres1~8=v_ULTIMATE.start_main_~__retres1~8_6, ~T2_E~0=v_~T2_E~0_18, ~t6_st~0=v_~t6_st~0_24, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_6~0=v_~E_6~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t6_pc~0, ~t5_i~0, ~t1_pc~0, ~t5_st~0, ~T6_E~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ~T4_E~0, ULTIMATE.start_start_simulation_#t~ret17, ~t6_i~0, ~t2_st~0, ~t2_pc~0, ULTIMATE.start_main_~__retres1~8, ~T2_E~0, ~t6_st~0, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_6~0, ULTIMATE.start_main_#res, ~E_2~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 18979#L444 [2453] L444-->L451-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 18980#L451-1 [3030] L451-1-->L456-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 19065#L456-1 [2574] L456-1-->L461-1: Formula: (and (= v_~t2_st~0_2 0) (= 1 v_~t2_i~0_3)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_2} AuxVars[] AssignedVars[~t2_st~0] 19066#L461-1 [2880] L461-1-->L466-1: Formula: (and (= v_~t3_st~0_3 0) (= v_~t3_i~0_3 1)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_3, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 18981#L466-1 [2457] L466-1-->L471-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 18982#L471-1 [3209] L471-1-->L476-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 19205#L476-1 [2761] L476-1-->L481-1: Formula: (and (= 1 v_~t6_i~0_3) (= v_~t6_st~0_4 0)) InVars {~t6_i~0=v_~t6_i~0_3} OutVars{~t6_st~0=v_~t6_st~0_4, ~t6_i~0=v_~t6_i~0_3} AuxVars[] AssignedVars[~t6_st~0] 19206#L481-1 [3652] L481-1-->L660-1: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 19340#L660-1 [3654] L660-1-->L665-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 18899#L665-1 [3655] L665-1-->L670-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 18900#L670-1 [3658] L670-1-->L675-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 18988#L675-1 [3659] L675-1-->L680-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 18989#L680-1 [3661] L680-1-->L685-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 19214#L685-1 [3663] L685-1-->L690-1: Formula: (< 0 v_~T6_E~0_4) InVars {~T6_E~0=v_~T6_E~0_4} OutVars{~T6_E~0=v_~T6_E~0_4} AuxVars[] AssignedVars[] 19215#L690-1 [3665] L690-1-->L695-1: Formula: (> v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 19110#L695-1 [3668] L695-1-->L700-1: Formula: (> v_~E_2~0_6 0) InVars {~E_2~0=v_~E_2~0_6} OutVars{~E_2~0=v_~E_2~0_6} AuxVars[] AssignedVars[] 19111#L700-1 [3670] L700-1-->L705-1: Formula: (> v_~E_3~0_6 0) InVars {~E_3~0=v_~E_3~0_6} OutVars{~E_3~0=v_~E_3~0_6} AuxVars[] AssignedVars[] 19316#L705-1 [3672] L705-1-->L710-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 19049#L710-1 [3674] L710-1-->L715-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 19050#L715-1 [3675] L715-1-->L720-1: Formula: (> v_~E_6~0_4 0) InVars {~E_6~0=v_~E_6~0_4} OutVars{~E_6~0=v_~E_6~0_4} AuxVars[] AssignedVars[] 18933#L720-1 [2412] L720-1-->L310: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_7, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_4|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_4|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_7, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_4, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_4, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_2|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_2|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_4|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_4|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_7, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_2|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_4} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 18934#L310 [2597] L310-->L311: Formula: (= v_~m_pc~0_4 1) InVars {~m_pc~0=v_~m_pc~0_4} OutVars{~m_pc~0=v_~m_pc~0_4} AuxVars[] AssignedVars[] 19081#L311 [2732] L311-->L321: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_10 1) (= 1 v_~M_E~0_8)) InVars {~M_E~0=v_~M_E~0_8} OutVars{~M_E~0=v_~M_E~0_8, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_10} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 19079#L321 [4267] L321-->L815: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 19080#L815 [3682] L815-->L815-2: Formula: (and (= v_~m_st~0_5 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_11)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} OutVars{~m_st~0=v_~m_st~0_5, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} AuxVars[] AssignedVars[~m_st~0] 19312#L815-2 [2961] L815-2-->L329: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 19246#L329 [3684] L329-->L329-2: Formula: (> v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 19248#L329-2 [2861] L329-2-->L340: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 19244#L340 [4268] L340-->L823: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 19245#L823 [3688] L823-->L823-2: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___0~0_11 0) (= v_~t1_st~0_5 0)) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_11} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_11, ~t1_st~0=v_~t1_st~0_5} AuxVars[] AssignedVars[~t1_st~0] 19398#L823-2 [3235] L823-2-->L348: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_4|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 19382#L348 [3690] L348-->L348-2: Formula: (< v_~t2_pc~0_5 1) InVars {~t2_pc~0=v_~t2_pc~0_5} OutVars{~t2_pc~0=v_~t2_pc~0_5} AuxVars[] AssignedVars[] 19384#L348-2 [3153] L348-2-->L359: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 19381#L359 [4269] L359-->L831: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 19056#L831 [3694] L831-->L831-2: Formula: (and (= v_~t2_st~0_5 0) (> v_ULTIMATE.start_activate_threads_~tmp___1~0_11 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_11} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_11, ~t2_st~0=v_~t2_st~0_5} AuxVars[] AssignedVars[~t2_st~0] 19044#L831-2 [2520] L831-2-->L367: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_4|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 18984#L367 [3695] L367-->L367-2: Formula: (> 1 v_~t3_pc~0_5) InVars {~t3_pc~0=v_~t3_pc~0_5} OutVars{~t3_pc~0=v_~t3_pc~0_5} AuxVars[] AssignedVars[] 18962#L367-2 [2438] L367-2-->L378: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 18963#L378 [4270] L378-->L839: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 18983#L839 [2791] L839-->L839-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} AuxVars[] AssignedVars[] 19221#L839-2 [2794] L839-2-->L386: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_7, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 19151#L386 [2675] L386-->L387: Formula: (= v_~t4_pc~0_4 1) InVars {~t4_pc~0=v_~t4_pc~0_4} OutVars{~t4_pc~0=v_~t4_pc~0_4} AuxVars[] AssignedVars[] 19070#L387 [2588] L387-->L397: Formula: (and (= v_~E_4~0_7 1) (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_10 1)) InVars {~E_4~0=v_~E_4~0_7} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_10, ~E_4~0=v_~E_4~0_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 19072#L397 [4271] L397-->L847: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 19150#L847 [3084] L847-->L847-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} AuxVars[] AssignedVars[] 19344#L847-2 [3064] L847-2-->L405: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_4|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 19345#L405 [3708] L405-->L405-2: Formula: (> 1 v_~t5_pc~0_5) InVars {~t5_pc~0=v_~t5_pc~0_5} OutVars{~t5_pc~0=v_~t5_pc~0_5} AuxVars[] AssignedVars[] 19274#L405-2 [2940] L405-2-->L416: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 19302#L416 [4272] L416-->L855: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 19351#L855 [3711] L855-->L855-2: Formula: (and (> v_ULTIMATE.start_activate_threads_~tmp___4~0_11 0) (= v_~t5_st~0_7 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_11} OutVars{~t5_st~0=v_~t5_st~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_11} AuxVars[] AssignedVars[~t5_st~0] 19352#L855-2 [3093] L855-2-->L424: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_4|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 19028#L424 [3714] L424-->L424-2: Formula: (> v_~t6_pc~0_5 1) InVars {~t6_pc~0=v_~t6_pc~0_5} OutVars{~t6_pc~0=v_~t6_pc~0_5} AuxVars[] AssignedVars[] 19029#L424-2 [2503] L424-2-->L435: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 19025#L435 [4273] L435-->L863: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___5~0_49 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_28|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_28|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 18947#L863 [2425] L863-->L863-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___5~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} AuxVars[] AssignedVars[] 18920#L863-2 [3720] L863-2-->L733-1: Formula: (< v_~M_E~0_15 1) InVars {~M_E~0=v_~M_E~0_15} OutVars{~M_E~0=v_~M_E~0_15} AuxVars[] AssignedVars[] 18921#L733-1 [3722] L733-1-->L738-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 19314#L738-1 [3723] L738-1-->L743-1: Formula: (< 1 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 19047#L743-1 [3726] L743-1-->L748-1: Formula: (< 1 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 19048#L748-1 [3728] L748-1-->L753-1: Formula: (> v_~T4_E~0_10 1) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 18928#L753-1 [3729] L753-1-->L758-1: Formula: (< 1 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 18929#L758-1 [3732] L758-1-->L763-1: Formula: (< v_~T6_E~0_10 1) InVars {~T6_E~0=v_~T6_E~0_10} OutVars{~T6_E~0=v_~T6_E~0_10} AuxVars[] AssignedVars[] 19000#L763-1 [3733] L763-1-->L768-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 19001#L768-1 [3736] L768-1-->L773-1: Formula: (< 1 v_~E_2~0_14) InVars {~E_2~0=v_~E_2~0_14} OutVars{~E_2~0=v_~E_2~0_14} AuxVars[] AssignedVars[] 19209#L773-1 [3737] L773-1-->L778-1: Formula: (< 1 v_~E_3~0_14) InVars {~E_3~0=v_~E_3~0_14} OutVars{~E_3~0=v_~E_3~0_14} AuxVars[] AssignedVars[] 19210#L778-1 [3740] L778-1-->L783-1: Formula: (< 1 v_~E_4~0_14) InVars {~E_4~0=v_~E_4~0_14} OutVars{~E_4~0=v_~E_4~0_14} AuxVars[] AssignedVars[] 19101#L783-1 [3741] L783-1-->L788-1: Formula: (< 1 v_~E_5~0_14) InVars {~E_5~0=v_~E_5~0_14} OutVars{~E_5~0=v_~E_5~0_14} AuxVars[] AssignedVars[] 19102#L788-1 [3744] L788-1-->L1014-1: Formula: (< 1 v_~E_6~0_14) InVars {~E_6~0=v_~E_6~0_14} OutVars{~E_6~0=v_~E_6~0_14} AuxVars[] AssignedVars[] 18941#L1014-1 [2020-06-22 00:13:11,666 INFO L796 eck$LassoCheckResult]: Loop: 18941#L1014-1 [4274] L1014-1-->L635: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp_ndt_7~0=v_ULTIMATE.start_eval_~tmp_ndt_7~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp_ndt_7~0] 18903#L635 [4275] L635-->L494: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_37} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 19270#L494 [2876] L494-->L531: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21 1) (= v_~m_st~0_8 0)) InVars {~m_st~0=v_~m_st~0_8} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21, ~m_st~0=v_~m_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 18972#L531 [4276] L531-->L546: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 19198#L546 [4278] L546-->L660-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 19341#L660-2 [3747] L660-2-->L660-4: Formula: (> v_~M_E~0_30 0) InVars {~M_E~0=v_~M_E~0_30} OutVars{~M_E~0=v_~M_E~0_30} AuxVars[] AssignedVars[] 19342#L660-4 [3058] L660-4-->L665-3: Formula: (and (= v_~T1_E~0_11 1) (= v_~T1_E~0_12 0)) InVars {~T1_E~0=v_~T1_E~0_12} OutVars{~T1_E~0=v_~T1_E~0_11} AuxVars[] AssignedVars[~T1_E~0] 18913#L665-3 [3756] L665-3-->L670-3: Formula: (< 0 v_~T2_E~0_13) InVars {~T2_E~0=v_~T2_E~0_13} OutVars{~T2_E~0=v_~T2_E~0_13} AuxVars[] AssignedVars[] 18914#L670-3 [3762] L670-3-->L675-3: Formula: (< 0 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 18990#L675-3 [3768] L675-3-->L680-3: Formula: (> v_~T4_E~0_13 0) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 18991#L680-3 [3776] L680-3-->L685-3: Formula: (< 0 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 19217#L685-3 [3785] L685-3-->L690-3: Formula: (> v_~T6_E~0_13 0) InVars {~T6_E~0=v_~T6_E~0_13} OutVars{~T6_E~0=v_~T6_E~0_13} AuxVars[] AssignedVars[] 19218#L690-3 [3795] L690-3-->L695-3: Formula: (< 0 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 19096#L695-3 [3805] L695-3-->L700-3: Formula: (< 0 v_~E_2~0_31) InVars {~E_2~0=v_~E_2~0_31} OutVars{~E_2~0=v_~E_2~0_31} AuxVars[] AssignedVars[] 19097#L700-3 [3818] L700-3-->L705-3: Formula: (< 0 v_~E_3~0_31) InVars {~E_3~0=v_~E_3~0_31} OutVars{~E_3~0=v_~E_3~0_31} AuxVars[] AssignedVars[] 19159#L705-3 [2688] L705-3-->L710-3: Formula: (and (= v_~E_4~0_29 1) (= 0 v_~E_4~0_30)) InVars {~E_4~0=v_~E_4~0_30} OutVars{~E_4~0=v_~E_4~0_29} AuxVars[] AssignedVars[~E_4~0] 19041#L710-3 [3844] L710-3-->L715-3: Formula: (< 0 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 19042#L715-3 [3854] L715-3-->L720-3: Formula: (< 0 v_~E_6~0_31) InVars {~E_6~0=v_~E_6~0_31} OutVars{~E_6~0=v_~E_6~0_31} AuxVars[] AssignedVars[] 18904#L720-3 [2388] L720-3-->L310-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_43, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_43, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_25|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_25|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_25|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_43, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_43, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_43, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_25|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_25|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_25|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_25|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_43, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_25|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_43, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_43} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 18905#L310-21 [3869] L310-21-->L310-23: Formula: (> v_~m_pc~0_24 1) InVars {~m_pc~0=v_~m_pc~0_24} OutVars{~m_pc~0=v_~m_pc~0_24} AuxVars[] AssignedVars[] 19184#L310-23 [2785] L310-23-->L321-7: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_47 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_47} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 19183#L321-7 [4303] L321-7-->L815-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 19144#L815-21 [3897] L815-21-->L815-23: Formula: (and (> 0 v_ULTIMATE.start_activate_threads_~tmp~1_47) (= v_~m_st~0_20 0)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_47} OutVars{~m_st~0=v_~m_st~0_20, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_47} AuxVars[] AssignedVars[~m_st~0] 19125#L815-23 [2638] L815-23-->L329-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 19126#L329-21 [3911] L329-21-->L329-23: Formula: (< v_~t1_pc~0_24 1) InVars {~t1_pc~0=v_~t1_pc~0_24} OutVars{~t1_pc~0=v_~t1_pc~0_24} AuxVars[] AssignedVars[] 19322#L329-23 [3052] L329-23-->L340-7: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 19235#L340-7 [4310] L340-7-->L823-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 19236#L823-21 [2931] L823-21-->L823-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} AuxVars[] AssignedVars[] 19293#L823-23 [2934] L823-23-->L348-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_25|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 19295#L348-21 [3953] L348-21-->L348-23: Formula: (> 1 v_~t2_pc~0_24) InVars {~t2_pc~0=v_~t2_pc~0_24} OutVars{~t2_pc~0=v_~t2_pc~0_24} AuxVars[] AssignedVars[] 19403#L348-23 [3319] L348-23-->L359-7: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 19378#L359-7 [4317] L359-7-->L831-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 19019#L831-21 [2490] L831-21-->L831-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} AuxVars[] AssignedVars[] 19020#L831-23 [3197] L831-23-->L367-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_25|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 18930#L367-21 [3995] L367-21-->L367-23: Formula: (> v_~t3_pc~0_24 1) InVars {~t3_pc~0=v_~t3_pc~0_24} OutVars{~t3_pc~0=v_~t3_pc~0_24} AuxVars[] AssignedVars[] 18897#L367-23 [2385] L367-23-->L378-7: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 18898#L378-7 [4324] L378-7-->L839-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 18954#L839-21 [4023] L839-21-->L839-23: Formula: (and (= v_~t3_st~0_21 0) (> v_ULTIMATE.start_activate_threads_~tmp___2~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} OutVars{~t3_st~0=v_~t3_st~0_21, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} AuxVars[] AssignedVars[~t3_st~0] 19178#L839-23 [2722] L839-23-->L386-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_49, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 19105#L386-21 [4037] L386-21-->L386-23: Formula: (< 1 v_~t4_pc~0_24) InVars {~t4_pc~0=v_~t4_pc~0_24} OutVars{~t4_pc~0=v_~t4_pc~0_24} AuxVars[] AssignedVars[] 19106#L386-23 [2623] L386-23-->L397-7: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 19112#L397-7 [4331] L397-7-->L847-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 19141#L847-21 [4065] L847-21-->L847-23: Formula: (and (= v_~t4_st~0_22 0) (< v_ULTIMATE.start_activate_threads_~tmp___3~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47, ~t4_st~0=v_~t4_st~0_22} AuxVars[] AssignedVars[~t4_st~0] 19323#L847-23 [2983] L847-23-->L405-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_25|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 19282#L405-21 [4080] L405-21-->L405-23: Formula: (> v_~t5_pc~0_24 1) InVars {~t5_pc~0=v_~t5_pc~0_24} OutVars{~t5_pc~0=v_~t5_pc~0_24} AuxVars[] AssignedVars[] 19269#L405-23 [2891] L405-23-->L416-7: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 19277#L416-7 [4338] L416-7-->L855-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 19288#L855-21 [3251] L855-21-->L855-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} AuxVars[] AssignedVars[] 19401#L855-23 [3257] L855-23-->L424-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_25|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 19388#L424-21 [4121] L424-21-->L424-23: Formula: (< 1 v_~t6_pc~0_24) InVars {~t6_pc~0=v_~t6_pc~0_24} OutVars{~t6_pc~0=v_~t6_pc~0_24} AuxVars[] AssignedVars[] 19371#L424-23 [3177] L424-23-->L435-7: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 19014#L435-7 [4340] L435-7-->L863-21: Formula: (and (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___5~0_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_35|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_41|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 19015#L863-21 [4135] L863-21-->L863-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___5~0_47 0) (= v_~t6_st~0_22 0)) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} OutVars{~t6_st~0=v_~t6_st~0_22, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} AuxVars[] AssignedVars[~t6_st~0] 19057#L863-23 [4137] L863-23-->L733-3: Formula: (< v_~M_E~0_35 1) InVars {~M_E~0=v_~M_E~0_35} OutVars{~M_E~0=v_~M_E~0_35} AuxVars[] AssignedVars[] 19058#L733-3 [3184] L733-3-->L738-3: Formula: (and (= v_~T1_E~0_15 1) (= v_~T1_E~0_14 2)) InVars {~T1_E~0=v_~T1_E~0_15} OutVars{~T1_E~0=v_~T1_E~0_14} AuxVars[] AssignedVars[~T1_E~0] 19317#L738-3 [4142] L738-3-->L743-3: Formula: (< 1 v_~T2_E~0_16) InVars {~T2_E~0=v_~T2_E~0_16} OutVars{~T2_E~0=v_~T2_E~0_16} AuxVars[] AssignedVars[] 19037#L743-3 [4143] L743-3-->L748-3: Formula: (< 1 v_~T3_E~0_16) InVars {~T3_E~0=v_~T3_E~0_16} OutVars{~T3_E~0=v_~T3_E~0_16} AuxVars[] AssignedVars[] 19038#L748-3 [4145] L748-3-->L753-3: Formula: (> v_~T4_E~0_16 1) InVars {~T4_E~0=v_~T4_E~0_16} OutVars{~T4_E~0=v_~T4_E~0_16} AuxVars[] AssignedVars[] 18895#L753-3 [4148] L753-3-->L758-3: Formula: (< 1 v_~T5_E~0_16) InVars {~T5_E~0=v_~T5_E~0_16} OutVars{~T5_E~0=v_~T5_E~0_16} AuxVars[] AssignedVars[] 18896#L758-3 [4149] L758-3-->L763-3: Formula: (> v_~T6_E~0_16 1) InVars {~T6_E~0=v_~T6_E~0_16} OutVars{~T6_E~0=v_~T6_E~0_16} AuxVars[] AssignedVars[] 18986#L763-3 [4151] L763-3-->L768-3: Formula: (< 1 v_~E_1~0_36) InVars {~E_1~0=v_~E_1~0_36} OutVars{~E_1~0=v_~E_1~0_36} AuxVars[] AssignedVars[] 18987#L768-3 [4154] L768-3-->L773-3: Formula: (< 1 v_~E_2~0_36) InVars {~E_2~0=v_~E_2~0_36} OutVars{~E_2~0=v_~E_2~0_36} AuxVars[] AssignedVars[] 19212#L773-3 [4156] L773-3-->L778-3: Formula: (< 1 v_~E_3~0_36) InVars {~E_3~0=v_~E_3~0_36} OutVars{~E_3~0=v_~E_3~0_36} AuxVars[] AssignedVars[] 19213#L778-3 [3308] L778-3-->L783-3: Formula: (and (= 1 v_~E_4~0_35) (= v_~E_4~0_34 2)) InVars {~E_4~0=v_~E_4~0_35} OutVars{~E_4~0=v_~E_4~0_34} AuxVars[] AssignedVars[~E_4~0] 19108#L783-3 [4160] L783-3-->L788-3: Formula: (< 1 v_~E_5~0_36) InVars {~E_5~0=v_~E_5~0_36} OutVars{~E_5~0=v_~E_5~0_36} AuxVars[] AssignedVars[] 19109#L788-3 [4162] L788-3-->L793-3: Formula: (< 1 v_~E_6~0_36) InVars {~E_6~0=v_~E_6~0_36} OutVars{~E_6~0=v_~E_6~0_36} AuxVars[] AssignedVars[] 19315#L793-3 [2966] L793-3-->L494-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_30} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 19271#L494-1 [2878] L494-1-->L531-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33 1) (= 0 v_~m_st~0_21)) InVars {~m_st~0=v_~m_st~0_21} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33, ~m_st~0=v_~m_st~0_21} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 18974#L531-1 [4341] L531-1-->L1033: Formula: (and (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp~3] 19201#L1033 [4169] L1033-->L1033-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_6) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} AuxVars[] AssignedVars[] 18944#L1033-1 [2919] L1033-1-->L494-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_3|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_6, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_exists_runnable_thread_~__retres1~7, ULTIMATE.start_stop_simulation_#res] 19272#L494-2 [2882] L494-2-->L531-2: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9 1) (= v_~m_st~0_6 0)) InVars {~m_st~0=v_~m_st~0_6} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9, ~m_st~0=v_~m_st~0_6} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 18978#L531-2 [4343] L531-2-->L988: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 19204#L988 [3240] L988-->L995: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 18940#L995 [4354] L995-->L1014-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_6|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_#t~ret17, ULTIMATE.start_stop_simulation_#res] 18941#L1014-1 [2020-06-22 00:13:11,666 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:11,666 INFO L82 PathProgramCache]: Analyzing trace with hash -621058394, now seen corresponding path program 1 times [2020-06-22 00:13:11,666 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:11,666 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:11,667 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:11,667 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:11,667 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:11,673 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:11,688 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:11,688 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:11,689 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-06-22 00:13:11,689 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-06-22 00:13:11,689 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:11,689 INFO L82 PathProgramCache]: Analyzing trace with hash -2115681615, now seen corresponding path program 1 times [2020-06-22 00:13:11,689 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:11,690 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:11,690 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:11,690 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:11,691 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:11,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:11,712 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:11,712 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:11,712 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2020-06-22 00:13:11,712 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-06-22 00:13:11,713 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-06-22 00:13:11,713 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-06-22 00:13:11,713 INFO L87 Difference]: Start difference. First operand 518 states and 964 transitions. cyclomatic complexity: 447 Second operand 3 states. [2020-06-22 00:13:12,713 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-06-22 00:13:12,713 INFO L93 Difference]: Finished difference Result 951 states and 1751 transitions. [2020-06-22 00:13:12,714 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-06-22 00:13:12,714 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 951 states and 1751 transitions. [2020-06-22 00:13:12,718 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 876 [2020-06-22 00:13:12,723 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 951 states to 951 states and 1751 transitions. [2020-06-22 00:13:12,723 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 951 [2020-06-22 00:13:12,724 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 951 [2020-06-22 00:13:12,724 INFO L73 IsDeterministic]: Start isDeterministic. Operand 951 states and 1751 transitions. [2020-06-22 00:13:12,725 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-06-22 00:13:12,725 INFO L706 BuchiCegarLoop]: Abstraction has 951 states and 1751 transitions. [2020-06-22 00:13:12,726 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 951 states and 1751 transitions. [2020-06-22 00:13:12,738 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 951 to 910. [2020-06-22 00:13:12,739 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 910 states. [2020-06-22 00:13:12,741 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 910 states to 910 states and 1680 transitions. [2020-06-22 00:13:12,741 INFO L729 BuchiCegarLoop]: Abstraction has 910 states and 1680 transitions. [2020-06-22 00:13:12,741 INFO L609 BuchiCegarLoop]: Abstraction has 910 states and 1680 transitions. [2020-06-22 00:13:12,741 INFO L442 BuchiCegarLoop]: ======== Iteration 20============ [2020-06-22 00:13:12,741 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 910 states and 1680 transitions. [2020-06-22 00:13:12,743 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 835 [2020-06-22 00:13:12,743 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-06-22 00:13:12,743 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-06-22 00:13:12,744 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:12,745 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:12,746 INFO L794 eck$LassoCheckResult]: Stem: 20824#ULTIMATE.startENTRY [4266] ULTIMATE.startENTRY-->L444: Formula: (and (= 1 v_~t6_i~0_7) (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~M_E~0_37 2) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 0 v_~t6_pc~0_26) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_6~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= v_~T6_E~0_18 2) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~t6_st~0_24) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t6_pc~0=v_~t6_pc~0_26, ~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~T6_E~0=v_~T6_E~0_18, ~M_E~0=v_~M_E~0_37, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ~T4_E~0=v_~T4_E~0_18, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_4|, ~t6_i~0=v_~t6_i~0_7, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ULTIMATE.start_main_~__retres1~8=v_ULTIMATE.start_main_~__retres1~8_6, ~T2_E~0=v_~T2_E~0_18, ~t6_st~0=v_~t6_st~0_24, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_6~0=v_~E_6~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t6_pc~0, ~t5_i~0, ~t1_pc~0, ~t5_st~0, ~T6_E~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ~T4_E~0, ULTIMATE.start_start_simulation_#t~ret17, ~t6_i~0, ~t2_st~0, ~t2_pc~0, ULTIMATE.start_main_~__retres1~8, ~T2_E~0, ~t6_st~0, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_6~0, ULTIMATE.start_main_#res, ~E_2~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 20453#L444 [2453] L444-->L451-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 20454#L451-1 [3030] L451-1-->L456-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 20543#L456-1 [2574] L456-1-->L461-1: Formula: (and (= v_~t2_st~0_2 0) (= 1 v_~t2_i~0_3)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_2} AuxVars[] AssignedVars[~t2_st~0] 20544#L461-1 [2880] L461-1-->L466-1: Formula: (and (= v_~t3_st~0_3 0) (= v_~t3_i~0_3 1)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_3, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 20458#L466-1 [2457] L466-1-->L471-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 20459#L471-1 [3209] L471-1-->L476-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 20687#L476-1 [2761] L476-1-->L481-1: Formula: (and (= 1 v_~t6_i~0_3) (= v_~t6_st~0_4 0)) InVars {~t6_i~0=v_~t6_i~0_3} OutVars{~t6_st~0=v_~t6_st~0_4, ~t6_i~0=v_~t6_i~0_3} AuxVars[] AssignedVars[~t6_st~0] 20688#L481-1 [3652] L481-1-->L660-1: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 20836#L660-1 [3654] L660-1-->L665-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 20374#L665-1 [3655] L665-1-->L670-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 20375#L670-1 [3658] L670-1-->L675-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 20465#L675-1 [3659] L675-1-->L680-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 20466#L680-1 [3661] L680-1-->L685-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 20698#L685-1 [3663] L685-1-->L690-1: Formula: (< 0 v_~T6_E~0_4) InVars {~T6_E~0=v_~T6_E~0_4} OutVars{~T6_E~0=v_~T6_E~0_4} AuxVars[] AssignedVars[] 20699#L690-1 [3665] L690-1-->L695-1: Formula: (> v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 20588#L695-1 [3668] L695-1-->L700-1: Formula: (> v_~E_2~0_6 0) InVars {~E_2~0=v_~E_2~0_6} OutVars{~E_2~0=v_~E_2~0_6} AuxVars[] AssignedVars[] 20589#L700-1 [3670] L700-1-->L705-1: Formula: (> v_~E_3~0_6 0) InVars {~E_3~0=v_~E_3~0_6} OutVars{~E_3~0=v_~E_3~0_6} AuxVars[] AssignedVars[] 20809#L705-1 [3672] L705-1-->L710-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 20527#L710-1 [3674] L710-1-->L715-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 20528#L715-1 [3675] L715-1-->L720-1: Formula: (> v_~E_6~0_4 0) InVars {~E_6~0=v_~E_6~0_4} OutVars{~E_6~0=v_~E_6~0_4} AuxVars[] AssignedVars[] 20410#L720-1 [2412] L720-1-->L310: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_7, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_4|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_4|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_7, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_4, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_4, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_2|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_2|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_4|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_4|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_7, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_2|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_4} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 20411#L310 [3678] L310-->L310-2: Formula: (< v_~m_pc~0_5 1) InVars {~m_pc~0=v_~m_pc~0_5} OutVars{~m_pc~0=v_~m_pc~0_5} AuxVars[] AssignedVars[] 20560#L310-2 [2805] L310-2-->L321: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_11 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 20555#L321 [4267] L321-->L815: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 20556#L815 [3682] L815-->L815-2: Formula: (and (= v_~m_st~0_5 0) (< 0 v_ULTIMATE.start_activate_threads_~tmp~1_11)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} OutVars{~m_st~0=v_~m_st~0_5, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} AuxVars[] AssignedVars[~m_st~0] 20805#L815-2 [2961] L815-2-->L329: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 20738#L329 [3684] L329-->L329-2: Formula: (> v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 20740#L329-2 [2861] L329-2-->L340: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 20734#L340 [4268] L340-->L823: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 20735#L823 [3688] L823-->L823-2: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___0~0_11 0) (= v_~t1_st~0_5 0)) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_11} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_11, ~t1_st~0=v_~t1_st~0_5} AuxVars[] AssignedVars[~t1_st~0] 20900#L823-2 [3235] L823-2-->L348: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_4|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 20878#L348 [3690] L348-->L348-2: Formula: (< v_~t2_pc~0_5 1) InVars {~t2_pc~0=v_~t2_pc~0_5} OutVars{~t2_pc~0=v_~t2_pc~0_5} AuxVars[] AssignedVars[] 20880#L348-2 [3153] L348-2-->L359: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 20877#L359 [4269] L359-->L831: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 20534#L831 [3694] L831-->L831-2: Formula: (and (= v_~t2_st~0_5 0) (> v_ULTIMATE.start_activate_threads_~tmp___1~0_11 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_11} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_11, ~t2_st~0=v_~t2_st~0_5} AuxVars[] AssignedVars[~t2_st~0] 20522#L831-2 [2520] L831-2-->L367: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_4|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 20461#L367 [3695] L367-->L367-2: Formula: (> 1 v_~t3_pc~0_5) InVars {~t3_pc~0=v_~t3_pc~0_5} OutVars{~t3_pc~0=v_~t3_pc~0_5} AuxVars[] AssignedVars[] 20439#L367-2 [2438] L367-2-->L378: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 20440#L378 [4270] L378-->L839: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 20460#L839 [2791] L839-->L839-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} AuxVars[] AssignedVars[] 20707#L839-2 [2794] L839-2-->L386: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_7, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 20629#L386 [2675] L386-->L387: Formula: (= v_~t4_pc~0_4 1) InVars {~t4_pc~0=v_~t4_pc~0_4} OutVars{~t4_pc~0=v_~t4_pc~0_4} AuxVars[] AssignedVars[] 20549#L387 [2588] L387-->L397: Formula: (and (= v_~E_4~0_7 1) (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_10 1)) InVars {~E_4~0=v_~E_4~0_7} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_10, ~E_4~0=v_~E_4~0_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 20551#L397 [4271] L397-->L847: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 20628#L847 [3084] L847-->L847-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} AuxVars[] AssignedVars[] 20840#L847-2 [3064] L847-2-->L405: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_4|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 20841#L405 [3708] L405-->L405-2: Formula: (> 1 v_~t5_pc~0_5) InVars {~t5_pc~0=v_~t5_pc~0_5} OutVars{~t5_pc~0=v_~t5_pc~0_5} AuxVars[] AssignedVars[] 20766#L405-2 [2940] L405-2-->L416: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 20793#L416 [4272] L416-->L855: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 20847#L855 [3711] L855-->L855-2: Formula: (and (> v_ULTIMATE.start_activate_threads_~tmp___4~0_11 0) (= v_~t5_st~0_7 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_11} OutVars{~t5_st~0=v_~t5_st~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_11} AuxVars[] AssignedVars[~t5_st~0] 20848#L855-2 [3093] L855-2-->L424: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_4|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 20505#L424 [3714] L424-->L424-2: Formula: (> v_~t6_pc~0_5 1) InVars {~t6_pc~0=v_~t6_pc~0_5} OutVars{~t6_pc~0=v_~t6_pc~0_5} AuxVars[] AssignedVars[] 20506#L424-2 [2503] L424-2-->L435: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 20502#L435 [4273] L435-->L863: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___5~0_49 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_28|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_28|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 20424#L863 [2425] L863-->L863-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___5~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} AuxVars[] AssignedVars[] 20397#L863-2 [3720] L863-2-->L733-1: Formula: (< v_~M_E~0_15 1) InVars {~M_E~0=v_~M_E~0_15} OutVars{~M_E~0=v_~M_E~0_15} AuxVars[] AssignedVars[] 20398#L733-1 [3722] L733-1-->L738-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 20807#L738-1 [3723] L738-1-->L743-1: Formula: (< 1 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 20525#L743-1 [3726] L743-1-->L748-1: Formula: (< 1 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 20526#L748-1 [3728] L748-1-->L753-1: Formula: (> v_~T4_E~0_10 1) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 20405#L753-1 [3729] L753-1-->L758-1: Formula: (< 1 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 20406#L758-1 [3732] L758-1-->L763-1: Formula: (< v_~T6_E~0_10 1) InVars {~T6_E~0=v_~T6_E~0_10} OutVars{~T6_E~0=v_~T6_E~0_10} AuxVars[] AssignedVars[] 20477#L763-1 [3733] L763-1-->L768-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 20478#L768-1 [3736] L768-1-->L773-1: Formula: (< 1 v_~E_2~0_14) InVars {~E_2~0=v_~E_2~0_14} OutVars{~E_2~0=v_~E_2~0_14} AuxVars[] AssignedVars[] 20691#L773-1 [3737] L773-1-->L778-1: Formula: (< 1 v_~E_3~0_14) InVars {~E_3~0=v_~E_3~0_14} OutVars{~E_3~0=v_~E_3~0_14} AuxVars[] AssignedVars[] 20692#L778-1 [3740] L778-1-->L783-1: Formula: (< 1 v_~E_4~0_14) InVars {~E_4~0=v_~E_4~0_14} OutVars{~E_4~0=v_~E_4~0_14} AuxVars[] AssignedVars[] 20579#L783-1 [3741] L783-1-->L788-1: Formula: (< 1 v_~E_5~0_14) InVars {~E_5~0=v_~E_5~0_14} OutVars{~E_5~0=v_~E_5~0_14} AuxVars[] AssignedVars[] 20580#L788-1 [3744] L788-1-->L1014-1: Formula: (< 1 v_~E_6~0_14) InVars {~E_6~0=v_~E_6~0_14} OutVars{~E_6~0=v_~E_6~0_14} AuxVars[] AssignedVars[] 20888#L1014-1 [2020-06-22 00:13:12,747 INFO L796 eck$LassoCheckResult]: Loop: 20888#L1014-1 [4274] L1014-1-->L635: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp_ndt_7~0=v_ULTIMATE.start_eval_~tmp_ndt_7~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp_ndt_7~0] 21124#L635 [4275] L635-->L494: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_37} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 21123#L494 [2876] L494-->L531: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21 1) (= v_~m_st~0_8 0)) InVars {~m_st~0=v_~m_st~0_8} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21, ~m_st~0=v_~m_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 21116#L531 [4276] L531-->L546: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 20885#L546 [4278] L546-->L660-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 20886#L660-2 [3747] L660-2-->L660-4: Formula: (> v_~M_E~0_30 0) InVars {~M_E~0=v_~M_E~0_30} OutVars{~M_E~0=v_~M_E~0_30} AuxVars[] AssignedVars[] 21208#L660-4 [3058] L660-4-->L665-3: Formula: (and (= v_~T1_E~0_11 1) (= v_~T1_E~0_12 0)) InVars {~T1_E~0=v_~T1_E~0_12} OutVars{~T1_E~0=v_~T1_E~0_11} AuxVars[] AssignedVars[~T1_E~0] 21205#L665-3 [3756] L665-3-->L670-3: Formula: (< 0 v_~T2_E~0_13) InVars {~T2_E~0=v_~T2_E~0_13} OutVars{~T2_E~0=v_~T2_E~0_13} AuxVars[] AssignedVars[] 21115#L670-3 [3762] L670-3-->L675-3: Formula: (< 0 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 21114#L675-3 [3768] L675-3-->L680-3: Formula: (> v_~T4_E~0_13 0) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 21113#L680-3 [3776] L680-3-->L685-3: Formula: (< 0 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 21111#L685-3 [3785] L685-3-->L690-3: Formula: (> v_~T6_E~0_13 0) InVars {~T6_E~0=v_~T6_E~0_13} OutVars{~T6_E~0=v_~T6_E~0_13} AuxVars[] AssignedVars[] 21109#L690-3 [3795] L690-3-->L695-3: Formula: (< 0 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 21083#L695-3 [3805] L695-3-->L700-3: Formula: (< 0 v_~E_2~0_31) InVars {~E_2~0=v_~E_2~0_31} OutVars{~E_2~0=v_~E_2~0_31} AuxVars[] AssignedVars[] 21043#L700-3 [3818] L700-3-->L705-3: Formula: (< 0 v_~E_3~0_31) InVars {~E_3~0=v_~E_3~0_31} OutVars{~E_3~0=v_~E_3~0_31} AuxVars[] AssignedVars[] 21041#L705-3 [2688] L705-3-->L710-3: Formula: (and (= v_~E_4~0_29 1) (= 0 v_~E_4~0_30)) InVars {~E_4~0=v_~E_4~0_30} OutVars{~E_4~0=v_~E_4~0_29} AuxVars[] AssignedVars[~E_4~0] 21037#L710-3 [3844] L710-3-->L715-3: Formula: (< 0 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 21034#L715-3 [3854] L715-3-->L720-3: Formula: (< 0 v_~E_6~0_31) InVars {~E_6~0=v_~E_6~0_31} OutVars{~E_6~0=v_~E_6~0_31} AuxVars[] AssignedVars[] 21032#L720-3 [2388] L720-3-->L310-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_43, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_43, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_25|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_25|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_25|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_43, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_43, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_43, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_25|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_25|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_25|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_25|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_43, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_25|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_43, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_43} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 20700#L310-21 [3870] L310-21-->L310-23: Formula: (< v_~m_pc~0_24 1) InVars {~m_pc~0=v_~m_pc~0_24} OutVars{~m_pc~0=v_~m_pc~0_24} AuxVars[] AssignedVars[] 20701#L310-23 [2785] L310-23-->L321-7: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_47 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_47} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 21279#L321-7 [4303] L321-7-->L815-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 21278#L815-21 [3897] L815-21-->L815-23: Formula: (and (> 0 v_ULTIMATE.start_activate_threads_~tmp~1_47) (= v_~m_st~0_20 0)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_47} OutVars{~m_st~0=v_~m_st~0_20, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_47} AuxVars[] AssignedVars[~m_st~0] 21277#L815-23 [2638] L815-23-->L329-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 21276#L329-21 [3911] L329-21-->L329-23: Formula: (< v_~t1_pc~0_24 1) InVars {~t1_pc~0=v_~t1_pc~0_24} OutVars{~t1_pc~0=v_~t1_pc~0_24} AuxVars[] AssignedVars[] 21274#L329-23 [3052] L329-23-->L340-7: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 21273#L340-7 [4310] L340-7-->L823-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 21272#L823-21 [2931] L823-21-->L823-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} AuxVars[] AssignedVars[] 21271#L823-23 [2934] L823-23-->L348-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_25|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 21269#L348-21 [3953] L348-21-->L348-23: Formula: (> 1 v_~t2_pc~0_24) InVars {~t2_pc~0=v_~t2_pc~0_24} OutVars{~t2_pc~0=v_~t2_pc~0_24} AuxVars[] AssignedVars[] 21268#L348-23 [3319] L348-23-->L359-7: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 21267#L359-7 [4317] L359-7-->L831-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 21266#L831-21 [2490] L831-21-->L831-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} AuxVars[] AssignedVars[] 21265#L831-23 [3197] L831-23-->L367-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_25|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 21264#L367-21 [3995] L367-21-->L367-23: Formula: (> v_~t3_pc~0_24 1) InVars {~t3_pc~0=v_~t3_pc~0_24} OutVars{~t3_pc~0=v_~t3_pc~0_24} AuxVars[] AssignedVars[] 21262#L367-23 [2385] L367-23-->L378-7: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 21261#L378-7 [4324] L378-7-->L839-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 21260#L839-21 [4023] L839-21-->L839-23: Formula: (and (= v_~t3_st~0_21 0) (> v_ULTIMATE.start_activate_threads_~tmp___2~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} OutVars{~t3_st~0=v_~t3_st~0_21, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} AuxVars[] AssignedVars[~t3_st~0] 21259#L839-23 [2722] L839-23-->L386-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_49, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 21258#L386-21 [2617] L386-21-->L387-7: Formula: (= 1 v_~t4_pc~0_23) InVars {~t4_pc~0=v_~t4_pc~0_23} OutVars{~t4_pc~0=v_~t4_pc~0_23} AuxVars[] AssignedVars[] 21256#L387-7 [2818] L387-7-->L397-7: Formula: (and (= 1 v_~E_4~0_32) (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_52 1)) InVars {~E_4~0=v_~E_4~0_32} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_52, ~E_4~0=v_~E_4~0_32} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 21255#L397-7 [4331] L397-7-->L847-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 20830#L847-21 [4065] L847-21-->L847-23: Formula: (and (= v_~t4_st~0_22 0) (< v_ULTIMATE.start_activate_threads_~tmp___3~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47, ~t4_st~0=v_~t4_st~0_22} AuxVars[] AssignedVars[~t4_st~0] 20817#L847-23 [2983] L847-23-->L405-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_25|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 20818#L405-21 [4080] L405-21-->L405-23: Formula: (> v_~t5_pc~0_24 1) InVars {~t5_pc~0=v_~t5_pc~0_24} OutVars{~t5_pc~0=v_~t5_pc~0_24} AuxVars[] AssignedVars[] 21252#L405-23 [2891] L405-23-->L416-7: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 21251#L416-7 [4338] L416-7-->L855-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 21250#L855-21 [3251] L855-21-->L855-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} AuxVars[] AssignedVars[] 21249#L855-23 [3257] L855-23-->L424-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_25|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 21247#L424-21 [4121] L424-21-->L424-23: Formula: (< 1 v_~t6_pc~0_24) InVars {~t6_pc~0=v_~t6_pc~0_24} OutVars{~t6_pc~0=v_~t6_pc~0_24} AuxVars[] AssignedVars[] 21246#L424-23 [3177] L424-23-->L435-7: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 21245#L435-7 [4340] L435-7-->L863-21: Formula: (and (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___5~0_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_35|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_41|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 21244#L863-21 [4135] L863-21-->L863-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___5~0_47 0) (= v_~t6_st~0_22 0)) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} OutVars{~t6_st~0=v_~t6_st~0_22, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} AuxVars[] AssignedVars[~t6_st~0] 21243#L863-23 [4137] L863-23-->L733-3: Formula: (< v_~M_E~0_35 1) InVars {~M_E~0=v_~M_E~0_35} OutVars{~M_E~0=v_~M_E~0_35} AuxVars[] AssignedVars[] 21242#L733-3 [3184] L733-3-->L738-3: Formula: (and (= v_~T1_E~0_15 1) (= v_~T1_E~0_14 2)) InVars {~T1_E~0=v_~T1_E~0_15} OutVars{~T1_E~0=v_~T1_E~0_14} AuxVars[] AssignedVars[~T1_E~0] 21241#L738-3 [4142] L738-3-->L743-3: Formula: (< 1 v_~T2_E~0_16) InVars {~T2_E~0=v_~T2_E~0_16} OutVars{~T2_E~0=v_~T2_E~0_16} AuxVars[] AssignedVars[] 20515#L743-3 [4143] L743-3-->L748-3: Formula: (< 1 v_~T3_E~0_16) InVars {~T3_E~0=v_~T3_E~0_16} OutVars{~T3_E~0=v_~T3_E~0_16} AuxVars[] AssignedVars[] 20516#L748-3 [4145] L748-3-->L753-3: Formula: (> v_~T4_E~0_16 1) InVars {~T4_E~0=v_~T4_E~0_16} OutVars{~T4_E~0=v_~T4_E~0_16} AuxVars[] AssignedVars[] 20372#L753-3 [4148] L753-3-->L758-3: Formula: (< 1 v_~T5_E~0_16) InVars {~T5_E~0=v_~T5_E~0_16} OutVars{~T5_E~0=v_~T5_E~0_16} AuxVars[] AssignedVars[] 20373#L758-3 [4149] L758-3-->L763-3: Formula: (> v_~T6_E~0_16 1) InVars {~T6_E~0=v_~T6_E~0_16} OutVars{~T6_E~0=v_~T6_E~0_16} AuxVars[] AssignedVars[] 20463#L763-3 [4151] L763-3-->L768-3: Formula: (< 1 v_~E_1~0_36) InVars {~E_1~0=v_~E_1~0_36} OutVars{~E_1~0=v_~E_1~0_36} AuxVars[] AssignedVars[] 20464#L768-3 [4154] L768-3-->L773-3: Formula: (< 1 v_~E_2~0_36) InVars {~E_2~0=v_~E_2~0_36} OutVars{~E_2~0=v_~E_2~0_36} AuxVars[] AssignedVars[] 20696#L773-3 [4156] L773-3-->L778-3: Formula: (< 1 v_~E_3~0_36) InVars {~E_3~0=v_~E_3~0_36} OutVars{~E_3~0=v_~E_3~0_36} AuxVars[] AssignedVars[] 20697#L778-3 [3308] L778-3-->L783-3: Formula: (and (= 1 v_~E_4~0_35) (= v_~E_4~0_34 2)) InVars {~E_4~0=v_~E_4~0_35} OutVars{~E_4~0=v_~E_4~0_34} AuxVars[] AssignedVars[~E_4~0] 20586#L783-3 [4160] L783-3-->L788-3: Formula: (< 1 v_~E_5~0_36) InVars {~E_5~0=v_~E_5~0_36} OutVars{~E_5~0=v_~E_5~0_36} AuxVars[] AssignedVars[] 20587#L788-3 [4162] L788-3-->L793-3: Formula: (< 1 v_~E_6~0_36) InVars {~E_6~0=v_~E_6~0_36} OutVars{~E_6~0=v_~E_6~0_36} AuxVars[] AssignedVars[] 20808#L793-3 [2966] L793-3-->L494-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_30} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 20763#L494-1 [2878] L494-1-->L531-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33 1) (= 0 v_~m_st~0_21)) InVars {~m_st~0=v_~m_st~0_21} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33, ~m_st~0=v_~m_st~0_21} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 20451#L531-1 [4341] L531-1-->L1033: Formula: (and (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp~3] 20683#L1033 [4169] L1033-->L1033-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_6) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} AuxVars[] AssignedVars[] 20775#L1033-1 [2919] L1033-1-->L494-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_3|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_6, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_exists_runnable_thread_~__retres1~7, ULTIMATE.start_stop_simulation_#res] 21135#L494-2 [2882] L494-2-->L531-2: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9 1) (= v_~m_st~0_6 0)) InVars {~m_st~0=v_~m_st~0_6} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9, ~m_st~0=v_~m_st~0_6} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 21133#L531-2 [4343] L531-2-->L988: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 21131#L988 [3240] L988-->L995: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 21129#L995 [4354] L995-->L1014-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_6|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_#t~ret17, ULTIMATE.start_stop_simulation_#res] 20888#L1014-1 [2020-06-22 00:13:12,747 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:12,747 INFO L82 PathProgramCache]: Analyzing trace with hash -824290954, now seen corresponding path program 1 times [2020-06-22 00:13:12,747 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:12,747 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:12,748 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:12,748 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:12,748 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:12,754 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:12,772 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:12,773 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:12,773 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2020-06-22 00:13:12,773 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-06-22 00:13:12,773 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:12,773 INFO L82 PathProgramCache]: Analyzing trace with hash 193525407, now seen corresponding path program 1 times [2020-06-22 00:13:12,774 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:12,774 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:12,774 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:12,774 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:12,775 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:12,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:12,796 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:12,796 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:12,797 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2020-06-22 00:13:12,797 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-06-22 00:13:12,797 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2020-06-22 00:13:12,797 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2020-06-22 00:13:12,797 INFO L87 Difference]: Start difference. First operand 910 states and 1680 transitions. cyclomatic complexity: 771 Second operand 4 states. [2020-06-22 00:13:14,391 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-06-22 00:13:14,391 INFO L93 Difference]: Finished difference Result 1734 states and 3194 transitions. [2020-06-22 00:13:14,392 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2020-06-22 00:13:14,392 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1734 states and 3194 transitions. [2020-06-22 00:13:14,398 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1659 [2020-06-22 00:13:14,408 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1734 states to 1734 states and 3194 transitions. [2020-06-22 00:13:14,408 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1734 [2020-06-22 00:13:14,409 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1734 [2020-06-22 00:13:14,409 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1734 states and 3194 transitions. [2020-06-22 00:13:14,410 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-06-22 00:13:14,410 INFO L706 BuchiCegarLoop]: Abstraction has 1734 states and 3194 transitions. [2020-06-22 00:13:14,411 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1734 states and 3194 transitions. [2020-06-22 00:13:14,425 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1734 to 926. [2020-06-22 00:13:14,425 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 926 states. [2020-06-22 00:13:14,427 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 926 states to 926 states and 1696 transitions. [2020-06-22 00:13:14,427 INFO L729 BuchiCegarLoop]: Abstraction has 926 states and 1696 transitions. [2020-06-22 00:13:14,427 INFO L609 BuchiCegarLoop]: Abstraction has 926 states and 1696 transitions. [2020-06-22 00:13:14,428 INFO L442 BuchiCegarLoop]: ======== Iteration 21============ [2020-06-22 00:13:14,428 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 926 states and 1696 transitions. [2020-06-22 00:13:14,430 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 851 [2020-06-22 00:13:14,430 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-06-22 00:13:14,430 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-06-22 00:13:14,431 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:14,431 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:14,432 INFO L794 eck$LassoCheckResult]: Stem: 23484#ULTIMATE.startENTRY [4266] ULTIMATE.startENTRY-->L444: Formula: (and (= 1 v_~t6_i~0_7) (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~M_E~0_37 2) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 0 v_~t6_pc~0_26) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_6~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= v_~T6_E~0_18 2) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~t6_st~0_24) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t6_pc~0=v_~t6_pc~0_26, ~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~T6_E~0=v_~T6_E~0_18, ~M_E~0=v_~M_E~0_37, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ~T4_E~0=v_~T4_E~0_18, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_4|, ~t6_i~0=v_~t6_i~0_7, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ULTIMATE.start_main_~__retres1~8=v_ULTIMATE.start_main_~__retres1~8_6, ~T2_E~0=v_~T2_E~0_18, ~t6_st~0=v_~t6_st~0_24, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_6~0=v_~E_6~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t6_pc~0, ~t5_i~0, ~t1_pc~0, ~t5_st~0, ~T6_E~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ~T4_E~0, ULTIMATE.start_start_simulation_#t~ret17, ~t6_i~0, ~t2_st~0, ~t2_pc~0, ULTIMATE.start_main_~__retres1~8, ~T2_E~0, ~t6_st~0, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_6~0, ULTIMATE.start_main_#res, ~E_2~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 23108#L444 [2453] L444-->L451-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 23109#L451-1 [3030] L451-1-->L456-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 23197#L456-1 [2574] L456-1-->L461-1: Formula: (and (= v_~t2_st~0_2 0) (= 1 v_~t2_i~0_3)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_2} AuxVars[] AssignedVars[~t2_st~0] 23198#L461-1 [2880] L461-1-->L466-1: Formula: (and (= v_~t3_st~0_3 0) (= v_~t3_i~0_3 1)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_3, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 23113#L466-1 [2457] L466-1-->L471-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 23114#L471-1 [3209] L471-1-->L476-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 23340#L476-1 [2761] L476-1-->L481-1: Formula: (and (= 1 v_~t6_i~0_3) (= v_~t6_st~0_4 0)) InVars {~t6_i~0=v_~t6_i~0_3} OutVars{~t6_st~0=v_~t6_st~0_4, ~t6_i~0=v_~t6_i~0_3} AuxVars[] AssignedVars[~t6_st~0] 23341#L481-1 [3652] L481-1-->L660-1: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 23495#L660-1 [3654] L660-1-->L665-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 23029#L665-1 [3655] L665-1-->L670-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 23030#L670-1 [3658] L670-1-->L675-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 23120#L675-1 [3659] L675-1-->L680-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 23121#L680-1 [3661] L680-1-->L685-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 23351#L685-1 [3663] L685-1-->L690-1: Formula: (< 0 v_~T6_E~0_4) InVars {~T6_E~0=v_~T6_E~0_4} OutVars{~T6_E~0=v_~T6_E~0_4} AuxVars[] AssignedVars[] 23352#L690-1 [3665] L690-1-->L695-1: Formula: (> v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 23241#L695-1 [3668] L695-1-->L700-1: Formula: (> v_~E_2~0_6 0) InVars {~E_2~0=v_~E_2~0_6} OutVars{~E_2~0=v_~E_2~0_6} AuxVars[] AssignedVars[] 23242#L700-1 [3670] L700-1-->L705-1: Formula: (> v_~E_3~0_6 0) InVars {~E_3~0=v_~E_3~0_6} OutVars{~E_3~0=v_~E_3~0_6} AuxVars[] AssignedVars[] 23470#L705-1 [3672] L705-1-->L710-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 23181#L710-1 [3674] L710-1-->L715-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 23182#L715-1 [3675] L715-1-->L720-1: Formula: (> v_~E_6~0_4 0) InVars {~E_6~0=v_~E_6~0_4} OutVars{~E_6~0=v_~E_6~0_4} AuxVars[] AssignedVars[] 23065#L720-1 [2412] L720-1-->L310: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_7, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_4|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_4|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_7, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_4, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_4, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_2|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_2|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_4|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_4|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_7, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_2|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_4} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 23066#L310 [3678] L310-->L310-2: Formula: (< v_~m_pc~0_5 1) InVars {~m_pc~0=v_~m_pc~0_5} OutVars{~m_pc~0=v_~m_pc~0_5} AuxVars[] AssignedVars[] 23213#L310-2 [2805] L310-2-->L321: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_11 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 23208#L321 [4267] L321-->L815: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 23209#L815 [3681] L815-->L815-2: Formula: (and (= v_~m_st~0_5 0) (> 0 v_ULTIMATE.start_activate_threads_~tmp~1_11)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} OutVars{~m_st~0=v_~m_st~0_5, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_11} AuxVars[] AssignedVars[~m_st~0] 23465#L815-2 [2961] L815-2-->L329: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 23398#L329 [3684] L329-->L329-2: Formula: (> v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 23400#L329-2 [2861] L329-2-->L340: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 23394#L340 [4268] L340-->L823: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 23395#L823 [3688] L823-->L823-2: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___0~0_11 0) (= v_~t1_st~0_5 0)) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_11} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_11, ~t1_st~0=v_~t1_st~0_5} AuxVars[] AssignedVars[~t1_st~0] 23558#L823-2 [3235] L823-2-->L348: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_4|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 23538#L348 [3690] L348-->L348-2: Formula: (< v_~t2_pc~0_5 1) InVars {~t2_pc~0=v_~t2_pc~0_5} OutVars{~t2_pc~0=v_~t2_pc~0_5} AuxVars[] AssignedVars[] 23540#L348-2 [3153] L348-2-->L359: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 23537#L359 [4269] L359-->L831: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 23188#L831 [3694] L831-->L831-2: Formula: (and (= v_~t2_st~0_5 0) (> v_ULTIMATE.start_activate_threads_~tmp___1~0_11 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_11} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_11, ~t2_st~0=v_~t2_st~0_5} AuxVars[] AssignedVars[~t2_st~0] 23176#L831-2 [2520] L831-2-->L367: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_4|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 23116#L367 [3695] L367-->L367-2: Formula: (> 1 v_~t3_pc~0_5) InVars {~t3_pc~0=v_~t3_pc~0_5} OutVars{~t3_pc~0=v_~t3_pc~0_5} AuxVars[] AssignedVars[] 23094#L367-2 [2438] L367-2-->L378: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 23095#L378 [4270] L378-->L839: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 23115#L839 [2791] L839-->L839-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} AuxVars[] AssignedVars[] 23361#L839-2 [2794] L839-2-->L386: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_7, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 23282#L386 [2675] L386-->L387: Formula: (= v_~t4_pc~0_4 1) InVars {~t4_pc~0=v_~t4_pc~0_4} OutVars{~t4_pc~0=v_~t4_pc~0_4} AuxVars[] AssignedVars[] 23202#L387 [2588] L387-->L397: Formula: (and (= v_~E_4~0_7 1) (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_10 1)) InVars {~E_4~0=v_~E_4~0_7} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_10, ~E_4~0=v_~E_4~0_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 23204#L397 [4271] L397-->L847: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 23281#L847 [3084] L847-->L847-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} AuxVars[] AssignedVars[] 23500#L847-2 [3064] L847-2-->L405: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_4|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 23501#L405 [3708] L405-->L405-2: Formula: (> 1 v_~t5_pc~0_5) InVars {~t5_pc~0=v_~t5_pc~0_5} OutVars{~t5_pc~0=v_~t5_pc~0_5} AuxVars[] AssignedVars[] 23426#L405-2 [2940] L405-2-->L416: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 23453#L416 [4272] L416-->L855: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 23507#L855 [3711] L855-->L855-2: Formula: (and (> v_ULTIMATE.start_activate_threads_~tmp___4~0_11 0) (= v_~t5_st~0_7 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_11} OutVars{~t5_st~0=v_~t5_st~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_11} AuxVars[] AssignedVars[~t5_st~0] 23508#L855-2 [3093] L855-2-->L424: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_4|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 23160#L424 [3714] L424-->L424-2: Formula: (> v_~t6_pc~0_5 1) InVars {~t6_pc~0=v_~t6_pc~0_5} OutVars{~t6_pc~0=v_~t6_pc~0_5} AuxVars[] AssignedVars[] 23161#L424-2 [2503] L424-2-->L435: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 23157#L435 [4273] L435-->L863: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___5~0_49 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_28|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_28|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 23079#L863 [2425] L863-->L863-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___5~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} AuxVars[] AssignedVars[] 23052#L863-2 [3720] L863-2-->L733-1: Formula: (< v_~M_E~0_15 1) InVars {~M_E~0=v_~M_E~0_15} OutVars{~M_E~0=v_~M_E~0_15} AuxVars[] AssignedVars[] 23053#L733-1 [3722] L733-1-->L738-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 23468#L738-1 [3723] L738-1-->L743-1: Formula: (< 1 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 23179#L743-1 [3726] L743-1-->L748-1: Formula: (< 1 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 23180#L748-1 [3728] L748-1-->L753-1: Formula: (> v_~T4_E~0_10 1) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 23060#L753-1 [3729] L753-1-->L758-1: Formula: (< 1 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 23061#L758-1 [3732] L758-1-->L763-1: Formula: (< v_~T6_E~0_10 1) InVars {~T6_E~0=v_~T6_E~0_10} OutVars{~T6_E~0=v_~T6_E~0_10} AuxVars[] AssignedVars[] 23132#L763-1 [3733] L763-1-->L768-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 23133#L768-1 [3736] L768-1-->L773-1: Formula: (< 1 v_~E_2~0_14) InVars {~E_2~0=v_~E_2~0_14} OutVars{~E_2~0=v_~E_2~0_14} AuxVars[] AssignedVars[] 23344#L773-1 [3737] L773-1-->L778-1: Formula: (< 1 v_~E_3~0_14) InVars {~E_3~0=v_~E_3~0_14} OutVars{~E_3~0=v_~E_3~0_14} AuxVars[] AssignedVars[] 23345#L778-1 [3740] L778-1-->L783-1: Formula: (< 1 v_~E_4~0_14) InVars {~E_4~0=v_~E_4~0_14} OutVars{~E_4~0=v_~E_4~0_14} AuxVars[] AssignedVars[] 23232#L783-1 [3741] L783-1-->L788-1: Formula: (< 1 v_~E_5~0_14) InVars {~E_5~0=v_~E_5~0_14} OutVars{~E_5~0=v_~E_5~0_14} AuxVars[] AssignedVars[] 23233#L788-1 [3744] L788-1-->L1014-1: Formula: (< 1 v_~E_6~0_14) InVars {~E_6~0=v_~E_6~0_14} OutVars{~E_6~0=v_~E_6~0_14} AuxVars[] AssignedVars[] 23544#L1014-1 [2020-06-22 00:13:14,433 INFO L796 eck$LassoCheckResult]: Loop: 23544#L1014-1 [4274] L1014-1-->L635: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp_ndt_7~0=v_ULTIMATE.start_eval_~tmp_ndt_7~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp_ndt_7~0] 23732#L635 [4275] L635-->L494: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_37} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 23720#L494 [2876] L494-->L531: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21 1) (= v_~m_st~0_8 0)) InVars {~m_st~0=v_~m_st~0_8} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21, ~m_st~0=v_~m_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 23711#L531 [4276] L531-->L546: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 23707#L546 [4278] L546-->L660-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 23708#L660-2 [3747] L660-2-->L660-4: Formula: (> v_~M_E~0_30 0) InVars {~M_E~0=v_~M_E~0_30} OutVars{~M_E~0=v_~M_E~0_30} AuxVars[] AssignedVars[] 23949#L660-4 [3058] L660-4-->L665-3: Formula: (and (= v_~T1_E~0_11 1) (= v_~T1_E~0_12 0)) InVars {~T1_E~0=v_~T1_E~0_12} OutVars{~T1_E~0=v_~T1_E~0_11} AuxVars[] AssignedVars[~T1_E~0] 23948#L665-3 [3756] L665-3-->L670-3: Formula: (< 0 v_~T2_E~0_13) InVars {~T2_E~0=v_~T2_E~0_13} OutVars{~T2_E~0=v_~T2_E~0_13} AuxVars[] AssignedVars[] 23947#L670-3 [3762] L670-3-->L675-3: Formula: (< 0 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 23946#L675-3 [3768] L675-3-->L680-3: Formula: (> v_~T4_E~0_13 0) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 23945#L680-3 [3776] L680-3-->L685-3: Formula: (< 0 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 23944#L685-3 [3785] L685-3-->L690-3: Formula: (> v_~T6_E~0_13 0) InVars {~T6_E~0=v_~T6_E~0_13} OutVars{~T6_E~0=v_~T6_E~0_13} AuxVars[] AssignedVars[] 23943#L690-3 [3795] L690-3-->L695-3: Formula: (< 0 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 23942#L695-3 [3805] L695-3-->L700-3: Formula: (< 0 v_~E_2~0_31) InVars {~E_2~0=v_~E_2~0_31} OutVars{~E_2~0=v_~E_2~0_31} AuxVars[] AssignedVars[] 23941#L700-3 [3818] L700-3-->L705-3: Formula: (< 0 v_~E_3~0_31) InVars {~E_3~0=v_~E_3~0_31} OutVars{~E_3~0=v_~E_3~0_31} AuxVars[] AssignedVars[] 23940#L705-3 [2688] L705-3-->L710-3: Formula: (and (= v_~E_4~0_29 1) (= 0 v_~E_4~0_30)) InVars {~E_4~0=v_~E_4~0_30} OutVars{~E_4~0=v_~E_4~0_29} AuxVars[] AssignedVars[~E_4~0] 23939#L710-3 [3844] L710-3-->L715-3: Formula: (< 0 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 23938#L715-3 [3854] L715-3-->L720-3: Formula: (< 0 v_~E_6~0_31) InVars {~E_6~0=v_~E_6~0_31} OutVars{~E_6~0=v_~E_6~0_31} AuxVars[] AssignedVars[] 23036#L720-3 [2388] L720-3-->L310-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_43, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_43, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_25|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_25|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_25|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_43, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_43, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_43, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_25|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_25|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_25|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_25|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_43, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_25|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_43, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_43} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 23037#L310-21 [3870] L310-21-->L310-23: Formula: (< v_~m_pc~0_24 1) InVars {~m_pc~0=v_~m_pc~0_24} OutVars{~m_pc~0=v_~m_pc~0_24} AuxVars[] AssignedVars[] 23353#L310-23 [2785] L310-23-->L321-7: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_47 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_47} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 23684#L321-7 [4303] L321-7-->L815-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 23682#L815-21 [3897] L815-21-->L815-23: Formula: (and (> 0 v_ULTIMATE.start_activate_threads_~tmp~1_47) (= v_~m_st~0_20 0)) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_47} OutVars{~m_st~0=v_~m_st~0_20, ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_47} AuxVars[] AssignedVars[~m_st~0] 23680#L815-23 [2638] L815-23-->L329-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 23678#L329-21 [3911] L329-21-->L329-23: Formula: (< v_~t1_pc~0_24 1) InVars {~t1_pc~0=v_~t1_pc~0_24} OutVars{~t1_pc~0=v_~t1_pc~0_24} AuxVars[] AssignedVars[] 23675#L329-23 [3052] L329-23-->L340-7: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 23672#L340-7 [4310] L340-7-->L823-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 23670#L823-21 [2931] L823-21-->L823-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} AuxVars[] AssignedVars[] 23668#L823-23 [2934] L823-23-->L348-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_25|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 23662#L348-21 [3953] L348-21-->L348-23: Formula: (> 1 v_~t2_pc~0_24) InVars {~t2_pc~0=v_~t2_pc~0_24} OutVars{~t2_pc~0=v_~t2_pc~0_24} AuxVars[] AssignedVars[] 23660#L348-23 [3319] L348-23-->L359-7: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 23658#L359-7 [4317] L359-7-->L831-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 23656#L831-21 [2490] L831-21-->L831-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} AuxVars[] AssignedVars[] 23655#L831-23 [3197] L831-23-->L367-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_25|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 23654#L367-21 [3995] L367-21-->L367-23: Formula: (> v_~t3_pc~0_24 1) InVars {~t3_pc~0=v_~t3_pc~0_24} OutVars{~t3_pc~0=v_~t3_pc~0_24} AuxVars[] AssignedVars[] 23650#L367-23 [2385] L367-23-->L378-7: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 23648#L378-7 [4324] L378-7-->L839-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 23646#L839-21 [4023] L839-21-->L839-23: Formula: (and (= v_~t3_st~0_21 0) (> v_ULTIMATE.start_activate_threads_~tmp___2~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} OutVars{~t3_st~0=v_~t3_st~0_21, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} AuxVars[] AssignedVars[~t3_st~0] 23644#L839-23 [2722] L839-23-->L386-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_49, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 23643#L386-21 [2617] L386-21-->L387-7: Formula: (= 1 v_~t4_pc~0_23) InVars {~t4_pc~0=v_~t4_pc~0_23} OutVars{~t4_pc~0=v_~t4_pc~0_23} AuxVars[] AssignedVars[] 23641#L387-7 [2818] L387-7-->L397-7: Formula: (and (= 1 v_~E_4~0_32) (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_52 1)) InVars {~E_4~0=v_~E_4~0_32} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_52, ~E_4~0=v_~E_4~0_32} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 23640#L397-7 [4331] L397-7-->L847-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 23637#L847-21 [4065] L847-21-->L847-23: Formula: (and (= v_~t4_st~0_22 0) (< v_ULTIMATE.start_activate_threads_~tmp___3~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47, ~t4_st~0=v_~t4_st~0_22} AuxVars[] AssignedVars[~t4_st~0] 23636#L847-23 [2983] L847-23-->L405-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_25|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 23634#L405-21 [4080] L405-21-->L405-23: Formula: (> v_~t5_pc~0_24 1) InVars {~t5_pc~0=v_~t5_pc~0_24} OutVars{~t5_pc~0=v_~t5_pc~0_24} AuxVars[] AssignedVars[] 23633#L405-23 [2891] L405-23-->L416-7: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 23632#L416-7 [4338] L416-7-->L855-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 23631#L855-21 [3251] L855-21-->L855-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} AuxVars[] AssignedVars[] 23630#L855-23 [3257] L855-23-->L424-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_25|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 23628#L424-21 [4121] L424-21-->L424-23: Formula: (< 1 v_~t6_pc~0_24) InVars {~t6_pc~0=v_~t6_pc~0_24} OutVars{~t6_pc~0=v_~t6_pc~0_24} AuxVars[] AssignedVars[] 23627#L424-23 [3177] L424-23-->L435-7: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 23626#L435-7 [4340] L435-7-->L863-21: Formula: (and (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___5~0_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_35|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_41|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 23625#L863-21 [4135] L863-21-->L863-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___5~0_47 0) (= v_~t6_st~0_22 0)) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} OutVars{~t6_st~0=v_~t6_st~0_22, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} AuxVars[] AssignedVars[~t6_st~0] 23624#L863-23 [4137] L863-23-->L733-3: Formula: (< v_~M_E~0_35 1) InVars {~M_E~0=v_~M_E~0_35} OutVars{~M_E~0=v_~M_E~0_35} AuxVars[] AssignedVars[] 23623#L733-3 [3184] L733-3-->L738-3: Formula: (and (= v_~T1_E~0_15 1) (= v_~T1_E~0_14 2)) InVars {~T1_E~0=v_~T1_E~0_15} OutVars{~T1_E~0=v_~T1_E~0_14} AuxVars[] AssignedVars[~T1_E~0] 23622#L738-3 [4142] L738-3-->L743-3: Formula: (< 1 v_~T2_E~0_16) InVars {~T2_E~0=v_~T2_E~0_16} OutVars{~T2_E~0=v_~T2_E~0_16} AuxVars[] AssignedVars[] 23619#L743-3 [4143] L743-3-->L748-3: Formula: (< 1 v_~T3_E~0_16) InVars {~T3_E~0=v_~T3_E~0_16} OutVars{~T3_E~0=v_~T3_E~0_16} AuxVars[] AssignedVars[] 23617#L748-3 [4145] L748-3-->L753-3: Formula: (> v_~T4_E~0_16 1) InVars {~T4_E~0=v_~T4_E~0_16} OutVars{~T4_E~0=v_~T4_E~0_16} AuxVars[] AssignedVars[] 23615#L753-3 [4148] L753-3-->L758-3: Formula: (< 1 v_~T5_E~0_16) InVars {~T5_E~0=v_~T5_E~0_16} OutVars{~T5_E~0=v_~T5_E~0_16} AuxVars[] AssignedVars[] 23613#L758-3 [4149] L758-3-->L763-3: Formula: (> v_~T6_E~0_16 1) InVars {~T6_E~0=v_~T6_E~0_16} OutVars{~T6_E~0=v_~T6_E~0_16} AuxVars[] AssignedVars[] 23611#L763-3 [4151] L763-3-->L768-3: Formula: (< 1 v_~E_1~0_36) InVars {~E_1~0=v_~E_1~0_36} OutVars{~E_1~0=v_~E_1~0_36} AuxVars[] AssignedVars[] 23608#L768-3 [4154] L768-3-->L773-3: Formula: (< 1 v_~E_2~0_36) InVars {~E_2~0=v_~E_2~0_36} OutVars{~E_2~0=v_~E_2~0_36} AuxVars[] AssignedVars[] 23606#L773-3 [4156] L773-3-->L778-3: Formula: (< 1 v_~E_3~0_36) InVars {~E_3~0=v_~E_3~0_36} OutVars{~E_3~0=v_~E_3~0_36} AuxVars[] AssignedVars[] 23604#L778-3 [3308] L778-3-->L783-3: Formula: (and (= 1 v_~E_4~0_35) (= v_~E_4~0_34 2)) InVars {~E_4~0=v_~E_4~0_35} OutVars{~E_4~0=v_~E_4~0_34} AuxVars[] AssignedVars[~E_4~0] 23602#L783-3 [4160] L783-3-->L788-3: Formula: (< 1 v_~E_5~0_36) InVars {~E_5~0=v_~E_5~0_36} OutVars{~E_5~0=v_~E_5~0_36} AuxVars[] AssignedVars[] 23601#L788-3 [4162] L788-3-->L793-3: Formula: (< 1 v_~E_6~0_36) InVars {~E_6~0=v_~E_6~0_36} OutVars{~E_6~0=v_~E_6~0_36} AuxVars[] AssignedVars[] 23598#L793-3 [2966] L793-3-->L494-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_30} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 23593#L494-1 [2878] L494-1-->L531-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33 1) (= 0 v_~m_st~0_21)) InVars {~m_st~0=v_~m_st~0_21} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33, ~m_st~0=v_~m_st~0_21} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 23582#L531-1 [4341] L531-1-->L1033: Formula: (and (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp~3] 23579#L1033 [4169] L1033-->L1033-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_6) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} AuxVars[] AssignedVars[] 23580#L1033-1 [2919] L1033-1-->L494-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_3|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_6, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_exists_runnable_thread_~__retres1~7, ULTIMATE.start_stop_simulation_#res] 23748#L494-2 [2882] L494-2-->L531-2: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9 1) (= v_~m_st~0_6 0)) InVars {~m_st~0=v_~m_st~0_6} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9, ~m_st~0=v_~m_st~0_6} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 23745#L531-2 [4343] L531-2-->L988: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 23742#L988 [3240] L988-->L995: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 23738#L995 [4354] L995-->L1014-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_6|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_#t~ret17, ULTIMATE.start_stop_simulation_#res] 23544#L1014-1 [2020-06-22 00:13:14,434 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:14,434 INFO L82 PathProgramCache]: Analyzing trace with hash 200402967, now seen corresponding path program 1 times [2020-06-22 00:13:14,434 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:14,434 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:14,435 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:14,435 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:14,435 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:14,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:14,462 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:14,463 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:14,463 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2020-06-22 00:13:14,463 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-06-22 00:13:14,463 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:14,464 INFO L82 PathProgramCache]: Analyzing trace with hash 193525407, now seen corresponding path program 2 times [2020-06-22 00:13:14,464 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:14,464 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:14,465 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:14,465 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:14,465 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:14,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:14,486 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:14,487 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:14,487 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2020-06-22 00:13:14,487 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-06-22 00:13:14,487 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2020-06-22 00:13:14,488 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2020-06-22 00:13:14,488 INFO L87 Difference]: Start difference. First operand 926 states and 1696 transitions. cyclomatic complexity: 771 Second operand 4 states. [2020-06-22 00:13:15,242 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-06-22 00:13:15,242 INFO L93 Difference]: Finished difference Result 926 states and 1672 transitions. [2020-06-22 00:13:15,242 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2020-06-22 00:13:15,243 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 926 states and 1672 transitions. [2020-06-22 00:13:15,246 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 851 [2020-06-22 00:13:15,252 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 926 states to 926 states and 1672 transitions. [2020-06-22 00:13:15,252 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 926 [2020-06-22 00:13:15,252 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 926 [2020-06-22 00:13:15,252 INFO L73 IsDeterministic]: Start isDeterministic. Operand 926 states and 1672 transitions. [2020-06-22 00:13:15,253 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-06-22 00:13:15,253 INFO L706 BuchiCegarLoop]: Abstraction has 926 states and 1672 transitions. [2020-06-22 00:13:15,254 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 926 states and 1672 transitions. [2020-06-22 00:13:15,263 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 926 to 926. [2020-06-22 00:13:15,264 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 926 states. [2020-06-22 00:13:15,266 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 926 states to 926 states and 1672 transitions. [2020-06-22 00:13:15,266 INFO L729 BuchiCegarLoop]: Abstraction has 926 states and 1672 transitions. [2020-06-22 00:13:15,266 INFO L609 BuchiCegarLoop]: Abstraction has 926 states and 1672 transitions. [2020-06-22 00:13:15,266 INFO L442 BuchiCegarLoop]: ======== Iteration 22============ [2020-06-22 00:13:15,266 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 926 states and 1672 transitions. [2020-06-22 00:13:15,268 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 851 [2020-06-22 00:13:15,269 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-06-22 00:13:15,269 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-06-22 00:13:15,270 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:15,270 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:15,271 INFO L794 eck$LassoCheckResult]: Stem: 25352#ULTIMATE.startENTRY [4266] ULTIMATE.startENTRY-->L444: Formula: (and (= 1 v_~t6_i~0_7) (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~M_E~0_37 2) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 0 v_~t6_pc~0_26) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_6~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= v_~T6_E~0_18 2) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~t6_st~0_24) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t6_pc~0=v_~t6_pc~0_26, ~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~T6_E~0=v_~T6_E~0_18, ~M_E~0=v_~M_E~0_37, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ~T4_E~0=v_~T4_E~0_18, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_4|, ~t6_i~0=v_~t6_i~0_7, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ULTIMATE.start_main_~__retres1~8=v_ULTIMATE.start_main_~__retres1~8_6, ~T2_E~0=v_~T2_E~0_18, ~t6_st~0=v_~t6_st~0_24, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_6~0=v_~E_6~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t6_pc~0, ~t5_i~0, ~t1_pc~0, ~t5_st~0, ~T6_E~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ~T4_E~0, ULTIMATE.start_start_simulation_#t~ret17, ~t6_i~0, ~t2_st~0, ~t2_pc~0, ULTIMATE.start_main_~__retres1~8, ~T2_E~0, ~t6_st~0, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_6~0, ULTIMATE.start_main_#res, ~E_2~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 24975#L444 [2453] L444-->L451-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 24976#L451-1 [3030] L451-1-->L456-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 25063#L456-1 [2574] L456-1-->L461-1: Formula: (and (= v_~t2_st~0_2 0) (= 1 v_~t2_i~0_3)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_2} AuxVars[] AssignedVars[~t2_st~0] 25064#L461-1 [2880] L461-1-->L466-1: Formula: (and (= v_~t3_st~0_3 0) (= v_~t3_i~0_3 1)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_3, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 24977#L466-1 [2457] L466-1-->L471-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 24978#L471-1 [3209] L471-1-->L476-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 25212#L476-1 [2761] L476-1-->L481-1: Formula: (and (= 1 v_~t6_i~0_3) (= v_~t6_st~0_4 0)) InVars {~t6_i~0=v_~t6_i~0_3} OutVars{~t6_st~0=v_~t6_st~0_4, ~t6_i~0=v_~t6_i~0_3} AuxVars[] AssignedVars[~t6_st~0] 25213#L481-1 [3652] L481-1-->L660-1: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 25363#L660-1 [3654] L660-1-->L665-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 24894#L665-1 [3655] L665-1-->L670-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 24895#L670-1 [3658] L670-1-->L675-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 24984#L675-1 [3659] L675-1-->L680-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 24985#L680-1 [3661] L680-1-->L685-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 25224#L685-1 [3663] L685-1-->L690-1: Formula: (< 0 v_~T6_E~0_4) InVars {~T6_E~0=v_~T6_E~0_4} OutVars{~T6_E~0=v_~T6_E~0_4} AuxVars[] AssignedVars[] 25225#L690-1 [3665] L690-1-->L695-1: Formula: (> v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 25108#L695-1 [3668] L695-1-->L700-1: Formula: (> v_~E_2~0_6 0) InVars {~E_2~0=v_~E_2~0_6} OutVars{~E_2~0=v_~E_2~0_6} AuxVars[] AssignedVars[] 25109#L700-1 [3670] L700-1-->L705-1: Formula: (> v_~E_3~0_6 0) InVars {~E_3~0=v_~E_3~0_6} OutVars{~E_3~0=v_~E_3~0_6} AuxVars[] AssignedVars[] 25339#L705-1 [3672] L705-1-->L710-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 25046#L710-1 [3674] L710-1-->L715-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 25047#L715-1 [3675] L715-1-->L720-1: Formula: (> v_~E_6~0_4 0) InVars {~E_6~0=v_~E_6~0_4} OutVars{~E_6~0=v_~E_6~0_4} AuxVars[] AssignedVars[] 24928#L720-1 [2412] L720-1-->L310: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_7, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_4|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_4|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_7, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_4, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_4, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_2|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_2|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_4|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_4|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_7, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_2|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_4} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 24929#L310 [3678] L310-->L310-2: Formula: (< v_~m_pc~0_5 1) InVars {~m_pc~0=v_~m_pc~0_5} OutVars{~m_pc~0=v_~m_pc~0_5} AuxVars[] AssignedVars[] 25080#L310-2 [2805] L310-2-->L321: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_11 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 25078#L321 [4267] L321-->L815: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 25079#L815 [2976] L815-->L815-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_12) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} AuxVars[] AssignedVars[] 25335#L815-2 [2961] L815-2-->L329: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 25268#L329 [3684] L329-->L329-2: Formula: (> v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 25270#L329-2 [2861] L329-2-->L340: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 25266#L340 [4268] L340-->L823: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 25267#L823 [3688] L823-->L823-2: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___0~0_11 0) (= v_~t1_st~0_5 0)) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_11} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_11, ~t1_st~0=v_~t1_st~0_5} AuxVars[] AssignedVars[~t1_st~0] 25423#L823-2 [3235] L823-2-->L348: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_4|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 25405#L348 [3690] L348-->L348-2: Formula: (< v_~t2_pc~0_5 1) InVars {~t2_pc~0=v_~t2_pc~0_5} OutVars{~t2_pc~0=v_~t2_pc~0_5} AuxVars[] AssignedVars[] 25407#L348-2 [3153] L348-2-->L359: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 25404#L359 [4269] L359-->L831: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 25053#L831 [3694] L831-->L831-2: Formula: (and (= v_~t2_st~0_5 0) (> v_ULTIMATE.start_activate_threads_~tmp___1~0_11 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_11} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_11, ~t2_st~0=v_~t2_st~0_5} AuxVars[] AssignedVars[~t2_st~0] 25041#L831-2 [2520] L831-2-->L367: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_4|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 24980#L367 [3695] L367-->L367-2: Formula: (> 1 v_~t3_pc~0_5) InVars {~t3_pc~0=v_~t3_pc~0_5} OutVars{~t3_pc~0=v_~t3_pc~0_5} AuxVars[] AssignedVars[] 24957#L367-2 [2438] L367-2-->L378: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 24958#L378 [4270] L378-->L839: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 24979#L839 [2791] L839-->L839-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} AuxVars[] AssignedVars[] 25237#L839-2 [2794] L839-2-->L386: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_7, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 25153#L386 [2675] L386-->L387: Formula: (= v_~t4_pc~0_4 1) InVars {~t4_pc~0=v_~t4_pc~0_4} OutVars{~t4_pc~0=v_~t4_pc~0_4} AuxVars[] AssignedVars[] 25069#L387 [2588] L387-->L397: Formula: (and (= v_~E_4~0_7 1) (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_10 1)) InVars {~E_4~0=v_~E_4~0_7} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_10, ~E_4~0=v_~E_4~0_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 25071#L397 [4271] L397-->L847: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 25152#L847 [3084] L847-->L847-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} AuxVars[] AssignedVars[] 25367#L847-2 [3064] L847-2-->L405: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_4|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 25368#L405 [3708] L405-->L405-2: Formula: (> 1 v_~t5_pc~0_5) InVars {~t5_pc~0=v_~t5_pc~0_5} OutVars{~t5_pc~0=v_~t5_pc~0_5} AuxVars[] AssignedVars[] 25297#L405-2 [2940] L405-2-->L416: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 25323#L416 [4272] L416-->L855: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 25374#L855 [3711] L855-->L855-2: Formula: (and (> v_ULTIMATE.start_activate_threads_~tmp___4~0_11 0) (= v_~t5_st~0_7 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_11} OutVars{~t5_st~0=v_~t5_st~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_11} AuxVars[] AssignedVars[~t5_st~0] 25375#L855-2 [3093] L855-2-->L424: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_4|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 25024#L424 [3714] L424-->L424-2: Formula: (> v_~t6_pc~0_5 1) InVars {~t6_pc~0=v_~t6_pc~0_5} OutVars{~t6_pc~0=v_~t6_pc~0_5} AuxVars[] AssignedVars[] 25025#L424-2 [2503] L424-2-->L435: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 25021#L435 [4273] L435-->L863: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___5~0_49 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_28|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_28|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 24944#L863 [2425] L863-->L863-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___5~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} AuxVars[] AssignedVars[] 24918#L863-2 [3720] L863-2-->L733-1: Formula: (< v_~M_E~0_15 1) InVars {~M_E~0=v_~M_E~0_15} OutVars{~M_E~0=v_~M_E~0_15} AuxVars[] AssignedVars[] 24919#L733-1 [3722] L733-1-->L738-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 25337#L738-1 [3723] L738-1-->L743-1: Formula: (< 1 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 25044#L743-1 [3726] L743-1-->L748-1: Formula: (< 1 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 25045#L748-1 [3728] L748-1-->L753-1: Formula: (> v_~T4_E~0_10 1) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 24923#L753-1 [3729] L753-1-->L758-1: Formula: (< 1 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 24924#L758-1 [3732] L758-1-->L763-1: Formula: (< v_~T6_E~0_10 1) InVars {~T6_E~0=v_~T6_E~0_10} OutVars{~T6_E~0=v_~T6_E~0_10} AuxVars[] AssignedVars[] 24996#L763-1 [3733] L763-1-->L768-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 24997#L768-1 [3736] L768-1-->L773-1: Formula: (< 1 v_~E_2~0_14) InVars {~E_2~0=v_~E_2~0_14} OutVars{~E_2~0=v_~E_2~0_14} AuxVars[] AssignedVars[] 25216#L773-1 [3737] L773-1-->L778-1: Formula: (< 1 v_~E_3~0_14) InVars {~E_3~0=v_~E_3~0_14} OutVars{~E_3~0=v_~E_3~0_14} AuxVars[] AssignedVars[] 25217#L778-1 [3740] L778-1-->L783-1: Formula: (< 1 v_~E_4~0_14) InVars {~E_4~0=v_~E_4~0_14} OutVars{~E_4~0=v_~E_4~0_14} AuxVars[] AssignedVars[] 25101#L783-1 [3741] L783-1-->L788-1: Formula: (< 1 v_~E_5~0_14) InVars {~E_5~0=v_~E_5~0_14} OutVars{~E_5~0=v_~E_5~0_14} AuxVars[] AssignedVars[] 25102#L788-1 [3744] L788-1-->L1014-1: Formula: (< 1 v_~E_6~0_14) InVars {~E_6~0=v_~E_6~0_14} OutVars{~E_6~0=v_~E_6~0_14} AuxVars[] AssignedVars[] 24933#L1014-1 [2020-06-22 00:13:15,272 INFO L796 eck$LassoCheckResult]: Loop: 24933#L1014-1 [4274] L1014-1-->L635: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp_ndt_7~0=v_ULTIMATE.start_eval_~tmp_ndt_7~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp_ndt_7~0] 24900#L635 [4275] L635-->L494: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_37} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 25293#L494 [2876] L494-->L531: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21 1) (= v_~m_st~0_8 0)) InVars {~m_st~0=v_~m_st~0_8} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21, ~m_st~0=v_~m_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 24968#L531 [4276] L531-->L546: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 25204#L546 [4278] L546-->L660-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 25410#L660-2 [3747] L660-2-->L660-4: Formula: (> v_~M_E~0_30 0) InVars {~M_E~0=v_~M_E~0_30} OutVars{~M_E~0=v_~M_E~0_30} AuxVars[] AssignedVars[] 25608#L660-4 [3058] L660-4-->L665-3: Formula: (and (= v_~T1_E~0_11 1) (= v_~T1_E~0_12 0)) InVars {~T1_E~0=v_~T1_E~0_12} OutVars{~T1_E~0=v_~T1_E~0_11} AuxVars[] AssignedVars[~T1_E~0] 25606#L665-3 [3756] L665-3-->L670-3: Formula: (< 0 v_~T2_E~0_13) InVars {~T2_E~0=v_~T2_E~0_13} OutVars{~T2_E~0=v_~T2_E~0_13} AuxVars[] AssignedVars[] 25604#L670-3 [3762] L670-3-->L675-3: Formula: (< 0 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 25602#L675-3 [3768] L675-3-->L680-3: Formula: (> v_~T4_E~0_13 0) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 25598#L680-3 [3776] L680-3-->L685-3: Formula: (< 0 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 25595#L685-3 [3785] L685-3-->L690-3: Formula: (> v_~T6_E~0_13 0) InVars {~T6_E~0=v_~T6_E~0_13} OutVars{~T6_E~0=v_~T6_E~0_13} AuxVars[] AssignedVars[] 25592#L690-3 [3795] L690-3-->L695-3: Formula: (< 0 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 25589#L695-3 [3805] L695-3-->L700-3: Formula: (< 0 v_~E_2~0_31) InVars {~E_2~0=v_~E_2~0_31} OutVars{~E_2~0=v_~E_2~0_31} AuxVars[] AssignedVars[] 25588#L700-3 [3818] L700-3-->L705-3: Formula: (< 0 v_~E_3~0_31) InVars {~E_3~0=v_~E_3~0_31} OutVars{~E_3~0=v_~E_3~0_31} AuxVars[] AssignedVars[] 25584#L705-3 [2688] L705-3-->L710-3: Formula: (and (= v_~E_4~0_29 1) (= 0 v_~E_4~0_30)) InVars {~E_4~0=v_~E_4~0_30} OutVars{~E_4~0=v_~E_4~0_29} AuxVars[] AssignedVars[~E_4~0] 25581#L710-3 [3844] L710-3-->L715-3: Formula: (< 0 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 25578#L715-3 [3854] L715-3-->L720-3: Formula: (< 0 v_~E_6~0_31) InVars {~E_6~0=v_~E_6~0_31} OutVars{~E_6~0=v_~E_6~0_31} AuxVars[] AssignedVars[] 25575#L720-3 [2388] L720-3-->L310-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_43, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_43, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_25|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_25|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_25|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_43, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_43, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_43, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_25|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_25|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_25|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_25|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_43, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_25|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_43, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_43} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 25226#L310-21 [3870] L310-21-->L310-23: Formula: (< v_~m_pc~0_24 1) InVars {~m_pc~0=v_~m_pc~0_24} OutVars{~m_pc~0=v_~m_pc~0_24} AuxVars[] AssignedVars[] 25227#L310-23 [2785] L310-23-->L321-7: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_47 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_47} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 25767#L321-7 [4303] L321-7-->L815-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 25766#L815-21 [2667] L815-21-->L815-23: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_48) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_48} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_48} AuxVars[] AssignedVars[] 25765#L815-23 [2638] L815-23-->L329-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 25764#L329-21 [3911] L329-21-->L329-23: Formula: (< v_~t1_pc~0_24 1) InVars {~t1_pc~0=v_~t1_pc~0_24} OutVars{~t1_pc~0=v_~t1_pc~0_24} AuxVars[] AssignedVars[] 25762#L329-23 [3052] L329-23-->L340-7: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 25761#L340-7 [4310] L340-7-->L823-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 25760#L823-21 [2931] L823-21-->L823-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} AuxVars[] AssignedVars[] 25759#L823-23 [2934] L823-23-->L348-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_25|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 25757#L348-21 [3953] L348-21-->L348-23: Formula: (> 1 v_~t2_pc~0_24) InVars {~t2_pc~0=v_~t2_pc~0_24} OutVars{~t2_pc~0=v_~t2_pc~0_24} AuxVars[] AssignedVars[] 25756#L348-23 [3319] L348-23-->L359-7: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 25755#L359-7 [4317] L359-7-->L831-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 25754#L831-21 [2490] L831-21-->L831-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} AuxVars[] AssignedVars[] 25753#L831-23 [3197] L831-23-->L367-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_25|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 25752#L367-21 [3995] L367-21-->L367-23: Formula: (> v_~t3_pc~0_24 1) InVars {~t3_pc~0=v_~t3_pc~0_24} OutVars{~t3_pc~0=v_~t3_pc~0_24} AuxVars[] AssignedVars[] 25750#L367-23 [2385] L367-23-->L378-7: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 25749#L378-7 [4324] L378-7-->L839-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 25748#L839-21 [4023] L839-21-->L839-23: Formula: (and (= v_~t3_st~0_21 0) (> v_ULTIMATE.start_activate_threads_~tmp___2~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} OutVars{~t3_st~0=v_~t3_st~0_21, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} AuxVars[] AssignedVars[~t3_st~0] 25747#L839-23 [2722] L839-23-->L386-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_49, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 25746#L386-21 [2617] L386-21-->L387-7: Formula: (= 1 v_~t4_pc~0_23) InVars {~t4_pc~0=v_~t4_pc~0_23} OutVars{~t4_pc~0=v_~t4_pc~0_23} AuxVars[] AssignedVars[] 25744#L387-7 [2818] L387-7-->L397-7: Formula: (and (= 1 v_~E_4~0_32) (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_52 1)) InVars {~E_4~0=v_~E_4~0_32} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_52, ~E_4~0=v_~E_4~0_32} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 25743#L397-7 [4331] L397-7-->L847-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 25742#L847-21 [4065] L847-21-->L847-23: Formula: (and (= v_~t4_st~0_22 0) (< v_ULTIMATE.start_activate_threads_~tmp___3~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47, ~t4_st~0=v_~t4_st~0_22} AuxVars[] AssignedVars[~t4_st~0] 25741#L847-23 [2983] L847-23-->L405-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_25|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 25739#L405-21 [4080] L405-21-->L405-23: Formula: (> v_~t5_pc~0_24 1) InVars {~t5_pc~0=v_~t5_pc~0_24} OutVars{~t5_pc~0=v_~t5_pc~0_24} AuxVars[] AssignedVars[] 25737#L405-23 [2891] L405-23-->L416-7: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 25735#L416-7 [4338] L416-7-->L855-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 25733#L855-21 [3251] L855-21-->L855-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} AuxVars[] AssignedVars[] 25732#L855-23 [3257] L855-23-->L424-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_25|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 25722#L424-21 [4121] L424-21-->L424-23: Formula: (< 1 v_~t6_pc~0_24) InVars {~t6_pc~0=v_~t6_pc~0_24} OutVars{~t6_pc~0=v_~t6_pc~0_24} AuxVars[] AssignedVars[] 25720#L424-23 [3177] L424-23-->L435-7: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 25718#L435-7 [4340] L435-7-->L863-21: Formula: (and (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___5~0_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_35|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_41|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 25716#L863-21 [4135] L863-21-->L863-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___5~0_47 0) (= v_~t6_st~0_22 0)) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} OutVars{~t6_st~0=v_~t6_st~0_22, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} AuxVars[] AssignedVars[~t6_st~0] 25054#L863-23 [4137] L863-23-->L733-3: Formula: (< v_~M_E~0_35 1) InVars {~M_E~0=v_~M_E~0_35} OutVars{~M_E~0=v_~M_E~0_35} AuxVars[] AssignedVars[] 25055#L733-3 [3184] L733-3-->L738-3: Formula: (and (= v_~T1_E~0_15 1) (= v_~T1_E~0_14 2)) InVars {~T1_E~0=v_~T1_E~0_15} OutVars{~T1_E~0=v_~T1_E~0_14} AuxVars[] AssignedVars[~T1_E~0] 25340#L738-3 [4142] L738-3-->L743-3: Formula: (< 1 v_~T2_E~0_16) InVars {~T2_E~0=v_~T2_E~0_16} OutVars{~T2_E~0=v_~T2_E~0_16} AuxVars[] AssignedVars[] 25033#L743-3 [4143] L743-3-->L748-3: Formula: (< 1 v_~T3_E~0_16) InVars {~T3_E~0=v_~T3_E~0_16} OutVars{~T3_E~0=v_~T3_E~0_16} AuxVars[] AssignedVars[] 25034#L748-3 [4145] L748-3-->L753-3: Formula: (> v_~T4_E~0_16 1) InVars {~T4_E~0=v_~T4_E~0_16} OutVars{~T4_E~0=v_~T4_E~0_16} AuxVars[] AssignedVars[] 24890#L753-3 [4148] L753-3-->L758-3: Formula: (< 1 v_~T5_E~0_16) InVars {~T5_E~0=v_~T5_E~0_16} OutVars{~T5_E~0=v_~T5_E~0_16} AuxVars[] AssignedVars[] 24891#L758-3 [4149] L758-3-->L763-3: Formula: (> v_~T6_E~0_16 1) InVars {~T6_E~0=v_~T6_E~0_16} OutVars{~T6_E~0=v_~T6_E~0_16} AuxVars[] AssignedVars[] 24982#L763-3 [4151] L763-3-->L768-3: Formula: (< 1 v_~E_1~0_36) InVars {~E_1~0=v_~E_1~0_36} OutVars{~E_1~0=v_~E_1~0_36} AuxVars[] AssignedVars[] 24983#L768-3 [4154] L768-3-->L773-3: Formula: (< 1 v_~E_2~0_36) InVars {~E_2~0=v_~E_2~0_36} OutVars{~E_2~0=v_~E_2~0_36} AuxVars[] AssignedVars[] 25221#L773-3 [4156] L773-3-->L778-3: Formula: (< 1 v_~E_3~0_36) InVars {~E_3~0=v_~E_3~0_36} OutVars{~E_3~0=v_~E_3~0_36} AuxVars[] AssignedVars[] 25222#L778-3 [3308] L778-3-->L783-3: Formula: (and (= 1 v_~E_4~0_35) (= v_~E_4~0_34 2)) InVars {~E_4~0=v_~E_4~0_35} OutVars{~E_4~0=v_~E_4~0_34} AuxVars[] AssignedVars[~E_4~0] 25106#L783-3 [4160] L783-3-->L788-3: Formula: (< 1 v_~E_5~0_36) InVars {~E_5~0=v_~E_5~0_36} OutVars{~E_5~0=v_~E_5~0_36} AuxVars[] AssignedVars[] 25107#L788-3 [4162] L788-3-->L793-3: Formula: (< 1 v_~E_6~0_36) InVars {~E_6~0=v_~E_6~0_36} OutVars{~E_6~0=v_~E_6~0_36} AuxVars[] AssignedVars[] 25338#L793-3 [2966] L793-3-->L494-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_30} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 25294#L494-1 [2878] L494-1-->L531-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33 1) (= 0 v_~m_st~0_21)) InVars {~m_st~0=v_~m_st~0_21} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33, ~m_st~0=v_~m_st~0_21} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 24970#L531-1 [4341] L531-1-->L1033: Formula: (and (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp~3] 25205#L1033 [4169] L1033-->L1033-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_6) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} AuxVars[] AssignedVars[] 24939#L1033-1 [2919] L1033-1-->L494-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_3|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_6, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_exists_runnable_thread_~__retres1~7, ULTIMATE.start_stop_simulation_#res] 25295#L494-2 [2882] L494-2-->L531-2: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9 1) (= v_~m_st~0_6 0)) InVars {~m_st~0=v_~m_st~0_6} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9, ~m_st~0=v_~m_st~0_6} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 24974#L531-2 [4343] L531-2-->L988: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 25209#L988 [3240] L988-->L995: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 24932#L995 [4354] L995-->L1014-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_6|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_#t~ret17, ULTIMATE.start_stop_simulation_#res] 24933#L1014-1 [2020-06-22 00:13:15,272 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:15,272 INFO L82 PathProgramCache]: Analyzing trace with hash 1055111544, now seen corresponding path program 1 times [2020-06-22 00:13:15,273 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:15,273 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:15,274 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:15,274 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2020-06-22 00:13:15,274 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:15,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:15,300 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:15,301 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:15,301 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-06-22 00:13:15,301 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-06-22 00:13:15,302 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:15,302 INFO L82 PathProgramCache]: Analyzing trace with hash 2072517841, now seen corresponding path program 1 times [2020-06-22 00:13:15,302 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:15,302 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:15,303 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:15,303 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:15,303 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:15,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:15,324 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:15,324 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:15,324 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2020-06-22 00:13:15,325 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-06-22 00:13:15,325 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-06-22 00:13:15,325 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-06-22 00:13:15,325 INFO L87 Difference]: Start difference. First operand 926 states and 1672 transitions. cyclomatic complexity: 747 Second operand 3 states. [2020-06-22 00:13:16,316 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-06-22 00:13:16,317 INFO L93 Difference]: Finished difference Result 1746 states and 3146 transitions. [2020-06-22 00:13:16,317 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-06-22 00:13:16,317 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1746 states and 3146 transitions. [2020-06-22 00:13:16,324 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1672 [2020-06-22 00:13:16,333 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1746 states to 1746 states and 3146 transitions. [2020-06-22 00:13:16,333 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1746 [2020-06-22 00:13:16,334 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1746 [2020-06-22 00:13:16,335 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1746 states and 3146 transitions. [2020-06-22 00:13:16,336 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-06-22 00:13:16,336 INFO L706 BuchiCegarLoop]: Abstraction has 1746 states and 3146 transitions. [2020-06-22 00:13:16,337 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1746 states and 3146 transitions. [2020-06-22 00:13:16,353 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1746 to 1676. [2020-06-22 00:13:16,353 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1676 states. [2020-06-22 00:13:16,357 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1676 states to 1676 states and 3024 transitions. [2020-06-22 00:13:16,357 INFO L729 BuchiCegarLoop]: Abstraction has 1676 states and 3024 transitions. [2020-06-22 00:13:16,357 INFO L609 BuchiCegarLoop]: Abstraction has 1676 states and 3024 transitions. [2020-06-22 00:13:16,357 INFO L442 BuchiCegarLoop]: ======== Iteration 23============ [2020-06-22 00:13:16,357 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1676 states and 3024 transitions. [2020-06-22 00:13:16,361 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1602 [2020-06-22 00:13:16,362 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-06-22 00:13:16,362 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-06-22 00:13:16,363 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:16,363 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:16,364 INFO L794 eck$LassoCheckResult]: Stem: 28031#ULTIMATE.startENTRY [4266] ULTIMATE.startENTRY-->L444: Formula: (and (= 1 v_~t6_i~0_7) (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~M_E~0_37 2) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 0 v_~t6_pc~0_26) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_6~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= v_~T6_E~0_18 2) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~t6_st~0_24) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t6_pc~0=v_~t6_pc~0_26, ~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~T6_E~0=v_~T6_E~0_18, ~M_E~0=v_~M_E~0_37, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ~T4_E~0=v_~T4_E~0_18, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_4|, ~t6_i~0=v_~t6_i~0_7, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ULTIMATE.start_main_~__retres1~8=v_ULTIMATE.start_main_~__retres1~8_6, ~T2_E~0=v_~T2_E~0_18, ~t6_st~0=v_~t6_st~0_24, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_6~0=v_~E_6~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t6_pc~0, ~t5_i~0, ~t1_pc~0, ~t5_st~0, ~T6_E~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ~T4_E~0, ULTIMATE.start_start_simulation_#t~ret17, ~t6_i~0, ~t2_st~0, ~t2_pc~0, ULTIMATE.start_main_~__retres1~8, ~T2_E~0, ~t6_st~0, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_6~0, ULTIMATE.start_main_#res, ~E_2~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 27652#L444 [2453] L444-->L451-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 27653#L451-1 [3030] L451-1-->L456-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 27741#L456-1 [2574] L456-1-->L461-1: Formula: (and (= v_~t2_st~0_2 0) (= 1 v_~t2_i~0_3)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_2} AuxVars[] AssignedVars[~t2_st~0] 27742#L461-1 [2880] L461-1-->L466-1: Formula: (and (= v_~t3_st~0_3 0) (= v_~t3_i~0_3 1)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_3, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 27657#L466-1 [2457] L466-1-->L471-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 27658#L471-1 [3209] L471-1-->L476-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 27891#L476-1 [2761] L476-1-->L481-1: Formula: (and (= 1 v_~t6_i~0_3) (= v_~t6_st~0_4 0)) InVars {~t6_i~0=v_~t6_i~0_3} OutVars{~t6_st~0=v_~t6_st~0_4, ~t6_i~0=v_~t6_i~0_3} AuxVars[] AssignedVars[~t6_st~0] 27892#L481-1 [3652] L481-1-->L660-1: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 28045#L660-1 [3654] L660-1-->L665-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 27572#L665-1 [3655] L665-1-->L670-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 27573#L670-1 [3658] L670-1-->L675-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 27664#L675-1 [3659] L675-1-->L680-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 27665#L680-1 [3661] L680-1-->L685-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 27902#L685-1 [3663] L685-1-->L690-1: Formula: (< 0 v_~T6_E~0_4) InVars {~T6_E~0=v_~T6_E~0_4} OutVars{~T6_E~0=v_~T6_E~0_4} AuxVars[] AssignedVars[] 27903#L690-1 [3665] L690-1-->L695-1: Formula: (> v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 27785#L695-1 [3668] L695-1-->L700-1: Formula: (> v_~E_2~0_6 0) InVars {~E_2~0=v_~E_2~0_6} OutVars{~E_2~0=v_~E_2~0_6} AuxVars[] AssignedVars[] 27786#L700-1 [3670] L700-1-->L705-1: Formula: (> v_~E_3~0_6 0) InVars {~E_3~0=v_~E_3~0_6} OutVars{~E_3~0=v_~E_3~0_6} AuxVars[] AssignedVars[] 28017#L705-1 [3672] L705-1-->L710-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 27725#L710-1 [3674] L710-1-->L715-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 27726#L715-1 [3675] L715-1-->L720-1: Formula: (> v_~E_6~0_4 0) InVars {~E_6~0=v_~E_6~0_4} OutVars{~E_6~0=v_~E_6~0_4} AuxVars[] AssignedVars[] 27608#L720-1 [2412] L720-1-->L310: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_7, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_4|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_4|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_7, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_4, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_4, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_2|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_2|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_4|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_4|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_7, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_2|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_4} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 27609#L310 [3678] L310-->L310-2: Formula: (< v_~m_pc~0_5 1) InVars {~m_pc~0=v_~m_pc~0_5} OutVars{~m_pc~0=v_~m_pc~0_5} AuxVars[] AssignedVars[] 27757#L310-2 [2805] L310-2-->L321: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_11 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 27752#L321 [4267] L321-->L815: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 27753#L815 [2976] L815-->L815-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_12) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} AuxVars[] AssignedVars[] 28013#L815-2 [2961] L815-2-->L329: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 27946#L329 [3683] L329-->L329-2: Formula: (< v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 27947#L329-2 [2861] L329-2-->L340: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 27942#L340 [4268] L340-->L823: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 27943#L823 [3688] L823-->L823-2: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___0~0_11 0) (= v_~t1_st~0_5 0)) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_11} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_11, ~t1_st~0=v_~t1_st~0_5} AuxVars[] AssignedVars[~t1_st~0] 28113#L823-2 [3235] L823-2-->L348: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_4|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 28095#L348 [3690] L348-->L348-2: Formula: (< v_~t2_pc~0_5 1) InVars {~t2_pc~0=v_~t2_pc~0_5} OutVars{~t2_pc~0=v_~t2_pc~0_5} AuxVars[] AssignedVars[] 28097#L348-2 [3153] L348-2-->L359: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 28094#L359 [4269] L359-->L831: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 27732#L831 [3694] L831-->L831-2: Formula: (and (= v_~t2_st~0_5 0) (> v_ULTIMATE.start_activate_threads_~tmp___1~0_11 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_11} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_11, ~t2_st~0=v_~t2_st~0_5} AuxVars[] AssignedVars[~t2_st~0] 27720#L831-2 [2520] L831-2-->L367: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_4|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 27660#L367 [3695] L367-->L367-2: Formula: (> 1 v_~t3_pc~0_5) InVars {~t3_pc~0=v_~t3_pc~0_5} OutVars{~t3_pc~0=v_~t3_pc~0_5} AuxVars[] AssignedVars[] 27638#L367-2 [2438] L367-2-->L378: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 27639#L378 [4270] L378-->L839: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 27659#L839 [2791] L839-->L839-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} AuxVars[] AssignedVars[] 27912#L839-2 [2794] L839-2-->L386: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_7, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 27828#L386 [2675] L386-->L387: Formula: (= v_~t4_pc~0_4 1) InVars {~t4_pc~0=v_~t4_pc~0_4} OutVars{~t4_pc~0=v_~t4_pc~0_4} AuxVars[] AssignedVars[] 27746#L387 [2588] L387-->L397: Formula: (and (= v_~E_4~0_7 1) (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_10 1)) InVars {~E_4~0=v_~E_4~0_7} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_10, ~E_4~0=v_~E_4~0_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 27748#L397 [4271] L397-->L847: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 27827#L847 [3084] L847-->L847-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} AuxVars[] AssignedVars[] 28053#L847-2 [3064] L847-2-->L405: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_4|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 28054#L405 [3708] L405-->L405-2: Formula: (> 1 v_~t5_pc~0_5) InVars {~t5_pc~0=v_~t5_pc~0_5} OutVars{~t5_pc~0=v_~t5_pc~0_5} AuxVars[] AssignedVars[] 27974#L405-2 [2940] L405-2-->L416: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 28001#L416 [4272] L416-->L855: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 28063#L855 [3711] L855-->L855-2: Formula: (and (> v_ULTIMATE.start_activate_threads_~tmp___4~0_11 0) (= v_~t5_st~0_7 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_11} OutVars{~t5_st~0=v_~t5_st~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_11} AuxVars[] AssignedVars[~t5_st~0] 28064#L855-2 [3093] L855-2-->L424: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_4|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 27704#L424 [3714] L424-->L424-2: Formula: (> v_~t6_pc~0_5 1) InVars {~t6_pc~0=v_~t6_pc~0_5} OutVars{~t6_pc~0=v_~t6_pc~0_5} AuxVars[] AssignedVars[] 27705#L424-2 [2503] L424-2-->L435: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 27701#L435 [4273] L435-->L863: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___5~0_49 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_28|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_28|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 27622#L863 [2425] L863-->L863-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___5~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} AuxVars[] AssignedVars[] 27595#L863-2 [3720] L863-2-->L733-1: Formula: (< v_~M_E~0_15 1) InVars {~M_E~0=v_~M_E~0_15} OutVars{~M_E~0=v_~M_E~0_15} AuxVars[] AssignedVars[] 27596#L733-1 [3722] L733-1-->L738-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 28015#L738-1 [3723] L738-1-->L743-1: Formula: (< 1 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 27723#L743-1 [3726] L743-1-->L748-1: Formula: (< 1 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 27724#L748-1 [3728] L748-1-->L753-1: Formula: (> v_~T4_E~0_10 1) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 27603#L753-1 [3729] L753-1-->L758-1: Formula: (< 1 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 27604#L758-1 [3732] L758-1-->L763-1: Formula: (< v_~T6_E~0_10 1) InVars {~T6_E~0=v_~T6_E~0_10} OutVars{~T6_E~0=v_~T6_E~0_10} AuxVars[] AssignedVars[] 27676#L763-1 [3733] L763-1-->L768-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 27677#L768-1 [3736] L768-1-->L773-1: Formula: (< 1 v_~E_2~0_14) InVars {~E_2~0=v_~E_2~0_14} OutVars{~E_2~0=v_~E_2~0_14} AuxVars[] AssignedVars[] 27895#L773-1 [3737] L773-1-->L778-1: Formula: (< 1 v_~E_3~0_14) InVars {~E_3~0=v_~E_3~0_14} OutVars{~E_3~0=v_~E_3~0_14} AuxVars[] AssignedVars[] 27896#L778-1 [3740] L778-1-->L783-1: Formula: (< 1 v_~E_4~0_14) InVars {~E_4~0=v_~E_4~0_14} OutVars{~E_4~0=v_~E_4~0_14} AuxVars[] AssignedVars[] 27776#L783-1 [3741] L783-1-->L788-1: Formula: (< 1 v_~E_5~0_14) InVars {~E_5~0=v_~E_5~0_14} OutVars{~E_5~0=v_~E_5~0_14} AuxVars[] AssignedVars[] 27777#L788-1 [3744] L788-1-->L1014-1: Formula: (< 1 v_~E_6~0_14) InVars {~E_6~0=v_~E_6~0_14} OutVars{~E_6~0=v_~E_6~0_14} AuxVars[] AssignedVars[] 27616#L1014-1 [2020-06-22 00:13:16,365 INFO L796 eck$LassoCheckResult]: Loop: 27616#L1014-1 [4274] L1014-1-->L635: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp_ndt_7~0=v_ULTIMATE.start_eval_~tmp_ndt_7~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp_ndt_7~0] 27578#L635 [4275] L635-->L494: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_37} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 27970#L494 [2876] L494-->L531: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21 1) (= v_~m_st~0_8 0)) InVars {~m_st~0=v_~m_st~0_8} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21, ~m_st~0=v_~m_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 27648#L531 [4276] L531-->L546: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 27883#L546 [4278] L546-->L660-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 28046#L660-2 [3747] L660-2-->L660-4: Formula: (> v_~M_E~0_30 0) InVars {~M_E~0=v_~M_E~0_30} OutVars{~M_E~0=v_~M_E~0_30} AuxVars[] AssignedVars[] 28047#L660-4 [3058] L660-4-->L665-3: Formula: (and (= v_~T1_E~0_11 1) (= v_~T1_E~0_12 0)) InVars {~T1_E~0=v_~T1_E~0_12} OutVars{~T1_E~0=v_~T1_E~0_11} AuxVars[] AssignedVars[~T1_E~0] 27588#L665-3 [3756] L665-3-->L670-3: Formula: (< 0 v_~T2_E~0_13) InVars {~T2_E~0=v_~T2_E~0_13} OutVars{~T2_E~0=v_~T2_E~0_13} AuxVars[] AssignedVars[] 27589#L670-3 [3762] L670-3-->L675-3: Formula: (< 0 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 27979#L675-3 [3768] L675-3-->L680-3: Formula: (> v_~T4_E~0_13 0) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 29176#L680-3 [3776] L680-3-->L685-3: Formula: (< 0 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 29175#L685-3 [3785] L685-3-->L690-3: Formula: (> v_~T6_E~0_13 0) InVars {~T6_E~0=v_~T6_E~0_13} OutVars{~T6_E~0=v_~T6_E~0_13} AuxVars[] AssignedVars[] 29174#L690-3 [3795] L690-3-->L695-3: Formula: (< 0 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 29173#L695-3 [3805] L695-3-->L700-3: Formula: (< 0 v_~E_2~0_31) InVars {~E_2~0=v_~E_2~0_31} OutVars{~E_2~0=v_~E_2~0_31} AuxVars[] AssignedVars[] 28100#L700-3 [3818] L700-3-->L705-3: Formula: (< 0 v_~E_3~0_31) InVars {~E_3~0=v_~E_3~0_31} OutVars{~E_3~0=v_~E_3~0_31} AuxVars[] AssignedVars[] 27837#L705-3 [2688] L705-3-->L710-3: Formula: (and (= v_~E_4~0_29 1) (= 0 v_~E_4~0_30)) InVars {~E_4~0=v_~E_4~0_30} OutVars{~E_4~0=v_~E_4~0_29} AuxVars[] AssignedVars[~E_4~0] 27717#L710-3 [3844] L710-3-->L715-3: Formula: (< 0 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 27718#L715-3 [3854] L715-3-->L720-3: Formula: (< 0 v_~E_6~0_31) InVars {~E_6~0=v_~E_6~0_31} OutVars{~E_6~0=v_~E_6~0_31} AuxVars[] AssignedVars[] 27579#L720-3 [2388] L720-3-->L310-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_43, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_43, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_25|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_25|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_25|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_43, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_43, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_43, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_25|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_25|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_25|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_25|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_43, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_25|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_43, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_43} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 27580#L310-21 [3870] L310-21-->L310-23: Formula: (< v_~m_pc~0_24 1) InVars {~m_pc~0=v_~m_pc~0_24} OutVars{~m_pc~0=v_~m_pc~0_24} AuxVars[] AssignedVars[] 27904#L310-23 [2785] L310-23-->L321-7: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_47 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_47} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 29160#L321-7 [4303] L321-7-->L815-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 27821#L815-21 [2667] L815-21-->L815-23: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_48) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_48} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_48} AuxVars[] AssignedVars[] 27800#L815-23 [2638] L815-23-->L329-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 27801#L329-21 [3911] L329-21-->L329-23: Formula: (< v_~t1_pc~0_24 1) InVars {~t1_pc~0=v_~t1_pc~0_24} OutVars{~t1_pc~0=v_~t1_pc~0_24} AuxVars[] AssignedVars[] 28043#L329-23 [3052] L329-23-->L340-7: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 27936#L340-7 [4310] L340-7-->L823-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 27937#L823-21 [2931] L823-21-->L823-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} AuxVars[] AssignedVars[] 27994#L823-23 [2934] L823-23-->L348-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_25|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 27996#L348-21 [3953] L348-21-->L348-23: Formula: (> 1 v_~t2_pc~0_24) InVars {~t2_pc~0=v_~t2_pc~0_24} OutVars{~t2_pc~0=v_~t2_pc~0_24} AuxVars[] AssignedVars[] 28118#L348-23 [3319] L348-23-->L359-7: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 28091#L359-7 [4317] L359-7-->L831-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 27695#L831-21 [2490] L831-21-->L831-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} AuxVars[] AssignedVars[] 27696#L831-23 [3197] L831-23-->L367-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_25|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 27605#L367-21 [3995] L367-21-->L367-23: Formula: (> v_~t3_pc~0_24 1) InVars {~t3_pc~0=v_~t3_pc~0_24} OutVars{~t3_pc~0=v_~t3_pc~0_24} AuxVars[] AssignedVars[] 27574#L367-23 [2385] L367-23-->L378-7: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 27575#L378-7 [4324] L378-7-->L839-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 27629#L839-21 [4023] L839-21-->L839-23: Formula: (and (= v_~t3_st~0_21 0) (> v_ULTIMATE.start_activate_threads_~tmp___2~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} OutVars{~t3_st~0=v_~t3_st~0_21, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} AuxVars[] AssignedVars[~t3_st~0] 27857#L839-23 [2722] L839-23-->L386-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_49, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 27780#L386-21 [4037] L386-21-->L386-23: Formula: (< 1 v_~t4_pc~0_24) InVars {~t4_pc~0=v_~t4_pc~0_24} OutVars{~t4_pc~0=v_~t4_pc~0_24} AuxVars[] AssignedVars[] 27781#L386-23 [2623] L386-23-->L397-7: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 27787#L397-7 [4331] L397-7-->L847-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 27818#L847-21 [4065] L847-21-->L847-23: Formula: (and (= v_~t4_st~0_22 0) (< v_ULTIMATE.start_activate_threads_~tmp___3~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47, ~t4_st~0=v_~t4_st~0_22} AuxVars[] AssignedVars[~t4_st~0] 28024#L847-23 [2983] L847-23-->L405-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_25|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 27983#L405-21 [4080] L405-21-->L405-23: Formula: (> v_~t5_pc~0_24 1) InVars {~t5_pc~0=v_~t5_pc~0_24} OutVars{~t5_pc~0=v_~t5_pc~0_24} AuxVars[] AssignedVars[] 27969#L405-23 [2891] L405-23-->L416-7: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 27977#L416-7 [4338] L416-7-->L855-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 27989#L855-21 [3251] L855-21-->L855-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} AuxVars[] AssignedVars[] 28116#L855-23 [3257] L855-23-->L424-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_25|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 28102#L424-21 [4121] L424-21-->L424-23: Formula: (< 1 v_~t6_pc~0_24) InVars {~t6_pc~0=v_~t6_pc~0_24} OutVars{~t6_pc~0=v_~t6_pc~0_24} AuxVars[] AssignedVars[] 28084#L424-23 [3177] L424-23-->L435-7: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 27690#L435-7 [4340] L435-7-->L863-21: Formula: (and (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___5~0_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_35|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_41|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 27691#L863-21 [4135] L863-21-->L863-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___5~0_47 0) (= v_~t6_st~0_22 0)) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} OutVars{~t6_st~0=v_~t6_st~0_22, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} AuxVars[] AssignedVars[~t6_st~0] 27733#L863-23 [4137] L863-23-->L733-3: Formula: (< v_~M_E~0_35 1) InVars {~M_E~0=v_~M_E~0_35} OutVars{~M_E~0=v_~M_E~0_35} AuxVars[] AssignedVars[] 27734#L733-3 [3184] L733-3-->L738-3: Formula: (and (= v_~T1_E~0_15 1) (= v_~T1_E~0_14 2)) InVars {~T1_E~0=v_~T1_E~0_15} OutVars{~T1_E~0=v_~T1_E~0_14} AuxVars[] AssignedVars[~T1_E~0] 28018#L738-3 [4142] L738-3-->L743-3: Formula: (< 1 v_~T2_E~0_16) InVars {~T2_E~0=v_~T2_E~0_16} OutVars{~T2_E~0=v_~T2_E~0_16} AuxVars[] AssignedVars[] 27713#L743-3 [4143] L743-3-->L748-3: Formula: (< 1 v_~T3_E~0_16) InVars {~T3_E~0=v_~T3_E~0_16} OutVars{~T3_E~0=v_~T3_E~0_16} AuxVars[] AssignedVars[] 27714#L748-3 [4145] L748-3-->L753-3: Formula: (> v_~T4_E~0_16 1) InVars {~T4_E~0=v_~T4_E~0_16} OutVars{~T4_E~0=v_~T4_E~0_16} AuxVars[] AssignedVars[] 27570#L753-3 [4148] L753-3-->L758-3: Formula: (< 1 v_~T5_E~0_16) InVars {~T5_E~0=v_~T5_E~0_16} OutVars{~T5_E~0=v_~T5_E~0_16} AuxVars[] AssignedVars[] 27571#L758-3 [4149] L758-3-->L763-3: Formula: (> v_~T6_E~0_16 1) InVars {~T6_E~0=v_~T6_E~0_16} OutVars{~T6_E~0=v_~T6_E~0_16} AuxVars[] AssignedVars[] 27662#L763-3 [4151] L763-3-->L768-3: Formula: (< 1 v_~E_1~0_36) InVars {~E_1~0=v_~E_1~0_36} OutVars{~E_1~0=v_~E_1~0_36} AuxVars[] AssignedVars[] 27663#L768-3 [4154] L768-3-->L773-3: Formula: (< 1 v_~E_2~0_36) InVars {~E_2~0=v_~E_2~0_36} OutVars{~E_2~0=v_~E_2~0_36} AuxVars[] AssignedVars[] 27900#L773-3 [4156] L773-3-->L778-3: Formula: (< 1 v_~E_3~0_36) InVars {~E_3~0=v_~E_3~0_36} OutVars{~E_3~0=v_~E_3~0_36} AuxVars[] AssignedVars[] 27901#L778-3 [3308] L778-3-->L783-3: Formula: (and (= 1 v_~E_4~0_35) (= v_~E_4~0_34 2)) InVars {~E_4~0=v_~E_4~0_35} OutVars{~E_4~0=v_~E_4~0_34} AuxVars[] AssignedVars[~E_4~0] 27783#L783-3 [4160] L783-3-->L788-3: Formula: (< 1 v_~E_5~0_36) InVars {~E_5~0=v_~E_5~0_36} OutVars{~E_5~0=v_~E_5~0_36} AuxVars[] AssignedVars[] 27784#L788-3 [4162] L788-3-->L793-3: Formula: (< 1 v_~E_6~0_36) InVars {~E_6~0=v_~E_6~0_36} OutVars{~E_6~0=v_~E_6~0_36} AuxVars[] AssignedVars[] 28016#L793-3 [2966] L793-3-->L494-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_30} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 27971#L494-1 [2878] L494-1-->L531-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33 1) (= 0 v_~m_st~0_21)) InVars {~m_st~0=v_~m_st~0_21} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33, ~m_st~0=v_~m_st~0_21} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 27650#L531-1 [4341] L531-1-->L1033: Formula: (and (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp~3] 27886#L1033 [4169] L1033-->L1033-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_6) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} AuxVars[] AssignedVars[] 27619#L1033-1 [2919] L1033-1-->L494-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_3|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_6, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_exists_runnable_thread_~__retres1~7, ULTIMATE.start_stop_simulation_#res] 27972#L494-2 [2882] L494-2-->L531-2: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9 1) (= v_~m_st~0_6 0)) InVars {~m_st~0=v_~m_st~0_6} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9, ~m_st~0=v_~m_st~0_6} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 27656#L531-2 [4343] L531-2-->L988: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 27890#L988 [3240] L988-->L995: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 27615#L995 [4354] L995-->L1014-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_6|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_#t~ret17, ULTIMATE.start_stop_simulation_#res] 27616#L1014-1 [2020-06-22 00:13:16,365 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:16,366 INFO L82 PathProgramCache]: Analyzing trace with hash 931038297, now seen corresponding path program 1 times [2020-06-22 00:13:16,366 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:16,366 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:16,367 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:16,367 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:16,367 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:16,374 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:16,408 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:16,408 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:16,409 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2020-06-22 00:13:16,409 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-06-22 00:13:16,409 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:16,409 INFO L82 PathProgramCache]: Analyzing trace with hash -216351806, now seen corresponding path program 1 times [2020-06-22 00:13:16,409 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:16,409 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:16,410 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:16,410 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:16,410 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:16,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:16,438 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:16,438 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:16,438 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2020-06-22 00:13:16,439 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-06-22 00:13:16,439 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2020-06-22 00:13:16,439 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2020-06-22 00:13:16,439 INFO L87 Difference]: Start difference. First operand 1676 states and 3024 transitions. cyclomatic complexity: 1349 Second operand 6 states. [2020-06-22 00:13:17,199 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-06-22 00:13:17,199 INFO L93 Difference]: Finished difference Result 1676 states and 2995 transitions. [2020-06-22 00:13:17,200 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2020-06-22 00:13:17,200 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1676 states and 2995 transitions. [2020-06-22 00:13:17,205 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1602 [2020-06-22 00:13:17,214 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1676 states to 1676 states and 2995 transitions. [2020-06-22 00:13:17,214 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1676 [2020-06-22 00:13:17,215 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1676 [2020-06-22 00:13:17,215 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1676 states and 2995 transitions. [2020-06-22 00:13:17,217 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-06-22 00:13:17,217 INFO L706 BuchiCegarLoop]: Abstraction has 1676 states and 2995 transitions. [2020-06-22 00:13:17,218 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1676 states and 2995 transitions. [2020-06-22 00:13:17,235 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1676 to 1676. [2020-06-22 00:13:17,235 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1676 states. [2020-06-22 00:13:17,238 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1676 states to 1676 states and 2995 transitions. [2020-06-22 00:13:17,238 INFO L729 BuchiCegarLoop]: Abstraction has 1676 states and 2995 transitions. [2020-06-22 00:13:17,238 INFO L609 BuchiCegarLoop]: Abstraction has 1676 states and 2995 transitions. [2020-06-22 00:13:17,239 INFO L442 BuchiCegarLoop]: ======== Iteration 24============ [2020-06-22 00:13:17,239 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1676 states and 2995 transitions. [2020-06-22 00:13:17,242 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1602 [2020-06-22 00:13:17,243 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-06-22 00:13:17,243 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-06-22 00:13:17,244 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:17,244 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:17,245 INFO L794 eck$LassoCheckResult]: Stem: 31407#ULTIMATE.startENTRY [4266] ULTIMATE.startENTRY-->L444: Formula: (and (= 1 v_~t6_i~0_7) (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~M_E~0_37 2) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 0 v_~t6_pc~0_26) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_6~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= v_~T6_E~0_18 2) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~t6_st~0_24) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t6_pc~0=v_~t6_pc~0_26, ~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~T6_E~0=v_~T6_E~0_18, ~M_E~0=v_~M_E~0_37, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ~T4_E~0=v_~T4_E~0_18, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_4|, ~t6_i~0=v_~t6_i~0_7, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ULTIMATE.start_main_~__retres1~8=v_ULTIMATE.start_main_~__retres1~8_6, ~T2_E~0=v_~T2_E~0_18, ~t6_st~0=v_~t6_st~0_24, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_6~0=v_~E_6~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t6_pc~0, ~t5_i~0, ~t1_pc~0, ~t5_st~0, ~T6_E~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ~T4_E~0, ULTIMATE.start_start_simulation_#t~ret17, ~t6_i~0, ~t2_st~0, ~t2_pc~0, ULTIMATE.start_main_~__retres1~8, ~T2_E~0, ~t6_st~0, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_6~0, ULTIMATE.start_main_#res, ~E_2~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 31024#L444 [2453] L444-->L451-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 31025#L451-1 [3030] L451-1-->L456-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 31115#L456-1 [2574] L456-1-->L461-1: Formula: (and (= v_~t2_st~0_2 0) (= 1 v_~t2_i~0_3)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_2} AuxVars[] AssignedVars[~t2_st~0] 31116#L461-1 [2880] L461-1-->L466-1: Formula: (and (= v_~t3_st~0_3 0) (= v_~t3_i~0_3 1)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_3, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 31029#L466-1 [2457] L466-1-->L471-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 31030#L471-1 [3209] L471-1-->L476-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 31264#L476-1 [2761] L476-1-->L481-1: Formula: (and (= 1 v_~t6_i~0_3) (= v_~t6_st~0_4 0)) InVars {~t6_i~0=v_~t6_i~0_3} OutVars{~t6_st~0=v_~t6_st~0_4, ~t6_i~0=v_~t6_i~0_3} AuxVars[] AssignedVars[~t6_st~0] 31265#L481-1 [3652] L481-1-->L660-1: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 31424#L660-1 [3654] L660-1-->L665-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 30944#L665-1 [3655] L665-1-->L670-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 30945#L670-1 [3658] L670-1-->L675-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 31036#L675-1 [3659] L675-1-->L680-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 31037#L680-1 [3661] L680-1-->L685-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 31275#L685-1 [3663] L685-1-->L690-1: Formula: (< 0 v_~T6_E~0_4) InVars {~T6_E~0=v_~T6_E~0_4} OutVars{~T6_E~0=v_~T6_E~0_4} AuxVars[] AssignedVars[] 31276#L690-1 [3665] L690-1-->L695-1: Formula: (> v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 31159#L695-1 [3668] L695-1-->L700-1: Formula: (> v_~E_2~0_6 0) InVars {~E_2~0=v_~E_2~0_6} OutVars{~E_2~0=v_~E_2~0_6} AuxVars[] AssignedVars[] 31160#L700-1 [3670] L700-1-->L705-1: Formula: (> v_~E_3~0_6 0) InVars {~E_3~0=v_~E_3~0_6} OutVars{~E_3~0=v_~E_3~0_6} AuxVars[] AssignedVars[] 31393#L705-1 [3672] L705-1-->L710-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 31097#L710-1 [3674] L710-1-->L715-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 31098#L715-1 [3675] L715-1-->L720-1: Formula: (> v_~E_6~0_4 0) InVars {~E_6~0=v_~E_6~0_4} OutVars{~E_6~0=v_~E_6~0_4} AuxVars[] AssignedVars[] 30981#L720-1 [2412] L720-1-->L310: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_7, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_4|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_4|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_7, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_4, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_4, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_2|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_2|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_4|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_4|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_7, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_2|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_4} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 30982#L310 [3678] L310-->L310-2: Formula: (< v_~m_pc~0_5 1) InVars {~m_pc~0=v_~m_pc~0_5} OutVars{~m_pc~0=v_~m_pc~0_5} AuxVars[] AssignedVars[] 31131#L310-2 [2805] L310-2-->L321: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_11 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 31126#L321 [4267] L321-->L815: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 31127#L815 [2976] L815-->L815-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_12) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} AuxVars[] AssignedVars[] 31388#L815-2 [2961] L815-2-->L329: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 31322#L329 [3683] L329-->L329-2: Formula: (< v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 31323#L329-2 [2861] L329-2-->L340: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 31318#L340 [4268] L340-->L823: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 31319#L823 [3687] L823-->L823-2: Formula: (and (> v_ULTIMATE.start_activate_threads_~tmp___0~0_11 0) (= v_~t1_st~0_5 0)) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_11} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_11, ~t1_st~0=v_~t1_st~0_5} AuxVars[] AssignedVars[~t1_st~0] 31493#L823-2 [3235] L823-2-->L348: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_4|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 31473#L348 [3690] L348-->L348-2: Formula: (< v_~t2_pc~0_5 1) InVars {~t2_pc~0=v_~t2_pc~0_5} OutVars{~t2_pc~0=v_~t2_pc~0_5} AuxVars[] AssignedVars[] 31475#L348-2 [3153] L348-2-->L359: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 31471#L359 [4269] L359-->L831: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 31104#L831 [3694] L831-->L831-2: Formula: (and (= v_~t2_st~0_5 0) (> v_ULTIMATE.start_activate_threads_~tmp___1~0_11 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_11} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_11, ~t2_st~0=v_~t2_st~0_5} AuxVars[] AssignedVars[~t2_st~0] 31092#L831-2 [2520] L831-2-->L367: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_4|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 31032#L367 [3695] L367-->L367-2: Formula: (> 1 v_~t3_pc~0_5) InVars {~t3_pc~0=v_~t3_pc~0_5} OutVars{~t3_pc~0=v_~t3_pc~0_5} AuxVars[] AssignedVars[] 31010#L367-2 [2438] L367-2-->L378: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 31011#L378 [4270] L378-->L839: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 31031#L839 [2791] L839-->L839-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} AuxVars[] AssignedVars[] 31286#L839-2 [2794] L839-2-->L386: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_7, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 31204#L386 [2675] L386-->L387: Formula: (= v_~t4_pc~0_4 1) InVars {~t4_pc~0=v_~t4_pc~0_4} OutVars{~t4_pc~0=v_~t4_pc~0_4} AuxVars[] AssignedVars[] 31120#L387 [2588] L387-->L397: Formula: (and (= v_~E_4~0_7 1) (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_10 1)) InVars {~E_4~0=v_~E_4~0_7} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_10, ~E_4~0=v_~E_4~0_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 31122#L397 [4271] L397-->L847: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 31203#L847 [3084] L847-->L847-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} AuxVars[] AssignedVars[] 31430#L847-2 [3064] L847-2-->L405: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_4|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 31431#L405 [3708] L405-->L405-2: Formula: (> 1 v_~t5_pc~0_5) InVars {~t5_pc~0=v_~t5_pc~0_5} OutVars{~t5_pc~0=v_~t5_pc~0_5} AuxVars[] AssignedVars[] 31349#L405-2 [2940] L405-2-->L416: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 31376#L416 [4272] L416-->L855: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 31440#L855 [3711] L855-->L855-2: Formula: (and (> v_ULTIMATE.start_activate_threads_~tmp___4~0_11 0) (= v_~t5_st~0_7 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_11} OutVars{~t5_st~0=v_~t5_st~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_11} AuxVars[] AssignedVars[~t5_st~0] 31441#L855-2 [3093] L855-2-->L424: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_4|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 31076#L424 [3714] L424-->L424-2: Formula: (> v_~t6_pc~0_5 1) InVars {~t6_pc~0=v_~t6_pc~0_5} OutVars{~t6_pc~0=v_~t6_pc~0_5} AuxVars[] AssignedVars[] 31077#L424-2 [2503] L424-2-->L435: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 31073#L435 [4273] L435-->L863: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___5~0_49 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_28|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_28|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 30995#L863 [2425] L863-->L863-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___5~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} AuxVars[] AssignedVars[] 30967#L863-2 [3720] L863-2-->L733-1: Formula: (< v_~M_E~0_15 1) InVars {~M_E~0=v_~M_E~0_15} OutVars{~M_E~0=v_~M_E~0_15} AuxVars[] AssignedVars[] 30968#L733-1 [3722] L733-1-->L738-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 31391#L738-1 [3723] L738-1-->L743-1: Formula: (< 1 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 31095#L743-1 [3726] L743-1-->L748-1: Formula: (< 1 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 31096#L748-1 [3728] L748-1-->L753-1: Formula: (> v_~T4_E~0_10 1) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 30975#L753-1 [3729] L753-1-->L758-1: Formula: (< 1 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 30976#L758-1 [3732] L758-1-->L763-1: Formula: (< v_~T6_E~0_10 1) InVars {~T6_E~0=v_~T6_E~0_10} OutVars{~T6_E~0=v_~T6_E~0_10} AuxVars[] AssignedVars[] 31048#L763-1 [3733] L763-1-->L768-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 31049#L768-1 [3736] L768-1-->L773-1: Formula: (< 1 v_~E_2~0_14) InVars {~E_2~0=v_~E_2~0_14} OutVars{~E_2~0=v_~E_2~0_14} AuxVars[] AssignedVars[] 31268#L773-1 [3737] L773-1-->L778-1: Formula: (< 1 v_~E_3~0_14) InVars {~E_3~0=v_~E_3~0_14} OutVars{~E_3~0=v_~E_3~0_14} AuxVars[] AssignedVars[] 31269#L778-1 [3740] L778-1-->L783-1: Formula: (< 1 v_~E_4~0_14) InVars {~E_4~0=v_~E_4~0_14} OutVars{~E_4~0=v_~E_4~0_14} AuxVars[] AssignedVars[] 31150#L783-1 [3741] L783-1-->L788-1: Formula: (< 1 v_~E_5~0_14) InVars {~E_5~0=v_~E_5~0_14} OutVars{~E_5~0=v_~E_5~0_14} AuxVars[] AssignedVars[] 31151#L788-1 [3744] L788-1-->L1014-1: Formula: (< 1 v_~E_6~0_14) InVars {~E_6~0=v_~E_6~0_14} OutVars{~E_6~0=v_~E_6~0_14} AuxVars[] AssignedVars[] 30989#L1014-1 [2020-06-22 00:13:17,246 INFO L796 eck$LassoCheckResult]: Loop: 30989#L1014-1 [4274] L1014-1-->L635: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp_ndt_7~0=v_ULTIMATE.start_eval_~tmp_ndt_7~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp_ndt_7~0] 30950#L635 [4275] L635-->L494: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_37} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 31345#L494 [2876] L494-->L531: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21 1) (= v_~m_st~0_8 0)) InVars {~m_st~0=v_~m_st~0_8} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21, ~m_st~0=v_~m_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 31020#L531 [4276] L531-->L546: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 31256#L546 [4278] L546-->L660-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 31425#L660-2 [3747] L660-2-->L660-4: Formula: (> v_~M_E~0_30 0) InVars {~M_E~0=v_~M_E~0_30} OutVars{~M_E~0=v_~M_E~0_30} AuxVars[] AssignedVars[] 31426#L660-4 [3058] L660-4-->L665-3: Formula: (and (= v_~T1_E~0_11 1) (= v_~T1_E~0_12 0)) InVars {~T1_E~0=v_~T1_E~0_12} OutVars{~T1_E~0=v_~T1_E~0_11} AuxVars[] AssignedVars[~T1_E~0] 30960#L665-3 [3756] L665-3-->L670-3: Formula: (< 0 v_~T2_E~0_13) InVars {~T2_E~0=v_~T2_E~0_13} OutVars{~T2_E~0=v_~T2_E~0_13} AuxVars[] AssignedVars[] 30961#L670-3 [3762] L670-3-->L675-3: Formula: (< 0 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 31038#L675-3 [3768] L675-3-->L680-3: Formula: (> v_~T4_E~0_13 0) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 31039#L680-3 [3776] L680-3-->L685-3: Formula: (< 0 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 32611#L685-3 [3785] L685-3-->L690-3: Formula: (> v_~T6_E~0_13 0) InVars {~T6_E~0=v_~T6_E~0_13} OutVars{~T6_E~0=v_~T6_E~0_13} AuxVars[] AssignedVars[] 32610#L690-3 [3795] L690-3-->L695-3: Formula: (< 0 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 32609#L695-3 [3805] L695-3-->L700-3: Formula: (< 0 v_~E_2~0_31) InVars {~E_2~0=v_~E_2~0_31} OutVars{~E_2~0=v_~E_2~0_31} AuxVars[] AssignedVars[] 32608#L700-3 [3818] L700-3-->L705-3: Formula: (< 0 v_~E_3~0_31) InVars {~E_3~0=v_~E_3~0_31} OutVars{~E_3~0=v_~E_3~0_31} AuxVars[] AssignedVars[] 32607#L705-3 [2688] L705-3-->L710-3: Formula: (and (= v_~E_4~0_29 1) (= 0 v_~E_4~0_30)) InVars {~E_4~0=v_~E_4~0_30} OutVars{~E_4~0=v_~E_4~0_29} AuxVars[] AssignedVars[~E_4~0] 32606#L710-3 [3844] L710-3-->L715-3: Formula: (< 0 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 32605#L715-3 [3854] L715-3-->L720-3: Formula: (< 0 v_~E_6~0_31) InVars {~E_6~0=v_~E_6~0_31} OutVars{~E_6~0=v_~E_6~0_31} AuxVars[] AssignedVars[] 32603#L720-3 [2388] L720-3-->L310-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_43, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_43, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_25|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_25|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_25|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_43, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_43, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_43, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_25|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_25|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_25|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_25|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_43, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_25|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_43, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_43} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 31277#L310-21 [3870] L310-21-->L310-23: Formula: (< v_~m_pc~0_24 1) InVars {~m_pc~0=v_~m_pc~0_24} OutVars{~m_pc~0=v_~m_pc~0_24} AuxVars[] AssignedVars[] 31278#L310-23 [2785] L310-23-->L321-7: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_47 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_47} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 32177#L321-7 [4303] L321-7-->L815-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 32175#L815-21 [2667] L815-21-->L815-23: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_48) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_48} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_48} AuxVars[] AssignedVars[] 32172#L815-23 [2638] L815-23-->L329-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 31419#L329-21 [3911] L329-21-->L329-23: Formula: (< v_~t1_pc~0_24 1) InVars {~t1_pc~0=v_~t1_pc~0_24} OutVars{~t1_pc~0=v_~t1_pc~0_24} AuxVars[] AssignedVars[] 31420#L329-23 [3052] L329-23-->L340-7: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 31311#L340-7 [4310] L340-7-->L823-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 31312#L823-21 [2931] L823-21-->L823-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} AuxVars[] AssignedVars[] 31369#L823-23 [2934] L823-23-->L348-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_25|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 31371#L348-21 [3953] L348-21-->L348-23: Formula: (> 1 v_~t2_pc~0_24) InVars {~t2_pc~0=v_~t2_pc~0_24} OutVars{~t2_pc~0=v_~t2_pc~0_24} AuxVars[] AssignedVars[] 31499#L348-23 [3319] L348-23-->L359-7: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 31467#L359-7 [4317] L359-7-->L831-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 31067#L831-21 [2490] L831-21-->L831-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} AuxVars[] AssignedVars[] 31068#L831-23 [3197] L831-23-->L367-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_25|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 30977#L367-21 [3995] L367-21-->L367-23: Formula: (> v_~t3_pc~0_24 1) InVars {~t3_pc~0=v_~t3_pc~0_24} OutVars{~t3_pc~0=v_~t3_pc~0_24} AuxVars[] AssignedVars[] 30979#L367-23 [2385] L367-23-->L378-7: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 32536#L378-7 [4324] L378-7-->L839-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 32535#L839-21 [4023] L839-21-->L839-23: Formula: (and (= v_~t3_st~0_21 0) (> v_ULTIMATE.start_activate_threads_~tmp___2~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} OutVars{~t3_st~0=v_~t3_st~0_21, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} AuxVars[] AssignedVars[~t3_st~0] 32534#L839-23 [2722] L839-23-->L386-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_49, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 32533#L386-21 [2617] L386-21-->L387-7: Formula: (= 1 v_~t4_pc~0_23) InVars {~t4_pc~0=v_~t4_pc~0_23} OutVars{~t4_pc~0=v_~t4_pc~0_23} AuxVars[] AssignedVars[] 32494#L387-7 [2818] L387-7-->L397-7: Formula: (and (= 1 v_~E_4~0_32) (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_52 1)) InVars {~E_4~0=v_~E_4~0_32} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_52, ~E_4~0=v_~E_4~0_32} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 32493#L397-7 [4331] L397-7-->L847-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 32492#L847-21 [4065] L847-21-->L847-23: Formula: (and (= v_~t4_st~0_22 0) (< v_ULTIMATE.start_activate_threads_~tmp___3~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47, ~t4_st~0=v_~t4_st~0_22} AuxVars[] AssignedVars[~t4_st~0] 32491#L847-23 [2983] L847-23-->L405-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_25|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 32489#L405-21 [4080] L405-21-->L405-23: Formula: (> v_~t5_pc~0_24 1) InVars {~t5_pc~0=v_~t5_pc~0_24} OutVars{~t5_pc~0=v_~t5_pc~0_24} AuxVars[] AssignedVars[] 32487#L405-23 [2891] L405-23-->L416-7: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 32486#L416-7 [4338] L416-7-->L855-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 32485#L855-21 [3251] L855-21-->L855-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} AuxVars[] AssignedVars[] 32484#L855-23 [3257] L855-23-->L424-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_25|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 32482#L424-21 [4121] L424-21-->L424-23: Formula: (< 1 v_~t6_pc~0_24) InVars {~t6_pc~0=v_~t6_pc~0_24} OutVars{~t6_pc~0=v_~t6_pc~0_24} AuxVars[] AssignedVars[] 31480#L424-23 [3177] L424-23-->L435-7: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 31062#L435-7 [4340] L435-7-->L863-21: Formula: (and (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___5~0_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_35|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_41|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 31063#L863-21 [4135] L863-21-->L863-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___5~0_47 0) (= v_~t6_st~0_22 0)) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} OutVars{~t6_st~0=v_~t6_st~0_22, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} AuxVars[] AssignedVars[~t6_st~0] 32373#L863-23 [4137] L863-23-->L733-3: Formula: (< v_~M_E~0_35 1) InVars {~M_E~0=v_~M_E~0_35} OutVars{~M_E~0=v_~M_E~0_35} AuxVars[] AssignedVars[] 32372#L733-3 [3184] L733-3-->L738-3: Formula: (and (= v_~T1_E~0_15 1) (= v_~T1_E~0_14 2)) InVars {~T1_E~0=v_~T1_E~0_15} OutVars{~T1_E~0=v_~T1_E~0_14} AuxVars[] AssignedVars[~T1_E~0] 32371#L738-3 [4142] L738-3-->L743-3: Formula: (< 1 v_~T2_E~0_16) InVars {~T2_E~0=v_~T2_E~0_16} OutVars{~T2_E~0=v_~T2_E~0_16} AuxVars[] AssignedVars[] 32370#L743-3 [4143] L743-3-->L748-3: Formula: (< 1 v_~T3_E~0_16) InVars {~T3_E~0=v_~T3_E~0_16} OutVars{~T3_E~0=v_~T3_E~0_16} AuxVars[] AssignedVars[] 31422#L748-3 [4145] L748-3-->L753-3: Formula: (> v_~T4_E~0_16 1) InVars {~T4_E~0=v_~T4_E~0_16} OutVars{~T4_E~0=v_~T4_E~0_16} AuxVars[] AssignedVars[] 30942#L753-3 [4148] L753-3-->L758-3: Formula: (< 1 v_~T5_E~0_16) InVars {~T5_E~0=v_~T5_E~0_16} OutVars{~T5_E~0=v_~T5_E~0_16} AuxVars[] AssignedVars[] 30943#L758-3 [4149] L758-3-->L763-3: Formula: (> v_~T6_E~0_16 1) InVars {~T6_E~0=v_~T6_E~0_16} OutVars{~T6_E~0=v_~T6_E~0_16} AuxVars[] AssignedVars[] 31034#L763-3 [4151] L763-3-->L768-3: Formula: (< 1 v_~E_1~0_36) InVars {~E_1~0=v_~E_1~0_36} OutVars{~E_1~0=v_~E_1~0_36} AuxVars[] AssignedVars[] 31035#L768-3 [4154] L768-3-->L773-3: Formula: (< 1 v_~E_2~0_36) InVars {~E_2~0=v_~E_2~0_36} OutVars{~E_2~0=v_~E_2~0_36} AuxVars[] AssignedVars[] 31273#L773-3 [4156] L773-3-->L778-3: Formula: (< 1 v_~E_3~0_36) InVars {~E_3~0=v_~E_3~0_36} OutVars{~E_3~0=v_~E_3~0_36} AuxVars[] AssignedVars[] 31274#L778-3 [3308] L778-3-->L783-3: Formula: (and (= 1 v_~E_4~0_35) (= v_~E_4~0_34 2)) InVars {~E_4~0=v_~E_4~0_35} OutVars{~E_4~0=v_~E_4~0_34} AuxVars[] AssignedVars[~E_4~0] 31157#L783-3 [4160] L783-3-->L788-3: Formula: (< 1 v_~E_5~0_36) InVars {~E_5~0=v_~E_5~0_36} OutVars{~E_5~0=v_~E_5~0_36} AuxVars[] AssignedVars[] 31158#L788-3 [4162] L788-3-->L793-3: Formula: (< 1 v_~E_6~0_36) InVars {~E_6~0=v_~E_6~0_36} OutVars{~E_6~0=v_~E_6~0_36} AuxVars[] AssignedVars[] 31392#L793-3 [2966] L793-3-->L494-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_30} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 31346#L494-1 [2878] L494-1-->L531-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33 1) (= 0 v_~m_st~0_21)) InVars {~m_st~0=v_~m_st~0_21} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33, ~m_st~0=v_~m_st~0_21} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 31022#L531-1 [4341] L531-1-->L1033: Formula: (and (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp~3] 31259#L1033 [4169] L1033-->L1033-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_6) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} AuxVars[] AssignedVars[] 31358#L1033-1 [2919] L1033-1-->L494-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_3|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_6, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_exists_runnable_thread_~__retres1~7, ULTIMATE.start_stop_simulation_#res] 32394#L494-2 [2882] L494-2-->L531-2: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9 1) (= v_~m_st~0_6 0)) InVars {~m_st~0=v_~m_st~0_6} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9, ~m_st~0=v_~m_st~0_6} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 32392#L531-2 [4343] L531-2-->L988: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 32391#L988 [3240] L988-->L995: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 30988#L995 [4354] L995-->L1014-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_6|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_#t~ret17, ULTIMATE.start_stop_simulation_#res] 30989#L1014-1 [2020-06-22 00:13:17,246 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:17,247 INFO L82 PathProgramCache]: Analyzing trace with hash 1853721880, now seen corresponding path program 1 times [2020-06-22 00:13:17,247 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:17,247 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:17,248 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:17,248 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:17,248 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:17,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:17,286 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:17,287 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:17,287 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2020-06-22 00:13:17,287 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-06-22 00:13:17,287 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:17,287 INFO L82 PathProgramCache]: Analyzing trace with hash 2072517841, now seen corresponding path program 2 times [2020-06-22 00:13:17,288 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:17,288 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:17,288 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:17,288 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:17,289 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:17,291 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:17,323 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:17,323 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:17,324 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2020-06-22 00:13:17,324 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-06-22 00:13:17,324 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2020-06-22 00:13:17,324 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2020-06-22 00:13:17,325 INFO L87 Difference]: Start difference. First operand 1676 states and 2995 transitions. cyclomatic complexity: 1320 Second operand 6 states. [2020-06-22 00:13:19,365 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-06-22 00:13:19,365 INFO L93 Difference]: Finished difference Result 3867 states and 7027 transitions. [2020-06-22 00:13:19,365 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2020-06-22 00:13:19,366 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3867 states and 7027 transitions. [2020-06-22 00:13:19,379 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3793 [2020-06-22 00:13:19,397 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3867 states to 3867 states and 7027 transitions. [2020-06-22 00:13:19,397 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3867 [2020-06-22 00:13:19,399 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3867 [2020-06-22 00:13:19,399 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3867 states and 7027 transitions. [2020-06-22 00:13:19,403 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-06-22 00:13:19,403 INFO L706 BuchiCegarLoop]: Abstraction has 3867 states and 7027 transitions. [2020-06-22 00:13:19,405 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3867 states and 7027 transitions. [2020-06-22 00:13:19,430 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3867 to 1678. [2020-06-22 00:13:19,430 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1678 states. [2020-06-22 00:13:19,433 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1678 states to 1678 states and 2969 transitions. [2020-06-22 00:13:19,433 INFO L729 BuchiCegarLoop]: Abstraction has 1678 states and 2969 transitions. [2020-06-22 00:13:19,433 INFO L609 BuchiCegarLoop]: Abstraction has 1678 states and 2969 transitions. [2020-06-22 00:13:19,434 INFO L442 BuchiCegarLoop]: ======== Iteration 25============ [2020-06-22 00:13:19,434 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1678 states and 2969 transitions. [2020-06-22 00:13:19,438 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1604 [2020-06-22 00:13:19,438 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-06-22 00:13:19,438 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-06-22 00:13:19,439 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:19,439 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:19,440 INFO L794 eck$LassoCheckResult]: Stem: 36992#ULTIMATE.startENTRY [4266] ULTIMATE.startENTRY-->L444: Formula: (and (= 1 v_~t6_i~0_7) (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~M_E~0_37 2) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 0 v_~t6_pc~0_26) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_6~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= v_~T6_E~0_18 2) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~t6_st~0_24) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t6_pc~0=v_~t6_pc~0_26, ~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~T6_E~0=v_~T6_E~0_18, ~M_E~0=v_~M_E~0_37, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ~T4_E~0=v_~T4_E~0_18, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_4|, ~t6_i~0=v_~t6_i~0_7, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ULTIMATE.start_main_~__retres1~8=v_ULTIMATE.start_main_~__retres1~8_6, ~T2_E~0=v_~T2_E~0_18, ~t6_st~0=v_~t6_st~0_24, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_6~0=v_~E_6~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t6_pc~0, ~t5_i~0, ~t1_pc~0, ~t5_st~0, ~T6_E~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ~T4_E~0, ULTIMATE.start_start_simulation_#t~ret17, ~t6_i~0, ~t2_st~0, ~t2_pc~0, ULTIMATE.start_main_~__retres1~8, ~T2_E~0, ~t6_st~0, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_6~0, ULTIMATE.start_main_#res, ~E_2~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 36601#L444 [2453] L444-->L451-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 36602#L451-1 [3030] L451-1-->L456-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 36689#L456-1 [2574] L456-1-->L461-1: Formula: (and (= v_~t2_st~0_2 0) (= 1 v_~t2_i~0_3)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_2} AuxVars[] AssignedVars[~t2_st~0] 36690#L461-1 [2880] L461-1-->L466-1: Formula: (and (= v_~t3_st~0_3 0) (= v_~t3_i~0_3 1)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_3, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 36603#L466-1 [2457] L466-1-->L471-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 36604#L471-1 [3209] L471-1-->L476-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 36838#L476-1 [2761] L476-1-->L481-1: Formula: (and (= 1 v_~t6_i~0_3) (= v_~t6_st~0_4 0)) InVars {~t6_i~0=v_~t6_i~0_3} OutVars{~t6_st~0=v_~t6_st~0_4, ~t6_i~0=v_~t6_i~0_3} AuxVars[] AssignedVars[~t6_st~0] 36839#L481-1 [3652] L481-1-->L660-1: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 37006#L660-1 [3654] L660-1-->L665-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 36519#L665-1 [3655] L665-1-->L670-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 36520#L670-1 [3658] L670-1-->L675-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 36610#L675-1 [3659] L675-1-->L680-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 36611#L680-1 [3661] L680-1-->L685-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 36850#L685-1 [3663] L685-1-->L690-1: Formula: (< 0 v_~T6_E~0_4) InVars {~T6_E~0=v_~T6_E~0_4} OutVars{~T6_E~0=v_~T6_E~0_4} AuxVars[] AssignedVars[] 36851#L690-1 [3665] L690-1-->L695-1: Formula: (> v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 36733#L695-1 [3668] L695-1-->L700-1: Formula: (> v_~E_2~0_6 0) InVars {~E_2~0=v_~E_2~0_6} OutVars{~E_2~0=v_~E_2~0_6} AuxVars[] AssignedVars[] 36734#L700-1 [3670] L700-1-->L705-1: Formula: (> v_~E_3~0_6 0) InVars {~E_3~0=v_~E_3~0_6} OutVars{~E_3~0=v_~E_3~0_6} AuxVars[] AssignedVars[] 36976#L705-1 [3672] L705-1-->L710-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 36672#L710-1 [3674] L710-1-->L715-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 36673#L715-1 [3675] L715-1-->L720-1: Formula: (> v_~E_6~0_4 0) InVars {~E_6~0=v_~E_6~0_4} OutVars{~E_6~0=v_~E_6~0_4} AuxVars[] AssignedVars[] 36554#L720-1 [2412] L720-1-->L310: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_7, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_4|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_4|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_7, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_4, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_4, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_2|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_2|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_4|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_4|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_7, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_2|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_4} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 36555#L310 [3678] L310-->L310-2: Formula: (< v_~m_pc~0_5 1) InVars {~m_pc~0=v_~m_pc~0_5} OutVars{~m_pc~0=v_~m_pc~0_5} AuxVars[] AssignedVars[] 36705#L310-2 [2805] L310-2-->L321: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_11 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 36703#L321 [4267] L321-->L815: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 36704#L815 [2976] L815-->L815-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_12) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} AuxVars[] AssignedVars[] 36971#L815-2 [2961] L815-2-->L329: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 36902#L329 [3683] L329-->L329-2: Formula: (< v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 36903#L329-2 [2861] L329-2-->L340: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 36900#L340 [4268] L340-->L823: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 36901#L823 [3234] L823-->L823-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} AuxVars[] AssignedVars[] 37075#L823-2 [3235] L823-2-->L348: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_4|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 37055#L348 [3690] L348-->L348-2: Formula: (< v_~t2_pc~0_5 1) InVars {~t2_pc~0=v_~t2_pc~0_5} OutVars{~t2_pc~0=v_~t2_pc~0_5} AuxVars[] AssignedVars[] 37057#L348-2 [3153] L348-2-->L359: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 37054#L359 [4269] L359-->L831: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 36679#L831 [3694] L831-->L831-2: Formula: (and (= v_~t2_st~0_5 0) (> v_ULTIMATE.start_activate_threads_~tmp___1~0_11 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_11} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_11, ~t2_st~0=v_~t2_st~0_5} AuxVars[] AssignedVars[~t2_st~0] 36667#L831-2 [2520] L831-2-->L367: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_4|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 36606#L367 [3695] L367-->L367-2: Formula: (> 1 v_~t3_pc~0_5) InVars {~t3_pc~0=v_~t3_pc~0_5} OutVars{~t3_pc~0=v_~t3_pc~0_5} AuxVars[] AssignedVars[] 36584#L367-2 [2438] L367-2-->L378: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 36585#L378 [4270] L378-->L839: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 36605#L839 [2791] L839-->L839-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} AuxVars[] AssignedVars[] 36863#L839-2 [2794] L839-2-->L386: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_7, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 36777#L386 [2675] L386-->L387: Formula: (= v_~t4_pc~0_4 1) InVars {~t4_pc~0=v_~t4_pc~0_4} OutVars{~t4_pc~0=v_~t4_pc~0_4} AuxVars[] AssignedVars[] 36694#L387 [2588] L387-->L397: Formula: (and (= v_~E_4~0_7 1) (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_10 1)) InVars {~E_4~0=v_~E_4~0_7} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_10, ~E_4~0=v_~E_4~0_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 36696#L397 [4271] L397-->L847: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 36776#L847 [3084] L847-->L847-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} AuxVars[] AssignedVars[] 37013#L847-2 [3064] L847-2-->L405: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_4|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 37014#L405 [3708] L405-->L405-2: Formula: (> 1 v_~t5_pc~0_5) InVars {~t5_pc~0=v_~t5_pc~0_5} OutVars{~t5_pc~0=v_~t5_pc~0_5} AuxVars[] AssignedVars[] 36930#L405-2 [2940] L405-2-->L416: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 36961#L416 [4272] L416-->L855: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 37023#L855 [3711] L855-->L855-2: Formula: (and (> v_ULTIMATE.start_activate_threads_~tmp___4~0_11 0) (= v_~t5_st~0_7 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_11} OutVars{~t5_st~0=v_~t5_st~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_11} AuxVars[] AssignedVars[~t5_st~0] 37024#L855-2 [3093] L855-2-->L424: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_4|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 36651#L424 [3714] L424-->L424-2: Formula: (> v_~t6_pc~0_5 1) InVars {~t6_pc~0=v_~t6_pc~0_5} OutVars{~t6_pc~0=v_~t6_pc~0_5} AuxVars[] AssignedVars[] 36652#L424-2 [2503] L424-2-->L435: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 36650#L435 [4273] L435-->L863: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___5~0_49 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_28|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_28|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 36570#L863 [2425] L863-->L863-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___5~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} AuxVars[] AssignedVars[] 36543#L863-2 [3720] L863-2-->L733-1: Formula: (< v_~M_E~0_15 1) InVars {~M_E~0=v_~M_E~0_15} OutVars{~M_E~0=v_~M_E~0_15} AuxVars[] AssignedVars[] 36544#L733-1 [3722] L733-1-->L738-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 36974#L738-1 [3723] L738-1-->L743-1: Formula: (< 1 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 36670#L743-1 [3726] L743-1-->L748-1: Formula: (< 1 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 36671#L748-1 [3728] L748-1-->L753-1: Formula: (> v_~T4_E~0_10 1) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 36549#L753-1 [3729] L753-1-->L758-1: Formula: (< 1 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 36550#L758-1 [3732] L758-1-->L763-1: Formula: (< v_~T6_E~0_10 1) InVars {~T6_E~0=v_~T6_E~0_10} OutVars{~T6_E~0=v_~T6_E~0_10} AuxVars[] AssignedVars[] 36622#L763-1 [3733] L763-1-->L768-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 36623#L768-1 [3736] L768-1-->L773-1: Formula: (< 1 v_~E_2~0_14) InVars {~E_2~0=v_~E_2~0_14} OutVars{~E_2~0=v_~E_2~0_14} AuxVars[] AssignedVars[] 36845#L773-1 [3737] L773-1-->L778-1: Formula: (< 1 v_~E_3~0_14) InVars {~E_3~0=v_~E_3~0_14} OutVars{~E_3~0=v_~E_3~0_14} AuxVars[] AssignedVars[] 36846#L778-1 [3740] L778-1-->L783-1: Formula: (< 1 v_~E_4~0_14) InVars {~E_4~0=v_~E_4~0_14} OutVars{~E_4~0=v_~E_4~0_14} AuxVars[] AssignedVars[] 36726#L783-1 [3741] L783-1-->L788-1: Formula: (< 1 v_~E_5~0_14) InVars {~E_5~0=v_~E_5~0_14} OutVars{~E_5~0=v_~E_5~0_14} AuxVars[] AssignedVars[] 36727#L788-1 [3744] L788-1-->L1014-1: Formula: (< 1 v_~E_6~0_14) InVars {~E_6~0=v_~E_6~0_14} OutVars{~E_6~0=v_~E_6~0_14} AuxVars[] AssignedVars[] 37063#L1014-1 [2020-06-22 00:13:19,441 INFO L796 eck$LassoCheckResult]: Loop: 37063#L1014-1 [4274] L1014-1-->L635: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp_ndt_7~0=v_ULTIMATE.start_eval_~tmp_ndt_7~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp_ndt_7~0] 37355#L635 [4275] L635-->L494: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_37} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 37266#L494 [2876] L494-->L531: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21 1) (= v_~m_st~0_8 0)) InVars {~m_st~0=v_~m_st~0_8} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21, ~m_st~0=v_~m_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 37254#L531 [4276] L531-->L546: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 37246#L546 [4278] L546-->L660-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 37247#L660-2 [3747] L660-2-->L660-4: Formula: (> v_~M_E~0_30 0) InVars {~M_E~0=v_~M_E~0_30} OutVars{~M_E~0=v_~M_E~0_30} AuxVars[] AssignedVars[] 37756#L660-4 [3058] L660-4-->L665-3: Formula: (and (= v_~T1_E~0_11 1) (= v_~T1_E~0_12 0)) InVars {~T1_E~0=v_~T1_E~0_12} OutVars{~T1_E~0=v_~T1_E~0_11} AuxVars[] AssignedVars[~T1_E~0] 37755#L665-3 [3756] L665-3-->L670-3: Formula: (< 0 v_~T2_E~0_13) InVars {~T2_E~0=v_~T2_E~0_13} OutVars{~T2_E~0=v_~T2_E~0_13} AuxVars[] AssignedVars[] 37754#L670-3 [3762] L670-3-->L675-3: Formula: (< 0 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 37753#L675-3 [3768] L675-3-->L680-3: Formula: (> v_~T4_E~0_13 0) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 37752#L680-3 [3776] L680-3-->L685-3: Formula: (< 0 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 37751#L685-3 [3785] L685-3-->L690-3: Formula: (> v_~T6_E~0_13 0) InVars {~T6_E~0=v_~T6_E~0_13} OutVars{~T6_E~0=v_~T6_E~0_13} AuxVars[] AssignedVars[] 37750#L690-3 [3795] L690-3-->L695-3: Formula: (< 0 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 37749#L695-3 [3805] L695-3-->L700-3: Formula: (< 0 v_~E_2~0_31) InVars {~E_2~0=v_~E_2~0_31} OutVars{~E_2~0=v_~E_2~0_31} AuxVars[] AssignedVars[] 37748#L700-3 [3818] L700-3-->L705-3: Formula: (< 0 v_~E_3~0_31) InVars {~E_3~0=v_~E_3~0_31} OutVars{~E_3~0=v_~E_3~0_31} AuxVars[] AssignedVars[] 37747#L705-3 [2688] L705-3-->L710-3: Formula: (and (= v_~E_4~0_29 1) (= 0 v_~E_4~0_30)) InVars {~E_4~0=v_~E_4~0_30} OutVars{~E_4~0=v_~E_4~0_29} AuxVars[] AssignedVars[~E_4~0] 37746#L710-3 [3844] L710-3-->L715-3: Formula: (< 0 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 37745#L715-3 [3854] L715-3-->L720-3: Formula: (< 0 v_~E_6~0_31) InVars {~E_6~0=v_~E_6~0_31} OutVars{~E_6~0=v_~E_6~0_31} AuxVars[] AssignedVars[] 37743#L720-3 [2388] L720-3-->L310-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_43, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_43, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_25|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_25|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_25|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_43, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_43, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_43, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_25|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_25|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_25|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_25|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_43, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_25|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_43, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_43} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 36852#L310-21 [3870] L310-21-->L310-23: Formula: (< v_~m_pc~0_24 1) InVars {~m_pc~0=v_~m_pc~0_24} OutVars{~m_pc~0=v_~m_pc~0_24} AuxVars[] AssignedVars[] 36853#L310-23 [2785] L310-23-->L321-7: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_47 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_47} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 38062#L321-7 [4303] L321-7-->L815-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 38061#L815-21 [2667] L815-21-->L815-23: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_48) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_48} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_48} AuxVars[] AssignedVars[] 36748#L815-23 [2638] L815-23-->L329-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 36749#L329-21 [3911] L329-21-->L329-23: Formula: (< v_~t1_pc~0_24 1) InVars {~t1_pc~0=v_~t1_pc~0_24} OutVars{~t1_pc~0=v_~t1_pc~0_24} AuxVars[] AssignedVars[] 37004#L329-23 [3052] L329-23-->L340-7: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 38164#L340-7 [4310] L340-7-->L823-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 38163#L823-21 [2931] L823-21-->L823-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} AuxVars[] AssignedVars[] 38162#L823-23 [2934] L823-23-->L348-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_25|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 38160#L348-21 [3953] L348-21-->L348-23: Formula: (> 1 v_~t2_pc~0_24) InVars {~t2_pc~0=v_~t2_pc~0_24} OutVars{~t2_pc~0=v_~t2_pc~0_24} AuxVars[] AssignedVars[] 38159#L348-23 [3319] L348-23-->L359-7: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 38158#L359-7 [4317] L359-7-->L831-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 38157#L831-21 [2490] L831-21-->L831-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} AuxVars[] AssignedVars[] 38156#L831-23 [3197] L831-23-->L367-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_25|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 38155#L367-21 [3995] L367-21-->L367-23: Formula: (> v_~t3_pc~0_24 1) InVars {~t3_pc~0=v_~t3_pc~0_24} OutVars{~t3_pc~0=v_~t3_pc~0_24} AuxVars[] AssignedVars[] 38153#L367-23 [2385] L367-23-->L378-7: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 38152#L378-7 [4324] L378-7-->L839-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 38151#L839-21 [4023] L839-21-->L839-23: Formula: (and (= v_~t3_st~0_21 0) (> v_ULTIMATE.start_activate_threads_~tmp___2~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} OutVars{~t3_st~0=v_~t3_st~0_21, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} AuxVars[] AssignedVars[~t3_st~0] 38150#L839-23 [2722] L839-23-->L386-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_49, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 38149#L386-21 [2617] L386-21-->L387-7: Formula: (= 1 v_~t4_pc~0_23) InVars {~t4_pc~0=v_~t4_pc~0_23} OutVars{~t4_pc~0=v_~t4_pc~0_23} AuxVars[] AssignedVars[] 38147#L387-7 [2818] L387-7-->L397-7: Formula: (and (= 1 v_~E_4~0_32) (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_52 1)) InVars {~E_4~0=v_~E_4~0_32} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_52, ~E_4~0=v_~E_4~0_32} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 38146#L397-7 [4331] L397-7-->L847-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 38145#L847-21 [4065] L847-21-->L847-23: Formula: (and (= v_~t4_st~0_22 0) (< v_ULTIMATE.start_activate_threads_~tmp___3~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47, ~t4_st~0=v_~t4_st~0_22} AuxVars[] AssignedVars[~t4_st~0] 38144#L847-23 [2983] L847-23-->L405-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_25|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 38142#L405-21 [4080] L405-21-->L405-23: Formula: (> v_~t5_pc~0_24 1) InVars {~t5_pc~0=v_~t5_pc~0_24} OutVars{~t5_pc~0=v_~t5_pc~0_24} AuxVars[] AssignedVars[] 38141#L405-23 [2891] L405-23-->L416-7: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 38140#L416-7 [4338] L416-7-->L855-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 38139#L855-21 [3251] L855-21-->L855-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} AuxVars[] AssignedVars[] 38138#L855-23 [3257] L855-23-->L424-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_25|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 38136#L424-21 [4121] L424-21-->L424-23: Formula: (< 1 v_~t6_pc~0_24) InVars {~t6_pc~0=v_~t6_pc~0_24} OutVars{~t6_pc~0=v_~t6_pc~0_24} AuxVars[] AssignedVars[] 38135#L424-23 [3177] L424-23-->L435-7: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 38134#L435-7 [4340] L435-7-->L863-21: Formula: (and (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___5~0_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_35|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_41|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 38133#L863-21 [4135] L863-21-->L863-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___5~0_47 0) (= v_~t6_st~0_22 0)) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} OutVars{~t6_st~0=v_~t6_st~0_22, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} AuxVars[] AssignedVars[~t6_st~0] 38132#L863-23 [4137] L863-23-->L733-3: Formula: (< v_~M_E~0_35 1) InVars {~M_E~0=v_~M_E~0_35} OutVars{~M_E~0=v_~M_E~0_35} AuxVars[] AssignedVars[] 38131#L733-3 [3184] L733-3-->L738-3: Formula: (and (= v_~T1_E~0_15 1) (= v_~T1_E~0_14 2)) InVars {~T1_E~0=v_~T1_E~0_15} OutVars{~T1_E~0=v_~T1_E~0_14} AuxVars[] AssignedVars[~T1_E~0] 38130#L738-3 [4142] L738-3-->L743-3: Formula: (< 1 v_~T2_E~0_16) InVars {~T2_E~0=v_~T2_E~0_16} OutVars{~T2_E~0=v_~T2_E~0_16} AuxVars[] AssignedVars[] 38129#L743-3 [4143] L743-3-->L748-3: Formula: (< 1 v_~T3_E~0_16) InVars {~T3_E~0=v_~T3_E~0_16} OutVars{~T3_E~0=v_~T3_E~0_16} AuxVars[] AssignedVars[] 38128#L748-3 [4145] L748-3-->L753-3: Formula: (> v_~T4_E~0_16 1) InVars {~T4_E~0=v_~T4_E~0_16} OutVars{~T4_E~0=v_~T4_E~0_16} AuxVars[] AssignedVars[] 38127#L753-3 [4148] L753-3-->L758-3: Formula: (< 1 v_~T5_E~0_16) InVars {~T5_E~0=v_~T5_E~0_16} OutVars{~T5_E~0=v_~T5_E~0_16} AuxVars[] AssignedVars[] 38126#L758-3 [4149] L758-3-->L763-3: Formula: (> v_~T6_E~0_16 1) InVars {~T6_E~0=v_~T6_E~0_16} OutVars{~T6_E~0=v_~T6_E~0_16} AuxVars[] AssignedVars[] 38125#L763-3 [4151] L763-3-->L768-3: Formula: (< 1 v_~E_1~0_36) InVars {~E_1~0=v_~E_1~0_36} OutVars{~E_1~0=v_~E_1~0_36} AuxVars[] AssignedVars[] 38124#L768-3 [4154] L768-3-->L773-3: Formula: (< 1 v_~E_2~0_36) InVars {~E_2~0=v_~E_2~0_36} OutVars{~E_2~0=v_~E_2~0_36} AuxVars[] AssignedVars[] 38123#L773-3 [4156] L773-3-->L778-3: Formula: (< 1 v_~E_3~0_36) InVars {~E_3~0=v_~E_3~0_36} OutVars{~E_3~0=v_~E_3~0_36} AuxVars[] AssignedVars[] 38122#L778-3 [3308] L778-3-->L783-3: Formula: (and (= 1 v_~E_4~0_35) (= v_~E_4~0_34 2)) InVars {~E_4~0=v_~E_4~0_35} OutVars{~E_4~0=v_~E_4~0_34} AuxVars[] AssignedVars[~E_4~0] 36731#L783-3 [4160] L783-3-->L788-3: Formula: (< 1 v_~E_5~0_36) InVars {~E_5~0=v_~E_5~0_36} OutVars{~E_5~0=v_~E_5~0_36} AuxVars[] AssignedVars[] 36732#L788-3 [4162] L788-3-->L793-3: Formula: (< 1 v_~E_6~0_36) InVars {~E_6~0=v_~E_6~0_36} OutVars{~E_6~0=v_~E_6~0_36} AuxVars[] AssignedVars[] 36975#L793-3 [2966] L793-3-->L494-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_30} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 36927#L494-1 [2878] L494-1-->L531-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33 1) (= 0 v_~m_st~0_21)) InVars {~m_st~0=v_~m_st~0_21} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33, ~m_st~0=v_~m_st~0_21} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 36596#L531-1 [4341] L531-1-->L1033: Formula: (and (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp~3] 36833#L1033 [4169] L1033-->L1033-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_6) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} AuxVars[] AssignedVars[] 36940#L1033-1 [2919] L1033-1-->L494-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_3|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_6, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_exists_runnable_thread_~__retres1~7, ULTIMATE.start_stop_simulation_#res] 37385#L494-2 [2882] L494-2-->L531-2: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9 1) (= v_~m_st~0_6 0)) InVars {~m_st~0=v_~m_st~0_6} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9, ~m_st~0=v_~m_st~0_6} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 37379#L531-2 [4343] L531-2-->L988: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 37371#L988 [3240] L988-->L995: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 37365#L995 [4354] L995-->L1014-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_6|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_#t~ret17, ULTIMATE.start_stop_simulation_#res] 37063#L1014-1 [2020-06-22 00:13:19,442 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:19,442 INFO L82 PathProgramCache]: Analyzing trace with hash -1077410029, now seen corresponding path program 1 times [2020-06-22 00:13:19,442 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:19,442 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:19,443 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:19,443 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2020-06-22 00:13:19,443 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:19,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:19,491 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:19,492 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:19,492 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2020-06-22 00:13:19,492 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-06-22 00:13:19,492 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:19,492 INFO L82 PathProgramCache]: Analyzing trace with hash 2072517841, now seen corresponding path program 3 times [2020-06-22 00:13:19,493 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:19,493 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:19,493 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:19,494 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:19,494 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:19,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:19,517 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:19,517 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:19,517 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2020-06-22 00:13:19,518 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-06-22 00:13:19,518 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2020-06-22 00:13:19,518 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2020-06-22 00:13:19,518 INFO L87 Difference]: Start difference. First operand 1678 states and 2969 transitions. cyclomatic complexity: 1292 Second operand 6 states. [2020-06-22 00:13:21,542 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-06-22 00:13:21,542 INFO L93 Difference]: Finished difference Result 4271 states and 7607 transitions. [2020-06-22 00:13:21,543 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2020-06-22 00:13:21,543 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4271 states and 7607 transitions. [2020-06-22 00:13:21,557 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4197 [2020-06-22 00:13:21,573 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4271 states to 4271 states and 7607 transitions. [2020-06-22 00:13:21,573 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4271 [2020-06-22 00:13:21,575 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4271 [2020-06-22 00:13:21,575 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4271 states and 7607 transitions. [2020-06-22 00:13:21,579 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-06-22 00:13:21,579 INFO L706 BuchiCegarLoop]: Abstraction has 4271 states and 7607 transitions. [2020-06-22 00:13:21,582 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4271 states and 7607 transitions. [2020-06-22 00:13:21,604 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4271 to 1682. [2020-06-22 00:13:21,604 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1682 states. [2020-06-22 00:13:21,607 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1682 states to 1682 states and 2948 transitions. [2020-06-22 00:13:21,607 INFO L729 BuchiCegarLoop]: Abstraction has 1682 states and 2948 transitions. [2020-06-22 00:13:21,607 INFO L609 BuchiCegarLoop]: Abstraction has 1682 states and 2948 transitions. [2020-06-22 00:13:21,607 INFO L442 BuchiCegarLoop]: ======== Iteration 26============ [2020-06-22 00:13:21,607 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1682 states and 2948 transitions. [2020-06-22 00:13:21,611 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1608 [2020-06-22 00:13:21,611 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-06-22 00:13:21,611 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-06-22 00:13:21,612 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:21,612 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:21,614 INFO L794 eck$LassoCheckResult]: Stem: 42970#ULTIMATE.startENTRY [4266] ULTIMATE.startENTRY-->L444: Formula: (and (= 1 v_~t6_i~0_7) (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~M_E~0_37 2) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 0 v_~t6_pc~0_26) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_6~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= v_~T6_E~0_18 2) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~t6_st~0_24) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t6_pc~0=v_~t6_pc~0_26, ~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~T6_E~0=v_~T6_E~0_18, ~M_E~0=v_~M_E~0_37, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ~T4_E~0=v_~T4_E~0_18, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_4|, ~t6_i~0=v_~t6_i~0_7, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ULTIMATE.start_main_~__retres1~8=v_ULTIMATE.start_main_~__retres1~8_6, ~T2_E~0=v_~T2_E~0_18, ~t6_st~0=v_~t6_st~0_24, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_6~0=v_~E_6~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t6_pc~0, ~t5_i~0, ~t1_pc~0, ~t5_st~0, ~T6_E~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ~T4_E~0, ULTIMATE.start_start_simulation_#t~ret17, ~t6_i~0, ~t2_st~0, ~t2_pc~0, ULTIMATE.start_main_~__retres1~8, ~T2_E~0, ~t6_st~0, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_6~0, ULTIMATE.start_main_#res, ~E_2~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 42580#L444 [2453] L444-->L451-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 42581#L451-1 [3030] L451-1-->L456-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 42666#L456-1 [2574] L456-1-->L461-1: Formula: (and (= v_~t2_st~0_2 0) (= 1 v_~t2_i~0_3)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_2} AuxVars[] AssignedVars[~t2_st~0] 42667#L461-1 [2880] L461-1-->L466-1: Formula: (and (= v_~t3_st~0_3 0) (= v_~t3_i~0_3 1)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_3, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 42582#L466-1 [2457] L466-1-->L471-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 42583#L471-1 [3209] L471-1-->L476-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 42814#L476-1 [2761] L476-1-->L481-1: Formula: (and (= 1 v_~t6_i~0_3) (= v_~t6_st~0_4 0)) InVars {~t6_i~0=v_~t6_i~0_3} OutVars{~t6_st~0=v_~t6_st~0_4, ~t6_i~0=v_~t6_i~0_3} AuxVars[] AssignedVars[~t6_st~0] 42815#L481-1 [3652] L481-1-->L660-1: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 42984#L660-1 [3654] L660-1-->L665-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 42496#L665-1 [3655] L665-1-->L670-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 42497#L670-1 [3658] L670-1-->L675-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 42589#L675-1 [3659] L675-1-->L680-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 42590#L680-1 [3661] L680-1-->L685-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 42825#L685-1 [3663] L685-1-->L690-1: Formula: (< 0 v_~T6_E~0_4) InVars {~T6_E~0=v_~T6_E~0_4} OutVars{~T6_E~0=v_~T6_E~0_4} AuxVars[] AssignedVars[] 42826#L690-1 [3665] L690-1-->L695-1: Formula: (> v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 42710#L695-1 [3668] L695-1-->L700-1: Formula: (> v_~E_2~0_6 0) InVars {~E_2~0=v_~E_2~0_6} OutVars{~E_2~0=v_~E_2~0_6} AuxVars[] AssignedVars[] 42711#L700-1 [3670] L700-1-->L705-1: Formula: (> v_~E_3~0_6 0) InVars {~E_3~0=v_~E_3~0_6} OutVars{~E_3~0=v_~E_3~0_6} AuxVars[] AssignedVars[] 42954#L705-1 [3672] L705-1-->L710-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 42650#L710-1 [3674] L710-1-->L715-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 42651#L715-1 [3675] L715-1-->L720-1: Formula: (> v_~E_6~0_4 0) InVars {~E_6~0=v_~E_6~0_4} OutVars{~E_6~0=v_~E_6~0_4} AuxVars[] AssignedVars[] 42532#L720-1 [2412] L720-1-->L310: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_7, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_4|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_4|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_7, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_4, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_4, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_2|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_2|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_4|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_4|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_7, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_2|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_4} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 42533#L310 [3678] L310-->L310-2: Formula: (< v_~m_pc~0_5 1) InVars {~m_pc~0=v_~m_pc~0_5} OutVars{~m_pc~0=v_~m_pc~0_5} AuxVars[] AssignedVars[] 42682#L310-2 [2805] L310-2-->L321: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_11 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 42677#L321 [4267] L321-->L815: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 42678#L815 [2976] L815-->L815-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_12) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} AuxVars[] AssignedVars[] 42949#L815-2 [2961] L815-2-->L329: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 42878#L329 [3683] L329-->L329-2: Formula: (< v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 42879#L329-2 [2861] L329-2-->L340: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 42874#L340 [4268] L340-->L823: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 42875#L823 [3234] L823-->L823-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} AuxVars[] AssignedVars[] 43061#L823-2 [3235] L823-2-->L348: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_4|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 43037#L348 [3690] L348-->L348-2: Formula: (< v_~t2_pc~0_5 1) InVars {~t2_pc~0=v_~t2_pc~0_5} OutVars{~t2_pc~0=v_~t2_pc~0_5} AuxVars[] AssignedVars[] 43039#L348-2 [3153] L348-2-->L359: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 43036#L359 [4269] L359-->L831: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 42657#L831 [3693] L831-->L831-2: Formula: (and (= v_~t2_st~0_5 0) (< v_ULTIMATE.start_activate_threads_~tmp___1~0_11 0)) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_11} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_11, ~t2_st~0=v_~t2_st~0_5} AuxVars[] AssignedVars[~t2_st~0] 42645#L831-2 [2520] L831-2-->L367: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_4|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 42585#L367 [3695] L367-->L367-2: Formula: (> 1 v_~t3_pc~0_5) InVars {~t3_pc~0=v_~t3_pc~0_5} OutVars{~t3_pc~0=v_~t3_pc~0_5} AuxVars[] AssignedVars[] 42561#L367-2 [2438] L367-2-->L378: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 42562#L378 [4270] L378-->L839: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 42584#L839 [2791] L839-->L839-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} AuxVars[] AssignedVars[] 42837#L839-2 [2794] L839-2-->L386: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_7, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 42752#L386 [2675] L386-->L387: Formula: (= v_~t4_pc~0_4 1) InVars {~t4_pc~0=v_~t4_pc~0_4} OutVars{~t4_pc~0=v_~t4_pc~0_4} AuxVars[] AssignedVars[] 42671#L387 [2588] L387-->L397: Formula: (and (= v_~E_4~0_7 1) (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_10 1)) InVars {~E_4~0=v_~E_4~0_7} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_10, ~E_4~0=v_~E_4~0_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 42673#L397 [4271] L397-->L847: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 42751#L847 [3084] L847-->L847-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} AuxVars[] AssignedVars[] 42991#L847-2 [3064] L847-2-->L405: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_4|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 42992#L405 [3708] L405-->L405-2: Formula: (> 1 v_~t5_pc~0_5) InVars {~t5_pc~0=v_~t5_pc~0_5} OutVars{~t5_pc~0=v_~t5_pc~0_5} AuxVars[] AssignedVars[] 42905#L405-2 [2940] L405-2-->L416: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 42937#L416 [4272] L416-->L855: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 43003#L855 [3711] L855-->L855-2: Formula: (and (> v_ULTIMATE.start_activate_threads_~tmp___4~0_11 0) (= v_~t5_st~0_7 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_11} OutVars{~t5_st~0=v_~t5_st~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_11} AuxVars[] AssignedVars[~t5_st~0] 43004#L855-2 [3093] L855-2-->L424: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_4|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 42629#L424 [3714] L424-->L424-2: Formula: (> v_~t6_pc~0_5 1) InVars {~t6_pc~0=v_~t6_pc~0_5} OutVars{~t6_pc~0=v_~t6_pc~0_5} AuxVars[] AssignedVars[] 42630#L424-2 [2503] L424-2-->L435: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 42626#L435 [4273] L435-->L863: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___5~0_49 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_28|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_28|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 42548#L863 [2425] L863-->L863-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___5~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} AuxVars[] AssignedVars[] 42519#L863-2 [3720] L863-2-->L733-1: Formula: (< v_~M_E~0_15 1) InVars {~M_E~0=v_~M_E~0_15} OutVars{~M_E~0=v_~M_E~0_15} AuxVars[] AssignedVars[] 42520#L733-1 [3722] L733-1-->L738-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 42952#L738-1 [3723] L738-1-->L743-1: Formula: (< 1 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 42648#L743-1 [3726] L743-1-->L748-1: Formula: (< 1 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 42649#L748-1 [3728] L748-1-->L753-1: Formula: (> v_~T4_E~0_10 1) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 42527#L753-1 [3729] L753-1-->L758-1: Formula: (< 1 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 42528#L758-1 [3732] L758-1-->L763-1: Formula: (< v_~T6_E~0_10 1) InVars {~T6_E~0=v_~T6_E~0_10} OutVars{~T6_E~0=v_~T6_E~0_10} AuxVars[] AssignedVars[] 42601#L763-1 [3733] L763-1-->L768-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 42602#L768-1 [3736] L768-1-->L773-1: Formula: (< 1 v_~E_2~0_14) InVars {~E_2~0=v_~E_2~0_14} OutVars{~E_2~0=v_~E_2~0_14} AuxVars[] AssignedVars[] 42819#L773-1 [3737] L773-1-->L778-1: Formula: (< 1 v_~E_3~0_14) InVars {~E_3~0=v_~E_3~0_14} OutVars{~E_3~0=v_~E_3~0_14} AuxVars[] AssignedVars[] 42820#L778-1 [3740] L778-1-->L783-1: Formula: (< 1 v_~E_4~0_14) InVars {~E_4~0=v_~E_4~0_14} OutVars{~E_4~0=v_~E_4~0_14} AuxVars[] AssignedVars[] 42701#L783-1 [3741] L783-1-->L788-1: Formula: (< 1 v_~E_5~0_14) InVars {~E_5~0=v_~E_5~0_14} OutVars{~E_5~0=v_~E_5~0_14} AuxVars[] AssignedVars[] 42702#L788-1 [3744] L788-1-->L1014-1: Formula: (< 1 v_~E_6~0_14) InVars {~E_6~0=v_~E_6~0_14} OutVars{~E_6~0=v_~E_6~0_14} AuxVars[] AssignedVars[] 43047#L1014-1 [2020-06-22 00:13:21,615 INFO L796 eck$LassoCheckResult]: Loop: 43047#L1014-1 [4274] L1014-1-->L635: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp_ndt_7~0=v_ULTIMATE.start_eval_~tmp_ndt_7~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp_ndt_7~0] 43199#L635 [4275] L635-->L494: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_37} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 43198#L494 [2876] L494-->L531: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21 1) (= v_~m_st~0_8 0)) InVars {~m_st~0=v_~m_st~0_8} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21, ~m_st~0=v_~m_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 43191#L531 [4276] L531-->L546: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 43189#L546 [4278] L546-->L660-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 43188#L660-2 [3747] L660-2-->L660-4: Formula: (> v_~M_E~0_30 0) InVars {~M_E~0=v_~M_E~0_30} OutVars{~M_E~0=v_~M_E~0_30} AuxVars[] AssignedVars[] 43187#L660-4 [3058] L660-4-->L665-3: Formula: (and (= v_~T1_E~0_11 1) (= v_~T1_E~0_12 0)) InVars {~T1_E~0=v_~T1_E~0_12} OutVars{~T1_E~0=v_~T1_E~0_11} AuxVars[] AssignedVars[~T1_E~0] 43186#L665-3 [3756] L665-3-->L670-3: Formula: (< 0 v_~T2_E~0_13) InVars {~T2_E~0=v_~T2_E~0_13} OutVars{~T2_E~0=v_~T2_E~0_13} AuxVars[] AssignedVars[] 43185#L670-3 [3762] L670-3-->L675-3: Formula: (< 0 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 43184#L675-3 [3768] L675-3-->L680-3: Formula: (> v_~T4_E~0_13 0) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 43183#L680-3 [3776] L680-3-->L685-3: Formula: (< 0 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 43182#L685-3 [3785] L685-3-->L690-3: Formula: (> v_~T6_E~0_13 0) InVars {~T6_E~0=v_~T6_E~0_13} OutVars{~T6_E~0=v_~T6_E~0_13} AuxVars[] AssignedVars[] 43181#L690-3 [3795] L690-3-->L695-3: Formula: (< 0 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 43180#L695-3 [3805] L695-3-->L700-3: Formula: (< 0 v_~E_2~0_31) InVars {~E_2~0=v_~E_2~0_31} OutVars{~E_2~0=v_~E_2~0_31} AuxVars[] AssignedVars[] 43179#L700-3 [3818] L700-3-->L705-3: Formula: (< 0 v_~E_3~0_31) InVars {~E_3~0=v_~E_3~0_31} OutVars{~E_3~0=v_~E_3~0_31} AuxVars[] AssignedVars[] 43178#L705-3 [2688] L705-3-->L710-3: Formula: (and (= v_~E_4~0_29 1) (= 0 v_~E_4~0_30)) InVars {~E_4~0=v_~E_4~0_30} OutVars{~E_4~0=v_~E_4~0_29} AuxVars[] AssignedVars[~E_4~0] 43177#L710-3 [3844] L710-3-->L715-3: Formula: (< 0 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 43176#L715-3 [3854] L715-3-->L720-3: Formula: (< 0 v_~E_6~0_31) InVars {~E_6~0=v_~E_6~0_31} OutVars{~E_6~0=v_~E_6~0_31} AuxVars[] AssignedVars[] 43175#L720-3 [2388] L720-3-->L310-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_43, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_43, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_25|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_25|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_25|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_43, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_43, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_43, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_25|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_25|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_25|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_25|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_43, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_25|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_43, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_43} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 42827#L310-21 [3870] L310-21-->L310-23: Formula: (< v_~m_pc~0_24 1) InVars {~m_pc~0=v_~m_pc~0_24} OutVars{~m_pc~0=v_~m_pc~0_24} AuxVars[] AssignedVars[] 42828#L310-23 [2785] L310-23-->L321-7: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_47 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_47} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 43946#L321-7 [4303] L321-7-->L815-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 43945#L815-21 [2667] L815-21-->L815-23: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_48) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_48} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_48} AuxVars[] AssignedVars[] 43944#L815-23 [2638] L815-23-->L329-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 43943#L329-21 [3911] L329-21-->L329-23: Formula: (< v_~t1_pc~0_24 1) InVars {~t1_pc~0=v_~t1_pc~0_24} OutVars{~t1_pc~0=v_~t1_pc~0_24} AuxVars[] AssignedVars[] 43167#L329-23 [3052] L329-23-->L340-7: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 43942#L340-7 [4310] L340-7-->L823-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 43941#L823-21 [2931] L823-21-->L823-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} AuxVars[] AssignedVars[] 43940#L823-23 [2934] L823-23-->L348-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_25|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 43938#L348-21 [3953] L348-21-->L348-23: Formula: (> 1 v_~t2_pc~0_24) InVars {~t2_pc~0=v_~t2_pc~0_24} OutVars{~t2_pc~0=v_~t2_pc~0_24} AuxVars[] AssignedVars[] 43937#L348-23 [3319] L348-23-->L359-7: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 43936#L359-7 [4317] L359-7-->L831-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 43935#L831-21 [2490] L831-21-->L831-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} AuxVars[] AssignedVars[] 43934#L831-23 [3197] L831-23-->L367-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_25|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 43933#L367-21 [3995] L367-21-->L367-23: Formula: (> v_~t3_pc~0_24 1) InVars {~t3_pc~0=v_~t3_pc~0_24} OutVars{~t3_pc~0=v_~t3_pc~0_24} AuxVars[] AssignedVars[] 43931#L367-23 [2385] L367-23-->L378-7: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 43930#L378-7 [4324] L378-7-->L839-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 43929#L839-21 [4023] L839-21-->L839-23: Formula: (and (= v_~t3_st~0_21 0) (> v_ULTIMATE.start_activate_threads_~tmp___2~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} OutVars{~t3_st~0=v_~t3_st~0_21, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} AuxVars[] AssignedVars[~t3_st~0] 43928#L839-23 [2722] L839-23-->L386-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_49, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 43927#L386-21 [2617] L386-21-->L387-7: Formula: (= 1 v_~t4_pc~0_23) InVars {~t4_pc~0=v_~t4_pc~0_23} OutVars{~t4_pc~0=v_~t4_pc~0_23} AuxVars[] AssignedVars[] 43925#L387-7 [2818] L387-7-->L397-7: Formula: (and (= 1 v_~E_4~0_32) (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_52 1)) InVars {~E_4~0=v_~E_4~0_32} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_52, ~E_4~0=v_~E_4~0_32} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 43924#L397-7 [4331] L397-7-->L847-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 43923#L847-21 [4065] L847-21-->L847-23: Formula: (and (= v_~t4_st~0_22 0) (< v_ULTIMATE.start_activate_threads_~tmp___3~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47, ~t4_st~0=v_~t4_st~0_22} AuxVars[] AssignedVars[~t4_st~0] 43922#L847-23 [2983] L847-23-->L405-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_25|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 43920#L405-21 [4080] L405-21-->L405-23: Formula: (> v_~t5_pc~0_24 1) InVars {~t5_pc~0=v_~t5_pc~0_24} OutVars{~t5_pc~0=v_~t5_pc~0_24} AuxVars[] AssignedVars[] 43919#L405-23 [2891] L405-23-->L416-7: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 43918#L416-7 [4338] L416-7-->L855-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 43917#L855-21 [3251] L855-21-->L855-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} AuxVars[] AssignedVars[] 43916#L855-23 [3257] L855-23-->L424-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_25|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 43914#L424-21 [4121] L424-21-->L424-23: Formula: (< 1 v_~t6_pc~0_24) InVars {~t6_pc~0=v_~t6_pc~0_24} OutVars{~t6_pc~0=v_~t6_pc~0_24} AuxVars[] AssignedVars[] 43913#L424-23 [3177] L424-23-->L435-7: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 43912#L435-7 [4340] L435-7-->L863-21: Formula: (and (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___5~0_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_35|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_41|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 43911#L863-21 [4135] L863-21-->L863-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___5~0_47 0) (= v_~t6_st~0_22 0)) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} OutVars{~t6_st~0=v_~t6_st~0_22, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} AuxVars[] AssignedVars[~t6_st~0] 43910#L863-23 [4137] L863-23-->L733-3: Formula: (< v_~M_E~0_35 1) InVars {~M_E~0=v_~M_E~0_35} OutVars{~M_E~0=v_~M_E~0_35} AuxVars[] AssignedVars[] 43909#L733-3 [3184] L733-3-->L738-3: Formula: (and (= v_~T1_E~0_15 1) (= v_~T1_E~0_14 2)) InVars {~T1_E~0=v_~T1_E~0_15} OutVars{~T1_E~0=v_~T1_E~0_14} AuxVars[] AssignedVars[~T1_E~0] 43908#L738-3 [4142] L738-3-->L743-3: Formula: (< 1 v_~T2_E~0_16) InVars {~T2_E~0=v_~T2_E~0_16} OutVars{~T2_E~0=v_~T2_E~0_16} AuxVars[] AssignedVars[] 43907#L743-3 [4143] L743-3-->L748-3: Formula: (< 1 v_~T3_E~0_16) InVars {~T3_E~0=v_~T3_E~0_16} OutVars{~T3_E~0=v_~T3_E~0_16} AuxVars[] AssignedVars[] 43906#L748-3 [4145] L748-3-->L753-3: Formula: (> v_~T4_E~0_16 1) InVars {~T4_E~0=v_~T4_E~0_16} OutVars{~T4_E~0=v_~T4_E~0_16} AuxVars[] AssignedVars[] 43905#L753-3 [4148] L753-3-->L758-3: Formula: (< 1 v_~T5_E~0_16) InVars {~T5_E~0=v_~T5_E~0_16} OutVars{~T5_E~0=v_~T5_E~0_16} AuxVars[] AssignedVars[] 43904#L758-3 [4149] L758-3-->L763-3: Formula: (> v_~T6_E~0_16 1) InVars {~T6_E~0=v_~T6_E~0_16} OutVars{~T6_E~0=v_~T6_E~0_16} AuxVars[] AssignedVars[] 43903#L763-3 [4151] L763-3-->L768-3: Formula: (< 1 v_~E_1~0_36) InVars {~E_1~0=v_~E_1~0_36} OutVars{~E_1~0=v_~E_1~0_36} AuxVars[] AssignedVars[] 43902#L768-3 [4154] L768-3-->L773-3: Formula: (< 1 v_~E_2~0_36) InVars {~E_2~0=v_~E_2~0_36} OutVars{~E_2~0=v_~E_2~0_36} AuxVars[] AssignedVars[] 43901#L773-3 [4156] L773-3-->L778-3: Formula: (< 1 v_~E_3~0_36) InVars {~E_3~0=v_~E_3~0_36} OutVars{~E_3~0=v_~E_3~0_36} AuxVars[] AssignedVars[] 43900#L778-3 [3308] L778-3-->L783-3: Formula: (and (= 1 v_~E_4~0_35) (= v_~E_4~0_34 2)) InVars {~E_4~0=v_~E_4~0_35} OutVars{~E_4~0=v_~E_4~0_34} AuxVars[] AssignedVars[~E_4~0] 43899#L783-3 [4160] L783-3-->L788-3: Formula: (< 1 v_~E_5~0_36) InVars {~E_5~0=v_~E_5~0_36} OutVars{~E_5~0=v_~E_5~0_36} AuxVars[] AssignedVars[] 43898#L788-3 [4162] L788-3-->L793-3: Formula: (< 1 v_~E_6~0_36) InVars {~E_6~0=v_~E_6~0_36} OutVars{~E_6~0=v_~E_6~0_36} AuxVars[] AssignedVars[] 43897#L793-3 [2966] L793-3-->L494-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_30} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 43896#L494-1 [2878] L494-1-->L531-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33 1) (= 0 v_~m_st~0_21)) InVars {~m_st~0=v_~m_st~0_21} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33, ~m_st~0=v_~m_st~0_21} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 42808#L531-1 [4341] L531-1-->L1033: Formula: (and (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp~3] 42809#L1033 [4169] L1033-->L1033-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_6) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} AuxVars[] AssignedVars[] 42915#L1033-1 [2919] L1033-1-->L494-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_3|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_6, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_exists_runnable_thread_~__retres1~7, ULTIMATE.start_stop_simulation_#res] 43231#L494-2 [2882] L494-2-->L531-2: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9 1) (= v_~m_st~0_6 0)) InVars {~m_st~0=v_~m_st~0_6} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9, ~m_st~0=v_~m_st~0_6} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 43222#L531-2 [4343] L531-2-->L988: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 43210#L988 [3240] L988-->L995: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 43204#L995 [4354] L995-->L1014-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_6|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_#t~ret17, ULTIMATE.start_stop_simulation_#res] 43047#L1014-1 [2020-06-22 00:13:21,615 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:21,615 INFO L82 PathProgramCache]: Analyzing trace with hash -2102902028, now seen corresponding path program 1 times [2020-06-22 00:13:21,615 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:21,615 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:21,616 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:21,616 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2020-06-22 00:13:21,616 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:21,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:21,659 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:21,659 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:21,659 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2020-06-22 00:13:21,660 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-06-22 00:13:21,660 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:21,660 INFO L82 PathProgramCache]: Analyzing trace with hash 2072517841, now seen corresponding path program 4 times [2020-06-22 00:13:21,660 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:21,660 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:21,661 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:21,661 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:21,661 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:21,663 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:21,682 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:21,682 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:21,682 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2020-06-22 00:13:21,682 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-06-22 00:13:21,683 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2020-06-22 00:13:21,683 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2020-06-22 00:13:21,683 INFO L87 Difference]: Start difference. First operand 1682 states and 2948 transitions. cyclomatic complexity: 1267 Second operand 6 states. [2020-06-22 00:13:22,396 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-06-22 00:13:22,396 INFO L93 Difference]: Finished difference Result 1682 states and 2917 transitions. [2020-06-22 00:13:22,396 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2020-06-22 00:13:22,397 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1682 states and 2917 transitions. [2020-06-22 00:13:22,402 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1608 [2020-06-22 00:13:22,408 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1682 states to 1682 states and 2917 transitions. [2020-06-22 00:13:22,408 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1682 [2020-06-22 00:13:22,409 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1682 [2020-06-22 00:13:22,409 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1682 states and 2917 transitions. [2020-06-22 00:13:22,411 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-06-22 00:13:22,411 INFO L706 BuchiCegarLoop]: Abstraction has 1682 states and 2917 transitions. [2020-06-22 00:13:22,412 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1682 states and 2917 transitions. [2020-06-22 00:13:22,426 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1682 to 1682. [2020-06-22 00:13:22,426 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1682 states. [2020-06-22 00:13:22,429 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1682 states to 1682 states and 2917 transitions. [2020-06-22 00:13:22,429 INFO L729 BuchiCegarLoop]: Abstraction has 1682 states and 2917 transitions. [2020-06-22 00:13:22,429 INFO L609 BuchiCegarLoop]: Abstraction has 1682 states and 2917 transitions. [2020-06-22 00:13:22,429 INFO L442 BuchiCegarLoop]: ======== Iteration 27============ [2020-06-22 00:13:22,429 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1682 states and 2917 transitions. [2020-06-22 00:13:22,433 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1608 [2020-06-22 00:13:22,433 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-06-22 00:13:22,433 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-06-22 00:13:22,434 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:22,435 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:22,436 INFO L794 eck$LassoCheckResult]: Stem: 46344#ULTIMATE.startENTRY [4266] ULTIMATE.startENTRY-->L444: Formula: (and (= 1 v_~t6_i~0_7) (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~M_E~0_37 2) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 0 v_~t6_pc~0_26) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_6~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= v_~T6_E~0_18 2) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~t6_st~0_24) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t6_pc~0=v_~t6_pc~0_26, ~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~T6_E~0=v_~T6_E~0_18, ~M_E~0=v_~M_E~0_37, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ~T4_E~0=v_~T4_E~0_18, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_4|, ~t6_i~0=v_~t6_i~0_7, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ULTIMATE.start_main_~__retres1~8=v_ULTIMATE.start_main_~__retres1~8_6, ~T2_E~0=v_~T2_E~0_18, ~t6_st~0=v_~t6_st~0_24, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_6~0=v_~E_6~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t6_pc~0, ~t5_i~0, ~t1_pc~0, ~t5_st~0, ~T6_E~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ~T4_E~0, ULTIMATE.start_start_simulation_#t~ret17, ~t6_i~0, ~t2_st~0, ~t2_pc~0, ULTIMATE.start_main_~__retres1~8, ~T2_E~0, ~t6_st~0, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_6~0, ULTIMATE.start_main_#res, ~E_2~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 45963#L444 [2453] L444-->L451-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 45964#L451-1 [3030] L451-1-->L456-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 46052#L456-1 [2574] L456-1-->L461-1: Formula: (and (= v_~t2_st~0_2 0) (= 1 v_~t2_i~0_3)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_2} AuxVars[] AssignedVars[~t2_st~0] 46053#L461-1 [2880] L461-1-->L466-1: Formula: (and (= v_~t3_st~0_3 0) (= v_~t3_i~0_3 1)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_3, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 45965#L466-1 [2457] L466-1-->L471-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 45966#L471-1 [3209] L471-1-->L476-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 46202#L476-1 [2761] L476-1-->L481-1: Formula: (and (= 1 v_~t6_i~0_3) (= v_~t6_st~0_4 0)) InVars {~t6_i~0=v_~t6_i~0_3} OutVars{~t6_st~0=v_~t6_st~0_4, ~t6_i~0=v_~t6_i~0_3} AuxVars[] AssignedVars[~t6_st~0] 46203#L481-1 [3652] L481-1-->L660-1: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 46360#L660-1 [3654] L660-1-->L665-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 45882#L665-1 [3655] L665-1-->L670-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 45883#L670-1 [3658] L670-1-->L675-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 45972#L675-1 [3659] L675-1-->L680-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 45973#L680-1 [3661] L680-1-->L685-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 46213#L685-1 [3663] L685-1-->L690-1: Formula: (< 0 v_~T6_E~0_4) InVars {~T6_E~0=v_~T6_E~0_4} OutVars{~T6_E~0=v_~T6_E~0_4} AuxVars[] AssignedVars[] 46214#L690-1 [3665] L690-1-->L695-1: Formula: (> v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 46096#L695-1 [3668] L695-1-->L700-1: Formula: (> v_~E_2~0_6 0) InVars {~E_2~0=v_~E_2~0_6} OutVars{~E_2~0=v_~E_2~0_6} AuxVars[] AssignedVars[] 46097#L700-1 [3670] L700-1-->L705-1: Formula: (> v_~E_3~0_6 0) InVars {~E_3~0=v_~E_3~0_6} OutVars{~E_3~0=v_~E_3~0_6} AuxVars[] AssignedVars[] 46328#L705-1 [3672] L705-1-->L710-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 46035#L710-1 [3674] L710-1-->L715-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 46036#L715-1 [3675] L715-1-->L720-1: Formula: (> v_~E_6~0_4 0) InVars {~E_6~0=v_~E_6~0_4} OutVars{~E_6~0=v_~E_6~0_4} AuxVars[] AssignedVars[] 45916#L720-1 [2412] L720-1-->L310: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_7, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_4|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_4|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_7, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_4, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_4, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_2|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_2|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_4|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_4|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_7, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_2|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_4} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 45917#L310 [3678] L310-->L310-2: Formula: (< v_~m_pc~0_5 1) InVars {~m_pc~0=v_~m_pc~0_5} OutVars{~m_pc~0=v_~m_pc~0_5} AuxVars[] AssignedVars[] 46068#L310-2 [2805] L310-2-->L321: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_11 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 46066#L321 [4267] L321-->L815: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 46067#L815 [2976] L815-->L815-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_12) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} AuxVars[] AssignedVars[] 46324#L815-2 [2961] L815-2-->L329: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 46257#L329 [3683] L329-->L329-2: Formula: (< v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 46258#L329-2 [2861] L329-2-->L340: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 46255#L340 [4268] L340-->L823: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 46256#L823 [3234] L823-->L823-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} AuxVars[] AssignedVars[] 46431#L823-2 [3235] L823-2-->L348: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_4|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 46409#L348 [3690] L348-->L348-2: Formula: (< v_~t2_pc~0_5 1) InVars {~t2_pc~0=v_~t2_pc~0_5} OutVars{~t2_pc~0=v_~t2_pc~0_5} AuxVars[] AssignedVars[] 46411#L348-2 [3153] L348-2-->L359: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 46407#L359 [4269] L359-->L831: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 46042#L831 [2537] L831-->L831-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} AuxVars[] AssignedVars[] 46030#L831-2 [2520] L831-2-->L367: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_4|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 45968#L367 [3695] L367-->L367-2: Formula: (> 1 v_~t3_pc~0_5) InVars {~t3_pc~0=v_~t3_pc~0_5} OutVars{~t3_pc~0=v_~t3_pc~0_5} AuxVars[] AssignedVars[] 45945#L367-2 [2438] L367-2-->L378: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 45946#L378 [4270] L378-->L839: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 45967#L839 [2791] L839-->L839-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} AuxVars[] AssignedVars[] 46224#L839-2 [2794] L839-2-->L386: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_7, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 46138#L386 [2675] L386-->L387: Formula: (= v_~t4_pc~0_4 1) InVars {~t4_pc~0=v_~t4_pc~0_4} OutVars{~t4_pc~0=v_~t4_pc~0_4} AuxVars[] AssignedVars[] 46057#L387 [2588] L387-->L397: Formula: (and (= v_~E_4~0_7 1) (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_10 1)) InVars {~E_4~0=v_~E_4~0_7} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_10, ~E_4~0=v_~E_4~0_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 46059#L397 [4271] L397-->L847: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 46137#L847 [3084] L847-->L847-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} AuxVars[] AssignedVars[] 46366#L847-2 [3064] L847-2-->L405: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_4|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 46367#L405 [3708] L405-->L405-2: Formula: (> 1 v_~t5_pc~0_5) InVars {~t5_pc~0=v_~t5_pc~0_5} OutVars{~t5_pc~0=v_~t5_pc~0_5} AuxVars[] AssignedVars[] 46284#L405-2 [2940] L405-2-->L416: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 46313#L416 [4272] L416-->L855: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 46376#L855 [3711] L855-->L855-2: Formula: (and (> v_ULTIMATE.start_activate_threads_~tmp___4~0_11 0) (= v_~t5_st~0_7 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_11} OutVars{~t5_st~0=v_~t5_st~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_11} AuxVars[] AssignedVars[~t5_st~0] 46377#L855-2 [3093] L855-2-->L424: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_4|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 46013#L424 [3714] L424-->L424-2: Formula: (> v_~t6_pc~0_5 1) InVars {~t6_pc~0=v_~t6_pc~0_5} OutVars{~t6_pc~0=v_~t6_pc~0_5} AuxVars[] AssignedVars[] 46014#L424-2 [2503] L424-2-->L435: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 46012#L435 [4273] L435-->L863: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___5~0_49 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_28|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_28|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 45932#L863 [2425] L863-->L863-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___5~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} AuxVars[] AssignedVars[] 45906#L863-2 [3720] L863-2-->L733-1: Formula: (< v_~M_E~0_15 1) InVars {~M_E~0=v_~M_E~0_15} OutVars{~M_E~0=v_~M_E~0_15} AuxVars[] AssignedVars[] 45907#L733-1 [3722] L733-1-->L738-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 46326#L738-1 [3723] L738-1-->L743-1: Formula: (< 1 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 46033#L743-1 [3726] L743-1-->L748-1: Formula: (< 1 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 46034#L748-1 [3728] L748-1-->L753-1: Formula: (> v_~T4_E~0_10 1) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 45911#L753-1 [3729] L753-1-->L758-1: Formula: (< 1 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 45912#L758-1 [3732] L758-1-->L763-1: Formula: (< v_~T6_E~0_10 1) InVars {~T6_E~0=v_~T6_E~0_10} OutVars{~T6_E~0=v_~T6_E~0_10} AuxVars[] AssignedVars[] 45984#L763-1 [3733] L763-1-->L768-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 45985#L768-1 [3736] L768-1-->L773-1: Formula: (< 1 v_~E_2~0_14) InVars {~E_2~0=v_~E_2~0_14} OutVars{~E_2~0=v_~E_2~0_14} AuxVars[] AssignedVars[] 46206#L773-1 [3737] L773-1-->L778-1: Formula: (< 1 v_~E_3~0_14) InVars {~E_3~0=v_~E_3~0_14} OutVars{~E_3~0=v_~E_3~0_14} AuxVars[] AssignedVars[] 46207#L778-1 [3740] L778-1-->L783-1: Formula: (< 1 v_~E_4~0_14) InVars {~E_4~0=v_~E_4~0_14} OutVars{~E_4~0=v_~E_4~0_14} AuxVars[] AssignedVars[] 46089#L783-1 [3741] L783-1-->L788-1: Formula: (< 1 v_~E_5~0_14) InVars {~E_5~0=v_~E_5~0_14} OutVars{~E_5~0=v_~E_5~0_14} AuxVars[] AssignedVars[] 46090#L788-1 [3744] L788-1-->L1014-1: Formula: (< 1 v_~E_6~0_14) InVars {~E_6~0=v_~E_6~0_14} OutVars{~E_6~0=v_~E_6~0_14} AuxVars[] AssignedVars[] 45924#L1014-1 [2020-06-22 00:13:22,437 INFO L796 eck$LassoCheckResult]: Loop: 45924#L1014-1 [4274] L1014-1-->L635: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp_ndt_7~0=v_ULTIMATE.start_eval_~tmp_ndt_7~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp_ndt_7~0] 45888#L635 [4275] L635-->L494: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_37} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 46280#L494 [2876] L494-->L531: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21 1) (= v_~m_st~0_8 0)) InVars {~m_st~0=v_~m_st~0_8} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21, ~m_st~0=v_~m_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 45956#L531 [4276] L531-->L546: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 46193#L546 [4278] L546-->L660-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 46415#L660-2 [3747] L660-2-->L660-4: Formula: (> v_~M_E~0_30 0) InVars {~M_E~0=v_~M_E~0_30} OutVars{~M_E~0=v_~M_E~0_30} AuxVars[] AssignedVars[] 47437#L660-4 [3058] L660-4-->L665-3: Formula: (and (= v_~T1_E~0_11 1) (= v_~T1_E~0_12 0)) InVars {~T1_E~0=v_~T1_E~0_12} OutVars{~T1_E~0=v_~T1_E~0_11} AuxVars[] AssignedVars[~T1_E~0] 47436#L665-3 [3756] L665-3-->L670-3: Formula: (< 0 v_~T2_E~0_13) InVars {~T2_E~0=v_~T2_E~0_13} OutVars{~T2_E~0=v_~T2_E~0_13} AuxVars[] AssignedVars[] 47435#L670-3 [3762] L670-3-->L675-3: Formula: (< 0 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 47434#L675-3 [3768] L675-3-->L680-3: Formula: (> v_~T4_E~0_13 0) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 47433#L680-3 [3776] L680-3-->L685-3: Formula: (< 0 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 47429#L685-3 [3785] L685-3-->L690-3: Formula: (> v_~T6_E~0_13 0) InVars {~T6_E~0=v_~T6_E~0_13} OutVars{~T6_E~0=v_~T6_E~0_13} AuxVars[] AssignedVars[] 47427#L690-3 [3795] L690-3-->L695-3: Formula: (< 0 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 47425#L695-3 [3805] L695-3-->L700-3: Formula: (< 0 v_~E_2~0_31) InVars {~E_2~0=v_~E_2~0_31} OutVars{~E_2~0=v_~E_2~0_31} AuxVars[] AssignedVars[] 47421#L700-3 [3818] L700-3-->L705-3: Formula: (< 0 v_~E_3~0_31) InVars {~E_3~0=v_~E_3~0_31} OutVars{~E_3~0=v_~E_3~0_31} AuxVars[] AssignedVars[] 47419#L705-3 [2688] L705-3-->L710-3: Formula: (and (= v_~E_4~0_29 1) (= 0 v_~E_4~0_30)) InVars {~E_4~0=v_~E_4~0_30} OutVars{~E_4~0=v_~E_4~0_29} AuxVars[] AssignedVars[~E_4~0] 47417#L710-3 [3844] L710-3-->L715-3: Formula: (< 0 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 47416#L715-3 [3854] L715-3-->L720-3: Formula: (< 0 v_~E_6~0_31) InVars {~E_6~0=v_~E_6~0_31} OutVars{~E_6~0=v_~E_6~0_31} AuxVars[] AssignedVars[] 47415#L720-3 [2388] L720-3-->L310-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_43, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_43, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_25|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_25|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_25|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_43, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_43, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_43, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_25|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_25|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_25|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_25|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_43, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_25|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_43, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_43} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 46215#L310-21 [3870] L310-21-->L310-23: Formula: (< v_~m_pc~0_24 1) InVars {~m_pc~0=v_~m_pc~0_24} OutVars{~m_pc~0=v_~m_pc~0_24} AuxVars[] AssignedVars[] 46216#L310-23 [2785] L310-23-->L321-7: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_47 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_47} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 47272#L321-7 [4303] L321-7-->L815-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 47270#L815-21 [2667] L815-21-->L815-23: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_48) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_48} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_48} AuxVars[] AssignedVars[] 47269#L815-23 [2638] L815-23-->L329-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 46357#L329-21 [3911] L329-21-->L329-23: Formula: (< v_~t1_pc~0_24 1) InVars {~t1_pc~0=v_~t1_pc~0_24} OutVars{~t1_pc~0=v_~t1_pc~0_24} AuxVars[] AssignedVars[] 46358#L329-23 [3052] L329-23-->L340-7: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 46246#L340-7 [4310] L340-7-->L823-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 46247#L823-21 [2931] L823-21-->L823-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} AuxVars[] AssignedVars[] 46304#L823-23 [2934] L823-23-->L348-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_25|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 46306#L348-21 [3953] L348-21-->L348-23: Formula: (> 1 v_~t2_pc~0_24) InVars {~t2_pc~0=v_~t2_pc~0_24} OutVars{~t2_pc~0=v_~t2_pc~0_24} AuxVars[] AssignedVars[] 46436#L348-23 [3319] L348-23-->L359-7: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 46403#L359-7 [4317] L359-7-->L831-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 46003#L831-21 [2490] L831-21-->L831-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} AuxVars[] AssignedVars[] 46004#L831-23 [3197] L831-23-->L367-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_25|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 45913#L367-21 [3995] L367-21-->L367-23: Formula: (> v_~t3_pc~0_24 1) InVars {~t3_pc~0=v_~t3_pc~0_24} OutVars{~t3_pc~0=v_~t3_pc~0_24} AuxVars[] AssignedVars[] 45880#L367-23 [2385] L367-23-->L378-7: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 45881#L378-7 [4324] L378-7-->L839-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 45937#L839-21 [4023] L839-21-->L839-23: Formula: (and (= v_~t3_st~0_21 0) (> v_ULTIMATE.start_activate_threads_~tmp___2~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} OutVars{~t3_st~0=v_~t3_st~0_21, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} AuxVars[] AssignedVars[~t3_st~0] 46165#L839-23 [2722] L839-23-->L386-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_49, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 46091#L386-21 [4037] L386-21-->L386-23: Formula: (< 1 v_~t4_pc~0_24) InVars {~t4_pc~0=v_~t4_pc~0_24} OutVars{~t4_pc~0=v_~t4_pc~0_24} AuxVars[] AssignedVars[] 46092#L386-23 [2623] L386-23-->L397-7: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 46098#L397-7 [4331] L397-7-->L847-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 46128#L847-21 [4065] L847-21-->L847-23: Formula: (and (= v_~t4_st~0_22 0) (< v_ULTIMATE.start_activate_threads_~tmp___3~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47, ~t4_st~0=v_~t4_st~0_22} AuxVars[] AssignedVars[~t4_st~0] 46335#L847-23 [2983] L847-23-->L405-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_25|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 46292#L405-21 [4080] L405-21-->L405-23: Formula: (> v_~t5_pc~0_24 1) InVars {~t5_pc~0=v_~t5_pc~0_24} OutVars{~t5_pc~0=v_~t5_pc~0_24} AuxVars[] AssignedVars[] 46277#L405-23 [2891] L405-23-->L416-7: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 46287#L416-7 [4338] L416-7-->L855-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 46299#L855-21 [3251] L855-21-->L855-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} AuxVars[] AssignedVars[] 46434#L855-23 [3257] L855-23-->L424-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_25|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 46417#L424-21 [4121] L424-21-->L424-23: Formula: (< 1 v_~t6_pc~0_24) InVars {~t6_pc~0=v_~t6_pc~0_24} OutVars{~t6_pc~0=v_~t6_pc~0_24} AuxVars[] AssignedVars[] 46396#L424-23 [3177] L424-23-->L435-7: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 45998#L435-7 [4340] L435-7-->L863-21: Formula: (and (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___5~0_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_35|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_41|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 45999#L863-21 [4135] L863-21-->L863-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___5~0_47 0) (= v_~t6_st~0_22 0)) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} OutVars{~t6_st~0=v_~t6_st~0_22, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} AuxVars[] AssignedVars[~t6_st~0] 46043#L863-23 [4137] L863-23-->L733-3: Formula: (< v_~M_E~0_35 1) InVars {~M_E~0=v_~M_E~0_35} OutVars{~M_E~0=v_~M_E~0_35} AuxVars[] AssignedVars[] 46044#L733-3 [3184] L733-3-->L738-3: Formula: (and (= v_~T1_E~0_15 1) (= v_~T1_E~0_14 2)) InVars {~T1_E~0=v_~T1_E~0_15} OutVars{~T1_E~0=v_~T1_E~0_14} AuxVars[] AssignedVars[~T1_E~0] 46329#L738-3 [4142] L738-3-->L743-3: Formula: (< 1 v_~T2_E~0_16) InVars {~T2_E~0=v_~T2_E~0_16} OutVars{~T2_E~0=v_~T2_E~0_16} AuxVars[] AssignedVars[] 46023#L743-3 [4143] L743-3-->L748-3: Formula: (< 1 v_~T3_E~0_16) InVars {~T3_E~0=v_~T3_E~0_16} OutVars{~T3_E~0=v_~T3_E~0_16} AuxVars[] AssignedVars[] 46024#L748-3 [4145] L748-3-->L753-3: Formula: (> v_~T4_E~0_16 1) InVars {~T4_E~0=v_~T4_E~0_16} OutVars{~T4_E~0=v_~T4_E~0_16} AuxVars[] AssignedVars[] 45878#L753-3 [4148] L753-3-->L758-3: Formula: (< 1 v_~T5_E~0_16) InVars {~T5_E~0=v_~T5_E~0_16} OutVars{~T5_E~0=v_~T5_E~0_16} AuxVars[] AssignedVars[] 45879#L758-3 [4149] L758-3-->L763-3: Formula: (> v_~T6_E~0_16 1) InVars {~T6_E~0=v_~T6_E~0_16} OutVars{~T6_E~0=v_~T6_E~0_16} AuxVars[] AssignedVars[] 45970#L763-3 [4151] L763-3-->L768-3: Formula: (< 1 v_~E_1~0_36) InVars {~E_1~0=v_~E_1~0_36} OutVars{~E_1~0=v_~E_1~0_36} AuxVars[] AssignedVars[] 45971#L768-3 [4154] L768-3-->L773-3: Formula: (< 1 v_~E_2~0_36) InVars {~E_2~0=v_~E_2~0_36} OutVars{~E_2~0=v_~E_2~0_36} AuxVars[] AssignedVars[] 46210#L773-3 [4156] L773-3-->L778-3: Formula: (< 1 v_~E_3~0_36) InVars {~E_3~0=v_~E_3~0_36} OutVars{~E_3~0=v_~E_3~0_36} AuxVars[] AssignedVars[] 46211#L778-3 [3308] L778-3-->L783-3: Formula: (and (= 1 v_~E_4~0_35) (= v_~E_4~0_34 2)) InVars {~E_4~0=v_~E_4~0_35} OutVars{~E_4~0=v_~E_4~0_34} AuxVars[] AssignedVars[~E_4~0] 46094#L783-3 [4160] L783-3-->L788-3: Formula: (< 1 v_~E_5~0_36) InVars {~E_5~0=v_~E_5~0_36} OutVars{~E_5~0=v_~E_5~0_36} AuxVars[] AssignedVars[] 46095#L788-3 [4162] L788-3-->L793-3: Formula: (< 1 v_~E_6~0_36) InVars {~E_6~0=v_~E_6~0_36} OutVars{~E_6~0=v_~E_6~0_36} AuxVars[] AssignedVars[] 46327#L793-3 [2966] L793-3-->L494-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_30} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 46281#L494-1 [2878] L494-1-->L531-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33 1) (= 0 v_~m_st~0_21)) InVars {~m_st~0=v_~m_st~0_21} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33, ~m_st~0=v_~m_st~0_21} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 45958#L531-1 [4341] L531-1-->L1033: Formula: (and (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp~3] 46194#L1033 [4169] L1033-->L1033-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_6) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} AuxVars[] AssignedVars[] 45927#L1033-1 [2919] L1033-1-->L494-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_3|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_6, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_exists_runnable_thread_~__retres1~7, ULTIMATE.start_stop_simulation_#res] 46282#L494-2 [2882] L494-2-->L531-2: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9 1) (= v_~m_st~0_6 0)) InVars {~m_st~0=v_~m_st~0_6} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9, ~m_st~0=v_~m_st~0_6} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 45962#L531-2 [4343] L531-2-->L988: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 46200#L988 [3240] L988-->L995: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 45923#L995 [4354] L995-->L1014-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_6|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_#t~ret17, ULTIMATE.start_stop_simulation_#res] 45924#L1014-1 [2020-06-22 00:13:22,437 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:22,437 INFO L82 PathProgramCache]: Analyzing trace with hash 2134288120, now seen corresponding path program 1 times [2020-06-22 00:13:22,437 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:22,438 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:22,438 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:22,438 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2020-06-22 00:13:22,439 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:22,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:22,461 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:22,462 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:22,462 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-06-22 00:13:22,462 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-06-22 00:13:22,462 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:22,462 INFO L82 PathProgramCache]: Analyzing trace with hash -216351806, now seen corresponding path program 2 times [2020-06-22 00:13:22,463 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:22,463 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:22,463 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:22,463 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:22,464 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:22,466 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:22,487 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:22,487 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:22,488 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2020-06-22 00:13:22,488 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-06-22 00:13:22,488 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-06-22 00:13:22,488 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-06-22 00:13:22,488 INFO L87 Difference]: Start difference. First operand 1682 states and 2917 transitions. cyclomatic complexity: 1236 Second operand 3 states. [2020-06-22 00:13:23,293 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-06-22 00:13:23,294 INFO L93 Difference]: Finished difference Result 3161 states and 5424 transitions. [2020-06-22 00:13:23,294 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-06-22 00:13:23,294 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3161 states and 5424 transitions. [2020-06-22 00:13:23,304 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3088 [2020-06-22 00:13:23,313 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3161 states to 3161 states and 5424 transitions. [2020-06-22 00:13:23,314 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3161 [2020-06-22 00:13:23,315 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3161 [2020-06-22 00:13:23,315 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3161 states and 5424 transitions. [2020-06-22 00:13:23,318 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-06-22 00:13:23,319 INFO L706 BuchiCegarLoop]: Abstraction has 3161 states and 5424 transitions. [2020-06-22 00:13:23,320 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3161 states and 5424 transitions. [2020-06-22 00:13:23,348 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3161 to 3093. [2020-06-22 00:13:23,348 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3093 states. [2020-06-22 00:13:23,353 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3093 states to 3093 states and 5308 transitions. [2020-06-22 00:13:23,353 INFO L729 BuchiCegarLoop]: Abstraction has 3093 states and 5308 transitions. [2020-06-22 00:13:23,353 INFO L609 BuchiCegarLoop]: Abstraction has 3093 states and 5308 transitions. [2020-06-22 00:13:23,354 INFO L442 BuchiCegarLoop]: ======== Iteration 28============ [2020-06-22 00:13:23,354 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3093 states and 5308 transitions. [2020-06-22 00:13:23,361 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3020 [2020-06-22 00:13:23,361 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-06-22 00:13:23,361 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-06-22 00:13:23,362 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:23,362 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:23,363 INFO L794 eck$LassoCheckResult]: Stem: 51214#ULTIMATE.startENTRY [4266] ULTIMATE.startENTRY-->L444: Formula: (and (= 1 v_~t6_i~0_7) (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~M_E~0_37 2) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 0 v_~t6_pc~0_26) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_6~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= v_~T6_E~0_18 2) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~t6_st~0_24) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t6_pc~0=v_~t6_pc~0_26, ~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~T6_E~0=v_~T6_E~0_18, ~M_E~0=v_~M_E~0_37, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ~T4_E~0=v_~T4_E~0_18, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_4|, ~t6_i~0=v_~t6_i~0_7, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ULTIMATE.start_main_~__retres1~8=v_ULTIMATE.start_main_~__retres1~8_6, ~T2_E~0=v_~T2_E~0_18, ~t6_st~0=v_~t6_st~0_24, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_6~0=v_~E_6~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t6_pc~0, ~t5_i~0, ~t1_pc~0, ~t5_st~0, ~T6_E~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ~T4_E~0, ULTIMATE.start_start_simulation_#t~ret17, ~t6_i~0, ~t2_st~0, ~t2_pc~0, ULTIMATE.start_main_~__retres1~8, ~T2_E~0, ~t6_st~0, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_6~0, ULTIMATE.start_main_#res, ~E_2~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 50816#L444 [2453] L444-->L451-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 50817#L451-1 [3030] L451-1-->L456-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 50905#L456-1 [2574] L456-1-->L461-1: Formula: (and (= v_~t2_st~0_2 0) (= 1 v_~t2_i~0_3)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_2} AuxVars[] AssignedVars[~t2_st~0] 50906#L461-1 [2880] L461-1-->L466-1: Formula: (and (= v_~t3_st~0_3 0) (= v_~t3_i~0_3 1)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_3, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 50818#L466-1 [2457] L466-1-->L471-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 50819#L471-1 [3209] L471-1-->L476-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 51055#L476-1 [2761] L476-1-->L481-1: Formula: (and (= 1 v_~t6_i~0_3) (= v_~t6_st~0_4 0)) InVars {~t6_i~0=v_~t6_i~0_3} OutVars{~t6_st~0=v_~t6_st~0_4, ~t6_i~0=v_~t6_i~0_3} AuxVars[] AssignedVars[~t6_st~0] 51056#L481-1 [3652] L481-1-->L660-1: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 51229#L660-1 [3654] L660-1-->L665-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 50733#L665-1 [3655] L665-1-->L670-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 50734#L670-1 [3658] L670-1-->L675-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 50825#L675-1 [3659] L675-1-->L680-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 50826#L680-1 [3661] L680-1-->L685-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 51066#L685-1 [3663] L685-1-->L690-1: Formula: (< 0 v_~T6_E~0_4) InVars {~T6_E~0=v_~T6_E~0_4} OutVars{~T6_E~0=v_~T6_E~0_4} AuxVars[] AssignedVars[] 51067#L690-1 [3665] L690-1-->L695-1: Formula: (> v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 50945#L695-1 [3668] L695-1-->L700-1: Formula: (> v_~E_2~0_6 0) InVars {~E_2~0=v_~E_2~0_6} OutVars{~E_2~0=v_~E_2~0_6} AuxVars[] AssignedVars[] 50946#L700-1 [3670] L700-1-->L705-1: Formula: (> v_~E_3~0_6 0) InVars {~E_3~0=v_~E_3~0_6} OutVars{~E_3~0=v_~E_3~0_6} AuxVars[] AssignedVars[] 51198#L705-1 [3672] L705-1-->L710-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 50888#L710-1 [3674] L710-1-->L715-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 50889#L715-1 [3675] L715-1-->L720-1: Formula: (> v_~E_6~0_4 0) InVars {~E_6~0=v_~E_6~0_4} OutVars{~E_6~0=v_~E_6~0_4} AuxVars[] AssignedVars[] 50768#L720-1 [2412] L720-1-->L310: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_7, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_4|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_4|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_7, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_4, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_4, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_2|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_2|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_4|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_4|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_7, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_2|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_4} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 50769#L310 [3678] L310-->L310-2: Formula: (< v_~m_pc~0_5 1) InVars {~m_pc~0=v_~m_pc~0_5} OutVars{~m_pc~0=v_~m_pc~0_5} AuxVars[] AssignedVars[] 50918#L310-2 [2805] L310-2-->L321: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_11 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 50916#L321 [4267] L321-->L815: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 50917#L815 [2976] L815-->L815-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_12) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} AuxVars[] AssignedVars[] 51193#L815-2 [2961] L815-2-->L329: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 51120#L329 [3683] L329-->L329-2: Formula: (< v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 51121#L329-2 [2861] L329-2-->L340: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 51118#L340 [4268] L340-->L823: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 51119#L823 [3234] L823-->L823-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} AuxVars[] AssignedVars[] 51307#L823-2 [3235] L823-2-->L348: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_4|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 51284#L348 [3690] L348-->L348-2: Formula: (< v_~t2_pc~0_5 1) InVars {~t2_pc~0=v_~t2_pc~0_5} OutVars{~t2_pc~0=v_~t2_pc~0_5} AuxVars[] AssignedVars[] 51286#L348-2 [3153] L348-2-->L359: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 51283#L359 [4269] L359-->L831: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 50895#L831 [2537] L831-->L831-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} AuxVars[] AssignedVars[] 50883#L831-2 [2520] L831-2-->L367: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_4|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 50821#L367 [3695] L367-->L367-2: Formula: (> 1 v_~t3_pc~0_5) InVars {~t3_pc~0=v_~t3_pc~0_5} OutVars{~t3_pc~0=v_~t3_pc~0_5} AuxVars[] AssignedVars[] 50799#L367-2 [2438] L367-2-->L378: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 50800#L378 [4270] L378-->L839: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 50820#L839 [2791] L839-->L839-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} AuxVars[] AssignedVars[] 51080#L839-2 [2794] L839-2-->L386: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_7, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 50994#L386 [3702] L386-->L386-2: Formula: (< v_~t4_pc~0_5 1) InVars {~t4_pc~0=v_~t4_pc~0_5} OutVars{~t4_pc~0=v_~t4_pc~0_5} AuxVars[] AssignedVars[] 50995#L386-2 [2680] L386-2-->L397: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 50992#L397 [4271] L397-->L847: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 50993#L847 [3084] L847-->L847-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} AuxVars[] AssignedVars[] 51238#L847-2 [3064] L847-2-->L405: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_4|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 51239#L405 [3708] L405-->L405-2: Formula: (> 1 v_~t5_pc~0_5) InVars {~t5_pc~0=v_~t5_pc~0_5} OutVars{~t5_pc~0=v_~t5_pc~0_5} AuxVars[] AssignedVars[] 51147#L405-2 [2940] L405-2-->L416: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 51179#L416 [4272] L416-->L855: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 51249#L855 [3711] L855-->L855-2: Formula: (and (> v_ULTIMATE.start_activate_threads_~tmp___4~0_11 0) (= v_~t5_st~0_7 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_11} OutVars{~t5_st~0=v_~t5_st~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_11} AuxVars[] AssignedVars[~t5_st~0] 51250#L855-2 [3093] L855-2-->L424: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_4|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 50866#L424 [3714] L424-->L424-2: Formula: (> v_~t6_pc~0_5 1) InVars {~t6_pc~0=v_~t6_pc~0_5} OutVars{~t6_pc~0=v_~t6_pc~0_5} AuxVars[] AssignedVars[] 50867#L424-2 [2503] L424-2-->L435: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 50865#L435 [4273] L435-->L863: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___5~0_49 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_28|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_28|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 50784#L863 [2425] L863-->L863-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___5~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} AuxVars[] AssignedVars[] 50757#L863-2 [3720] L863-2-->L733-1: Formula: (< v_~M_E~0_15 1) InVars {~M_E~0=v_~M_E~0_15} OutVars{~M_E~0=v_~M_E~0_15} AuxVars[] AssignedVars[] 50758#L733-1 [3722] L733-1-->L738-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 51195#L738-1 [3723] L738-1-->L743-1: Formula: (< 1 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 50886#L743-1 [3726] L743-1-->L748-1: Formula: (< 1 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 50887#L748-1 [3728] L748-1-->L753-1: Formula: (> v_~T4_E~0_10 1) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 50762#L753-1 [3729] L753-1-->L758-1: Formula: (< 1 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 50763#L758-1 [3732] L758-1-->L763-1: Formula: (< v_~T6_E~0_10 1) InVars {~T6_E~0=v_~T6_E~0_10} OutVars{~T6_E~0=v_~T6_E~0_10} AuxVars[] AssignedVars[] 50837#L763-1 [3733] L763-1-->L768-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 50838#L768-1 [3736] L768-1-->L773-1: Formula: (< 1 v_~E_2~0_14) InVars {~E_2~0=v_~E_2~0_14} OutVars{~E_2~0=v_~E_2~0_14} AuxVars[] AssignedVars[] 51059#L773-1 [3737] L773-1-->L778-1: Formula: (< 1 v_~E_3~0_14) InVars {~E_3~0=v_~E_3~0_14} OutVars{~E_3~0=v_~E_3~0_14} AuxVars[] AssignedVars[] 51060#L778-1 [3740] L778-1-->L783-1: Formula: (< 1 v_~E_4~0_14) InVars {~E_4~0=v_~E_4~0_14} OutVars{~E_4~0=v_~E_4~0_14} AuxVars[] AssignedVars[] 50939#L783-1 [3741] L783-1-->L788-1: Formula: (< 1 v_~E_5~0_14) InVars {~E_5~0=v_~E_5~0_14} OutVars{~E_5~0=v_~E_5~0_14} AuxVars[] AssignedVars[] 50940#L788-1 [3744] L788-1-->L1014-1: Formula: (< 1 v_~E_6~0_14) InVars {~E_6~0=v_~E_6~0_14} OutVars{~E_6~0=v_~E_6~0_14} AuxVars[] AssignedVars[] 50776#L1014-1 [2020-06-22 00:13:23,364 INFO L796 eck$LassoCheckResult]: Loop: 50776#L1014-1 [4274] L1014-1-->L635: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp_ndt_7~0=v_ULTIMATE.start_eval_~tmp_ndt_7~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp_ndt_7~0] 50739#L635 [4275] L635-->L494: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_37} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 51143#L494 [2876] L494-->L531: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21 1) (= v_~m_st~0_8 0)) InVars {~m_st~0=v_~m_st~0_8} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21, ~m_st~0=v_~m_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 50809#L531 [4276] L531-->L546: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 51046#L546 [4278] L546-->L660-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 51289#L660-2 [3747] L660-2-->L660-4: Formula: (> v_~M_E~0_30 0) InVars {~M_E~0=v_~M_E~0_30} OutVars{~M_E~0=v_~M_E~0_30} AuxVars[] AssignedVars[] 53670#L660-4 [3058] L660-4-->L665-3: Formula: (and (= v_~T1_E~0_11 1) (= v_~T1_E~0_12 0)) InVars {~T1_E~0=v_~T1_E~0_12} OutVars{~T1_E~0=v_~T1_E~0_11} AuxVars[] AssignedVars[~T1_E~0] 53669#L665-3 [3756] L665-3-->L670-3: Formula: (< 0 v_~T2_E~0_13) InVars {~T2_E~0=v_~T2_E~0_13} OutVars{~T2_E~0=v_~T2_E~0_13} AuxVars[] AssignedVars[] 53668#L670-3 [3762] L670-3-->L675-3: Formula: (< 0 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 53667#L675-3 [3768] L675-3-->L680-3: Formula: (> v_~T4_E~0_13 0) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 53665#L680-3 [3776] L680-3-->L685-3: Formula: (< 0 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 53652#L685-3 [3785] L685-3-->L690-3: Formula: (> v_~T6_E~0_13 0) InVars {~T6_E~0=v_~T6_E~0_13} OutVars{~T6_E~0=v_~T6_E~0_13} AuxVars[] AssignedVars[] 53651#L690-3 [3795] L690-3-->L695-3: Formula: (< 0 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 53650#L695-3 [3805] L695-3-->L700-3: Formula: (< 0 v_~E_2~0_31) InVars {~E_2~0=v_~E_2~0_31} OutVars{~E_2~0=v_~E_2~0_31} AuxVars[] AssignedVars[] 53649#L700-3 [3818] L700-3-->L705-3: Formula: (< 0 v_~E_3~0_31) InVars {~E_3~0=v_~E_3~0_31} OutVars{~E_3~0=v_~E_3~0_31} AuxVars[] AssignedVars[] 53601#L705-3 [2688] L705-3-->L710-3: Formula: (and (= v_~E_4~0_29 1) (= 0 v_~E_4~0_30)) InVars {~E_4~0=v_~E_4~0_30} OutVars{~E_4~0=v_~E_4~0_29} AuxVars[] AssignedVars[~E_4~0] 53598#L710-3 [3844] L710-3-->L715-3: Formula: (< 0 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 53574#L715-3 [3854] L715-3-->L720-3: Formula: (< 0 v_~E_6~0_31) InVars {~E_6~0=v_~E_6~0_31} OutVars{~E_6~0=v_~E_6~0_31} AuxVars[] AssignedVars[] 53573#L720-3 [2388] L720-3-->L310-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_43, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_43, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_25|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_25|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_25|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_43, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_43, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_43, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_25|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_25|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_25|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_25|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_43, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_25|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_43, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_43} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 51068#L310-21 [3870] L310-21-->L310-23: Formula: (< v_~m_pc~0_24 1) InVars {~m_pc~0=v_~m_pc~0_24} OutVars{~m_pc~0=v_~m_pc~0_24} AuxVars[] AssignedVars[] 51069#L310-23 [2785] L310-23-->L321-7: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_47 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_47} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 53592#L321-7 [4303] L321-7-->L815-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 53593#L815-21 [2667] L815-21-->L815-23: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_48) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_48} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_48} AuxVars[] AssignedVars[] 53586#L815-23 [2638] L815-23-->L329-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 53587#L329-21 [3911] L329-21-->L329-23: Formula: (< v_~t1_pc~0_24 1) InVars {~t1_pc~0=v_~t1_pc~0_24} OutVars{~t1_pc~0=v_~t1_pc~0_24} AuxVars[] AssignedVars[] 53239#L329-23 [3052] L329-23-->L340-7: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 53581#L340-7 [4310] L340-7-->L823-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 53578#L823-21 [2931] L823-21-->L823-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} AuxVars[] AssignedVars[] 53579#L823-23 [2934] L823-23-->L348-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_25|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 53622#L348-21 [3953] L348-21-->L348-23: Formula: (> 1 v_~t2_pc~0_24) InVars {~t2_pc~0=v_~t2_pc~0_24} OutVars{~t2_pc~0=v_~t2_pc~0_24} AuxVars[] AssignedVars[] 53621#L348-23 [3319] L348-23-->L359-7: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 53620#L359-7 [4317] L359-7-->L831-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 50857#L831-21 [2490] L831-21-->L831-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} AuxVars[] AssignedVars[] 50858#L831-23 [3197] L831-23-->L367-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_25|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 50764#L367-21 [3995] L367-21-->L367-23: Formula: (> v_~t3_pc~0_24 1) InVars {~t3_pc~0=v_~t3_pc~0_24} OutVars{~t3_pc~0=v_~t3_pc~0_24} AuxVars[] AssignedVars[] 50766#L367-23 [2385] L367-23-->L378-7: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 50790#L378-7 [4324] L378-7-->L839-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 50791#L839-21 [4023] L839-21-->L839-23: Formula: (and (= v_~t3_st~0_21 0) (> v_ULTIMATE.start_activate_threads_~tmp___2~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} OutVars{~t3_st~0=v_~t3_st~0_21, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} AuxVars[] AssignedVars[~t3_st~0] 51023#L839-23 [2722] L839-23-->L386-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_49, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 50941#L386-21 [4038] L386-21-->L386-23: Formula: (> 1 v_~t4_pc~0_24) InVars {~t4_pc~0=v_~t4_pc~0_24} OutVars{~t4_pc~0=v_~t4_pc~0_24} AuxVars[] AssignedVars[] 50942#L386-23 [2623] L386-23-->L397-7: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 53702#L397-7 [4331] L397-7-->L847-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 53700#L847-21 [4065] L847-21-->L847-23: Formula: (and (= v_~t4_st~0_22 0) (< v_ULTIMATE.start_activate_threads_~tmp___3~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47, ~t4_st~0=v_~t4_st~0_22} AuxVars[] AssignedVars[~t4_st~0] 53698#L847-23 [2983] L847-23-->L405-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_25|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 53696#L405-21 [4080] L405-21-->L405-23: Formula: (> v_~t5_pc~0_24 1) InVars {~t5_pc~0=v_~t5_pc~0_24} OutVars{~t5_pc~0=v_~t5_pc~0_24} AuxVars[] AssignedVars[] 53693#L405-23 [2891] L405-23-->L416-7: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 53691#L416-7 [4338] L416-7-->L855-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 53689#L855-21 [3251] L855-21-->L855-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} AuxVars[] AssignedVars[] 53688#L855-23 [3257] L855-23-->L424-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_25|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 53685#L424-21 [4121] L424-21-->L424-23: Formula: (< 1 v_~t6_pc~0_24) InVars {~t6_pc~0=v_~t6_pc~0_24} OutVars{~t6_pc~0=v_~t6_pc~0_24} AuxVars[] AssignedVars[] 51292#L424-23 [3177] L424-23-->L435-7: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 50851#L435-7 [4340] L435-7-->L863-21: Formula: (and (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___5~0_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_35|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_41|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 50852#L863-21 [4135] L863-21-->L863-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___5~0_47 0) (= v_~t6_st~0_22 0)) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} OutVars{~t6_st~0=v_~t6_st~0_22, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} AuxVars[] AssignedVars[~t6_st~0] 50903#L863-23 [4137] L863-23-->L733-3: Formula: (< v_~M_E~0_35 1) InVars {~M_E~0=v_~M_E~0_35} OutVars{~M_E~0=v_~M_E~0_35} AuxVars[] AssignedVars[] 53503#L733-3 [3184] L733-3-->L738-3: Formula: (and (= v_~T1_E~0_15 1) (= v_~T1_E~0_14 2)) InVars {~T1_E~0=v_~T1_E~0_15} OutVars{~T1_E~0=v_~T1_E~0_14} AuxVars[] AssignedVars[~T1_E~0] 53502#L738-3 [4142] L738-3-->L743-3: Formula: (< 1 v_~T2_E~0_16) InVars {~T2_E~0=v_~T2_E~0_16} OutVars{~T2_E~0=v_~T2_E~0_16} AuxVars[] AssignedVars[] 53501#L743-3 [4143] L743-3-->L748-3: Formula: (< 1 v_~T3_E~0_16) InVars {~T3_E~0=v_~T3_E~0_16} OutVars{~T3_E~0=v_~T3_E~0_16} AuxVars[] AssignedVars[] 53499#L748-3 [4145] L748-3-->L753-3: Formula: (> v_~T4_E~0_16 1) InVars {~T4_E~0=v_~T4_E~0_16} OutVars{~T4_E~0=v_~T4_E~0_16} AuxVars[] AssignedVars[] 53497#L753-3 [4148] L753-3-->L758-3: Formula: (< 1 v_~T5_E~0_16) InVars {~T5_E~0=v_~T5_E~0_16} OutVars{~T5_E~0=v_~T5_E~0_16} AuxVars[] AssignedVars[] 53495#L758-3 [4149] L758-3-->L763-3: Formula: (> v_~T6_E~0_16 1) InVars {~T6_E~0=v_~T6_E~0_16} OutVars{~T6_E~0=v_~T6_E~0_16} AuxVars[] AssignedVars[] 53493#L763-3 [4151] L763-3-->L768-3: Formula: (< 1 v_~E_1~0_36) InVars {~E_1~0=v_~E_1~0_36} OutVars{~E_1~0=v_~E_1~0_36} AuxVars[] AssignedVars[] 53491#L768-3 [4154] L768-3-->L773-3: Formula: (< 1 v_~E_2~0_36) InVars {~E_2~0=v_~E_2~0_36} OutVars{~E_2~0=v_~E_2~0_36} AuxVars[] AssignedVars[] 53489#L773-3 [4156] L773-3-->L778-3: Formula: (< 1 v_~E_3~0_36) InVars {~E_3~0=v_~E_3~0_36} OutVars{~E_3~0=v_~E_3~0_36} AuxVars[] AssignedVars[] 53487#L778-3 [3308] L778-3-->L783-3: Formula: (and (= 1 v_~E_4~0_35) (= v_~E_4~0_34 2)) InVars {~E_4~0=v_~E_4~0_35} OutVars{~E_4~0=v_~E_4~0_34} AuxVars[] AssignedVars[~E_4~0] 53485#L783-3 [4160] L783-3-->L788-3: Formula: (< 1 v_~E_5~0_36) InVars {~E_5~0=v_~E_5~0_36} OutVars{~E_5~0=v_~E_5~0_36} AuxVars[] AssignedVars[] 53483#L788-3 [4162] L788-3-->L793-3: Formula: (< 1 v_~E_6~0_36) InVars {~E_6~0=v_~E_6~0_36} OutVars{~E_6~0=v_~E_6~0_36} AuxVars[] AssignedVars[] 53481#L793-3 [2966] L793-3-->L494-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_30} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 51144#L494-1 [2878] L494-1-->L531-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33 1) (= 0 v_~m_st~0_21)) InVars {~m_st~0=v_~m_st~0_21} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33, ~m_st~0=v_~m_st~0_21} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 50811#L531-1 [4341] L531-1-->L1033: Formula: (and (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp~3] 51047#L1033 [4169] L1033-->L1033-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_6) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} AuxVars[] AssignedVars[] 50779#L1033-1 [2919] L1033-1-->L494-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_3|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_6, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_exists_runnable_thread_~__retres1~7, ULTIMATE.start_stop_simulation_#res] 51145#L494-2 [2882] L494-2-->L531-2: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9 1) (= v_~m_st~0_6 0)) InVars {~m_st~0=v_~m_st~0_6} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9, ~m_st~0=v_~m_st~0_6} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 50815#L531-2 [4343] L531-2-->L988: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 51054#L988 [3240] L988-->L995: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 50775#L995 [4354] L995-->L1014-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_6|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_#t~ret17, ULTIMATE.start_stop_simulation_#res] 50776#L1014-1 [2020-06-22 00:13:23,365 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:23,365 INFO L82 PathProgramCache]: Analyzing trace with hash 428260447, now seen corresponding path program 1 times [2020-06-22 00:13:23,365 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:23,365 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:23,366 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:23,366 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2020-06-22 00:13:23,366 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:23,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:23,405 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:23,406 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:23,406 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2020-06-22 00:13:23,406 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-06-22 00:13:23,406 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:23,406 INFO L82 PathProgramCache]: Analyzing trace with hash 1733948449, now seen corresponding path program 1 times [2020-06-22 00:13:23,406 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:23,406 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:23,407 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:23,407 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:23,407 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:23,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:23,440 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:23,441 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:23,441 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2020-06-22 00:13:23,441 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-06-22 00:13:23,441 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2020-06-22 00:13:23,441 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2020-06-22 00:13:23,442 INFO L87 Difference]: Start difference. First operand 3093 states and 5308 transitions. cyclomatic complexity: 2216 Second operand 6 states. [2020-06-22 00:13:25,402 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-06-22 00:13:25,402 INFO L93 Difference]: Finished difference Result 8639 states and 15025 transitions. [2020-06-22 00:13:25,403 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2020-06-22 00:13:25,403 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8639 states and 15025 transitions. [2020-06-22 00:13:25,436 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 8566 [2020-06-22 00:13:25,462 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8639 states to 8639 states and 15025 transitions. [2020-06-22 00:13:25,462 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8639 [2020-06-22 00:13:25,468 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8639 [2020-06-22 00:13:25,469 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8639 states and 15025 transitions. [2020-06-22 00:13:25,476 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-06-22 00:13:25,476 INFO L706 BuchiCegarLoop]: Abstraction has 8639 states and 15025 transitions. [2020-06-22 00:13:25,481 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8639 states and 15025 transitions. [2020-06-22 00:13:25,535 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8639 to 3101. [2020-06-22 00:13:25,536 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3101 states. [2020-06-22 00:13:25,541 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3101 states to 3101 states and 5271 transitions. [2020-06-22 00:13:25,541 INFO L729 BuchiCegarLoop]: Abstraction has 3101 states and 5271 transitions. [2020-06-22 00:13:25,541 INFO L609 BuchiCegarLoop]: Abstraction has 3101 states and 5271 transitions. [2020-06-22 00:13:25,541 INFO L442 BuchiCegarLoop]: ======== Iteration 29============ [2020-06-22 00:13:25,541 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3101 states and 5271 transitions. [2020-06-22 00:13:25,548 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3028 [2020-06-22 00:13:25,548 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-06-22 00:13:25,549 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-06-22 00:13:25,550 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:25,550 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:25,551 INFO L794 eck$LassoCheckResult]: Stem: 62988#ULTIMATE.startENTRY [4266] ULTIMATE.startENTRY-->L444: Formula: (and (= 1 v_~t6_i~0_7) (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~M_E~0_37 2) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 0 v_~t6_pc~0_26) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_6~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= v_~T6_E~0_18 2) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~t6_st~0_24) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t6_pc~0=v_~t6_pc~0_26, ~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~T6_E~0=v_~T6_E~0_18, ~M_E~0=v_~M_E~0_37, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ~T4_E~0=v_~T4_E~0_18, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_4|, ~t6_i~0=v_~t6_i~0_7, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ULTIMATE.start_main_~__retres1~8=v_ULTIMATE.start_main_~__retres1~8_6, ~T2_E~0=v_~T2_E~0_18, ~t6_st~0=v_~t6_st~0_24, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_6~0=v_~E_6~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t6_pc~0, ~t5_i~0, ~t1_pc~0, ~t5_st~0, ~T6_E~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ~T4_E~0, ULTIMATE.start_start_simulation_#t~ret17, ~t6_i~0, ~t2_st~0, ~t2_pc~0, ULTIMATE.start_main_~__retres1~8, ~T2_E~0, ~t6_st~0, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_6~0, ULTIMATE.start_main_#res, ~E_2~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 62577#L444 [2453] L444-->L451-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 62578#L451-1 [3030] L451-1-->L456-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 62673#L456-1 [2574] L456-1-->L461-1: Formula: (and (= v_~t2_st~0_2 0) (= 1 v_~t2_i~0_3)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_2} AuxVars[] AssignedVars[~t2_st~0] 62674#L461-1 [2880] L461-1-->L466-1: Formula: (and (= v_~t3_st~0_3 0) (= v_~t3_i~0_3 1)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_3, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 62582#L466-1 [2457] L466-1-->L471-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 62583#L471-1 [3209] L471-1-->L476-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 62826#L476-1 [2761] L476-1-->L481-1: Formula: (and (= 1 v_~t6_i~0_3) (= v_~t6_st~0_4 0)) InVars {~t6_i~0=v_~t6_i~0_3} OutVars{~t6_st~0=v_~t6_st~0_4, ~t6_i~0=v_~t6_i~0_3} AuxVars[] AssignedVars[~t6_st~0] 62827#L481-1 [3652] L481-1-->L660-1: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 63009#L660-1 [3654] L660-1-->L665-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 62493#L665-1 [3655] L665-1-->L670-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 62494#L670-1 [3658] L670-1-->L675-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 62589#L675-1 [3659] L675-1-->L680-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 62590#L680-1 [3661] L680-1-->L685-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 62838#L685-1 [3663] L685-1-->L690-1: Formula: (< 0 v_~T6_E~0_4) InVars {~T6_E~0=v_~T6_E~0_4} OutVars{~T6_E~0=v_~T6_E~0_4} AuxVars[] AssignedVars[] 62839#L690-1 [3665] L690-1-->L695-1: Formula: (> v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 62715#L695-1 [3668] L695-1-->L700-1: Formula: (> v_~E_2~0_6 0) InVars {~E_2~0=v_~E_2~0_6} OutVars{~E_2~0=v_~E_2~0_6} AuxVars[] AssignedVars[] 62716#L700-1 [3670] L700-1-->L705-1: Formula: (> v_~E_3~0_6 0) InVars {~E_3~0=v_~E_3~0_6} OutVars{~E_3~0=v_~E_3~0_6} AuxVars[] AssignedVars[] 62971#L705-1 [3672] L705-1-->L710-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 62652#L710-1 [3674] L710-1-->L715-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 62653#L715-1 [3675] L715-1-->L720-1: Formula: (> v_~E_6~0_4 0) InVars {~E_6~0=v_~E_6~0_4} OutVars{~E_6~0=v_~E_6~0_4} AuxVars[] AssignedVars[] 62530#L720-1 [2412] L720-1-->L310: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_7, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_4|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_4|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_7, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_4, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_4, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_2|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_2|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_4|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_4|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_7, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_2|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_4} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 62531#L310 [3678] L310-->L310-2: Formula: (< v_~m_pc~0_5 1) InVars {~m_pc~0=v_~m_pc~0_5} OutVars{~m_pc~0=v_~m_pc~0_5} AuxVars[] AssignedVars[] 62688#L310-2 [2805] L310-2-->L321: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_11 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 62683#L321 [4267] L321-->L815: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 62684#L815 [2976] L815-->L815-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_12) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} AuxVars[] AssignedVars[] 62966#L815-2 [2961] L815-2-->L329: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 62890#L329 [3683] L329-->L329-2: Formula: (< v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 62891#L329-2 [2861] L329-2-->L340: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 62886#L340 [4268] L340-->L823: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 62887#L823 [3234] L823-->L823-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} AuxVars[] AssignedVars[] 63092#L823-2 [3235] L823-2-->L348: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_4|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 63067#L348 [3690] L348-->L348-2: Formula: (< v_~t2_pc~0_5 1) InVars {~t2_pc~0=v_~t2_pc~0_5} OutVars{~t2_pc~0=v_~t2_pc~0_5} AuxVars[] AssignedVars[] 63069#L348-2 [3153] L348-2-->L359: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 63064#L359 [4269] L359-->L831: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 62661#L831 [2537] L831-->L831-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} AuxVars[] AssignedVars[] 62647#L831-2 [2520] L831-2-->L367: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_4|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 62585#L367 [3695] L367-->L367-2: Formula: (> 1 v_~t3_pc~0_5) InVars {~t3_pc~0=v_~t3_pc~0_5} OutVars{~t3_pc~0=v_~t3_pc~0_5} AuxVars[] AssignedVars[] 62563#L367-2 [2438] L367-2-->L378: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 62564#L378 [4270] L378-->L839: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 62584#L839 [2791] L839-->L839-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} AuxVars[] AssignedVars[] 62848#L839-2 [2794] L839-2-->L386: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_7, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 62762#L386 [3702] L386-->L386-2: Formula: (< v_~t4_pc~0_5 1) InVars {~t4_pc~0=v_~t4_pc~0_5} OutVars{~t4_pc~0=v_~t4_pc~0_5} AuxVars[] AssignedVars[] 62763#L386-2 [2680] L386-2-->L397: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 62760#L397 [4271] L397-->L847: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 62761#L847 [3084] L847-->L847-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} AuxVars[] AssignedVars[] 63019#L847-2 [3064] L847-2-->L405: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_4|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 63020#L405 [3708] L405-->L405-2: Formula: (> 1 v_~t5_pc~0_5) InVars {~t5_pc~0=v_~t5_pc~0_5} OutVars{~t5_pc~0=v_~t5_pc~0_5} AuxVars[] AssignedVars[] 62916#L405-2 [2940] L405-2-->L416: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 62953#L416 [4272] L416-->L855: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 63031#L855 [3091] L855-->L855-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_12} AuxVars[] AssignedVars[] 63032#L855-2 [3093] L855-2-->L424: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_4|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 62630#L424 [3714] L424-->L424-2: Formula: (> v_~t6_pc~0_5 1) InVars {~t6_pc~0=v_~t6_pc~0_5} OutVars{~t6_pc~0=v_~t6_pc~0_5} AuxVars[] AssignedVars[] 62631#L424-2 [2503] L424-2-->L435: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 62627#L435 [4273] L435-->L863: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___5~0_49 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_28|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_28|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 62545#L863 [2425] L863-->L863-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___5~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} AuxVars[] AssignedVars[] 62516#L863-2 [3720] L863-2-->L733-1: Formula: (< v_~M_E~0_15 1) InVars {~M_E~0=v_~M_E~0_15} OutVars{~M_E~0=v_~M_E~0_15} AuxVars[] AssignedVars[] 62517#L733-1 [3722] L733-1-->L738-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 62969#L738-1 [3723] L738-1-->L743-1: Formula: (< 1 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 62650#L743-1 [3726] L743-1-->L748-1: Formula: (< 1 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 62651#L748-1 [3728] L748-1-->L753-1: Formula: (> v_~T4_E~0_10 1) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 62524#L753-1 [3729] L753-1-->L758-1: Formula: (< 1 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 62525#L758-1 [3732] L758-1-->L763-1: Formula: (< v_~T6_E~0_10 1) InVars {~T6_E~0=v_~T6_E~0_10} OutVars{~T6_E~0=v_~T6_E~0_10} AuxVars[] AssignedVars[] 62601#L763-1 [3733] L763-1-->L768-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 62602#L768-1 [3736] L768-1-->L773-1: Formula: (< 1 v_~E_2~0_14) InVars {~E_2~0=v_~E_2~0_14} OutVars{~E_2~0=v_~E_2~0_14} AuxVars[] AssignedVars[] 62830#L773-1 [3737] L773-1-->L778-1: Formula: (< 1 v_~E_3~0_14) InVars {~E_3~0=v_~E_3~0_14} OutVars{~E_3~0=v_~E_3~0_14} AuxVars[] AssignedVars[] 62831#L778-1 [3740] L778-1-->L783-1: Formula: (< 1 v_~E_4~0_14) InVars {~E_4~0=v_~E_4~0_14} OutVars{~E_4~0=v_~E_4~0_14} AuxVars[] AssignedVars[] 62707#L783-1 [3741] L783-1-->L788-1: Formula: (< 1 v_~E_5~0_14) InVars {~E_5~0=v_~E_5~0_14} OutVars{~E_5~0=v_~E_5~0_14} AuxVars[] AssignedVars[] 62708#L788-1 [3744] L788-1-->L1014-1: Formula: (< 1 v_~E_6~0_14) InVars {~E_6~0=v_~E_6~0_14} OutVars{~E_6~0=v_~E_6~0_14} AuxVars[] AssignedVars[] 63076#L1014-1 [2020-06-22 00:13:25,552 INFO L796 eck$LassoCheckResult]: Loop: 63076#L1014-1 [4274] L1014-1-->L635: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp_ndt_7~0=v_ULTIMATE.start_eval_~tmp_ndt_7~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp_ndt_7~0] 63531#L635 [4275] L635-->L494: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_37} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 63526#L494 [2876] L494-->L531: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21 1) (= v_~m_st~0_8 0)) InVars {~m_st~0=v_~m_st~0_8} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21, ~m_st~0=v_~m_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 63515#L531 [4276] L531-->L546: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 63510#L546 [4278] L546-->L660-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 63511#L660-2 [3747] L660-2-->L660-4: Formula: (> v_~M_E~0_30 0) InVars {~M_E~0=v_~M_E~0_30} OutVars{~M_E~0=v_~M_E~0_30} AuxVars[] AssignedVars[] 64956#L660-4 [3058] L660-4-->L665-3: Formula: (and (= v_~T1_E~0_11 1) (= v_~T1_E~0_12 0)) InVars {~T1_E~0=v_~T1_E~0_12} OutVars{~T1_E~0=v_~T1_E~0_11} AuxVars[] AssignedVars[~T1_E~0] 64955#L665-3 [3756] L665-3-->L670-3: Formula: (< 0 v_~T2_E~0_13) InVars {~T2_E~0=v_~T2_E~0_13} OutVars{~T2_E~0=v_~T2_E~0_13} AuxVars[] AssignedVars[] 64954#L670-3 [3762] L670-3-->L675-3: Formula: (< 0 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 64953#L675-3 [3768] L675-3-->L680-3: Formula: (> v_~T4_E~0_13 0) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 64952#L680-3 [3776] L680-3-->L685-3: Formula: (< 0 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 64951#L685-3 [3785] L685-3-->L690-3: Formula: (> v_~T6_E~0_13 0) InVars {~T6_E~0=v_~T6_E~0_13} OutVars{~T6_E~0=v_~T6_E~0_13} AuxVars[] AssignedVars[] 64950#L690-3 [3795] L690-3-->L695-3: Formula: (< 0 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 64949#L695-3 [3805] L695-3-->L700-3: Formula: (< 0 v_~E_2~0_31) InVars {~E_2~0=v_~E_2~0_31} OutVars{~E_2~0=v_~E_2~0_31} AuxVars[] AssignedVars[] 64948#L700-3 [3818] L700-3-->L705-3: Formula: (< 0 v_~E_3~0_31) InVars {~E_3~0=v_~E_3~0_31} OutVars{~E_3~0=v_~E_3~0_31} AuxVars[] AssignedVars[] 64947#L705-3 [2688] L705-3-->L710-3: Formula: (and (= v_~E_4~0_29 1) (= 0 v_~E_4~0_30)) InVars {~E_4~0=v_~E_4~0_30} OutVars{~E_4~0=v_~E_4~0_29} AuxVars[] AssignedVars[~E_4~0] 64946#L710-3 [3844] L710-3-->L715-3: Formula: (< 0 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 64945#L715-3 [3854] L715-3-->L720-3: Formula: (< 0 v_~E_6~0_31) InVars {~E_6~0=v_~E_6~0_31} OutVars{~E_6~0=v_~E_6~0_31} AuxVars[] AssignedVars[] 64944#L720-3 [2388] L720-3-->L310-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_43, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_43, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_25|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_25|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_25|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_43, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_43, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_43, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_25|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_25|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_25|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_25|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_43, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_25|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_43, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_43} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 64942#L310-21 [3870] L310-21-->L310-23: Formula: (< v_~m_pc~0_24 1) InVars {~m_pc~0=v_~m_pc~0_24} OutVars{~m_pc~0=v_~m_pc~0_24} AuxVars[] AssignedVars[] 64938#L310-23 [2785] L310-23-->L321-7: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_47 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_47} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 64937#L321-7 [4303] L321-7-->L815-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 64936#L815-21 [2667] L815-21-->L815-23: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_48) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_48} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_48} AuxVars[] AssignedVars[] 64935#L815-23 [2638] L815-23-->L329-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 64934#L329-21 [3911] L329-21-->L329-23: Formula: (< v_~t1_pc~0_24 1) InVars {~t1_pc~0=v_~t1_pc~0_24} OutVars{~t1_pc~0=v_~t1_pc~0_24} AuxVars[] AssignedVars[] 63380#L329-23 [3052] L329-23-->L340-7: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 64933#L340-7 [4310] L340-7-->L823-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 64932#L823-21 [2931] L823-21-->L823-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} AuxVars[] AssignedVars[] 64931#L823-23 [2934] L823-23-->L348-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_25|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 64929#L348-21 [3953] L348-21-->L348-23: Formula: (> 1 v_~t2_pc~0_24) InVars {~t2_pc~0=v_~t2_pc~0_24} OutVars{~t2_pc~0=v_~t2_pc~0_24} AuxVars[] AssignedVars[] 64928#L348-23 [3319] L348-23-->L359-7: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 64927#L359-7 [4317] L359-7-->L831-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 64926#L831-21 [2490] L831-21-->L831-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} AuxVars[] AssignedVars[] 64925#L831-23 [3197] L831-23-->L367-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_25|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 64924#L367-21 [3995] L367-21-->L367-23: Formula: (> v_~t3_pc~0_24 1) InVars {~t3_pc~0=v_~t3_pc~0_24} OutVars{~t3_pc~0=v_~t3_pc~0_24} AuxVars[] AssignedVars[] 64922#L367-23 [2385] L367-23-->L378-7: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 64921#L378-7 [4324] L378-7-->L839-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 64920#L839-21 [4023] L839-21-->L839-23: Formula: (and (= v_~t3_st~0_21 0) (> v_ULTIMATE.start_activate_threads_~tmp___2~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} OutVars{~t3_st~0=v_~t3_st~0_21, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} AuxVars[] AssignedVars[~t3_st~0] 64919#L839-23 [2722] L839-23-->L386-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_49, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 63714#L386-21 [4038] L386-21-->L386-23: Formula: (> 1 v_~t4_pc~0_24) InVars {~t4_pc~0=v_~t4_pc~0_24} OutVars{~t4_pc~0=v_~t4_pc~0_24} AuxVars[] AssignedVars[] 63706#L386-23 [2623] L386-23-->L397-7: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 63698#L397-7 [4331] L397-7-->L847-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 63690#L847-21 [4065] L847-21-->L847-23: Formula: (and (= v_~t4_st~0_22 0) (< v_ULTIMATE.start_activate_threads_~tmp___3~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47, ~t4_st~0=v_~t4_st~0_22} AuxVars[] AssignedVars[~t4_st~0] 63689#L847-23 [2983] L847-23-->L405-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_25|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 63687#L405-21 [4080] L405-21-->L405-23: Formula: (> v_~t5_pc~0_24 1) InVars {~t5_pc~0=v_~t5_pc~0_24} OutVars{~t5_pc~0=v_~t5_pc~0_24} AuxVars[] AssignedVars[] 63686#L405-23 [2891] L405-23-->L416-7: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 63685#L416-7 [4338] L416-7-->L855-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 63684#L855-21 [3251] L855-21-->L855-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} AuxVars[] AssignedVars[] 63683#L855-23 [3257] L855-23-->L424-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_25|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 63681#L424-21 [4121] L424-21-->L424-23: Formula: (< 1 v_~t6_pc~0_24) InVars {~t6_pc~0=v_~t6_pc~0_24} OutVars{~t6_pc~0=v_~t6_pc~0_24} AuxVars[] AssignedVars[] 63680#L424-23 [3177] L424-23-->L435-7: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 63679#L435-7 [4340] L435-7-->L863-21: Formula: (and (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___5~0_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_35|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_41|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 63678#L863-21 [4135] L863-21-->L863-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___5~0_47 0) (= v_~t6_st~0_22 0)) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} OutVars{~t6_st~0=v_~t6_st~0_22, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} AuxVars[] AssignedVars[~t6_st~0] 63677#L863-23 [4137] L863-23-->L733-3: Formula: (< v_~M_E~0_35 1) InVars {~M_E~0=v_~M_E~0_35} OutVars{~M_E~0=v_~M_E~0_35} AuxVars[] AssignedVars[] 63676#L733-3 [3184] L733-3-->L738-3: Formula: (and (= v_~T1_E~0_15 1) (= v_~T1_E~0_14 2)) InVars {~T1_E~0=v_~T1_E~0_15} OutVars{~T1_E~0=v_~T1_E~0_14} AuxVars[] AssignedVars[~T1_E~0] 63675#L738-3 [4142] L738-3-->L743-3: Formula: (< 1 v_~T2_E~0_16) InVars {~T2_E~0=v_~T2_E~0_16} OutVars{~T2_E~0=v_~T2_E~0_16} AuxVars[] AssignedVars[] 63674#L743-3 [4143] L743-3-->L748-3: Formula: (< 1 v_~T3_E~0_16) InVars {~T3_E~0=v_~T3_E~0_16} OutVars{~T3_E~0=v_~T3_E~0_16} AuxVars[] AssignedVars[] 63673#L748-3 [4145] L748-3-->L753-3: Formula: (> v_~T4_E~0_16 1) InVars {~T4_E~0=v_~T4_E~0_16} OutVars{~T4_E~0=v_~T4_E~0_16} AuxVars[] AssignedVars[] 63672#L753-3 [4148] L753-3-->L758-3: Formula: (< 1 v_~T5_E~0_16) InVars {~T5_E~0=v_~T5_E~0_16} OutVars{~T5_E~0=v_~T5_E~0_16} AuxVars[] AssignedVars[] 63671#L758-3 [4149] L758-3-->L763-3: Formula: (> v_~T6_E~0_16 1) InVars {~T6_E~0=v_~T6_E~0_16} OutVars{~T6_E~0=v_~T6_E~0_16} AuxVars[] AssignedVars[] 63670#L763-3 [4151] L763-3-->L768-3: Formula: (< 1 v_~E_1~0_36) InVars {~E_1~0=v_~E_1~0_36} OutVars{~E_1~0=v_~E_1~0_36} AuxVars[] AssignedVars[] 63669#L768-3 [4154] L768-3-->L773-3: Formula: (< 1 v_~E_2~0_36) InVars {~E_2~0=v_~E_2~0_36} OutVars{~E_2~0=v_~E_2~0_36} AuxVars[] AssignedVars[] 63668#L773-3 [4156] L773-3-->L778-3: Formula: (< 1 v_~E_3~0_36) InVars {~E_3~0=v_~E_3~0_36} OutVars{~E_3~0=v_~E_3~0_36} AuxVars[] AssignedVars[] 63667#L778-3 [3308] L778-3-->L783-3: Formula: (and (= 1 v_~E_4~0_35) (= v_~E_4~0_34 2)) InVars {~E_4~0=v_~E_4~0_35} OutVars{~E_4~0=v_~E_4~0_34} AuxVars[] AssignedVars[~E_4~0] 63665#L783-3 [4160] L783-3-->L788-3: Formula: (< 1 v_~E_5~0_36) InVars {~E_5~0=v_~E_5~0_36} OutVars{~E_5~0=v_~E_5~0_36} AuxVars[] AssignedVars[] 63663#L788-3 [4162] L788-3-->L793-3: Formula: (< 1 v_~E_6~0_36) InVars {~E_6~0=v_~E_6~0_36} OutVars{~E_6~0=v_~E_6~0_36} AuxVars[] AssignedVars[] 63661#L793-3 [2966] L793-3-->L494-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_30} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 63647#L494-1 [2878] L494-1-->L531-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33 1) (= 0 v_~m_st~0_21)) InVars {~m_st~0=v_~m_st~0_21} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33, ~m_st~0=v_~m_st~0_21} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 63635#L531-1 [4341] L531-1-->L1033: Formula: (and (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp~3] 63579#L1033 [4169] L1033-->L1033-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_6) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} AuxVars[] AssignedVars[] 63576#L1033-1 [2919] L1033-1-->L494-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_3|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_6, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_exists_runnable_thread_~__retres1~7, ULTIMATE.start_stop_simulation_#res] 63568#L494-2 [2882] L494-2-->L531-2: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9 1) (= v_~m_st~0_6 0)) InVars {~m_st~0=v_~m_st~0_6} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9, ~m_st~0=v_~m_st~0_6} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 63564#L531-2 [4343] L531-2-->L988: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 63561#L988 [3240] L988-->L995: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 63541#L995 [4354] L995-->L1014-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_6|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_#t~ret17, ULTIMATE.start_stop_simulation_#res] 63076#L1014-1 [2020-06-22 00:13:25,552 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:25,553 INFO L82 PathProgramCache]: Analyzing trace with hash 14810355, now seen corresponding path program 1 times [2020-06-22 00:13:25,553 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:25,553 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:25,554 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:25,554 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:25,554 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:25,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:25,576 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:25,577 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:25,577 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-06-22 00:13:25,577 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-06-22 00:13:25,577 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:25,577 INFO L82 PathProgramCache]: Analyzing trace with hash 1733948449, now seen corresponding path program 2 times [2020-06-22 00:13:25,577 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:25,578 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:25,578 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:25,578 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:25,578 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:25,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:25,613 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:25,613 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:25,613 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2020-06-22 00:13:25,613 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-06-22 00:13:25,614 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-06-22 00:13:25,614 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-06-22 00:13:25,614 INFO L87 Difference]: Start difference. First operand 3101 states and 5271 transitions. cyclomatic complexity: 2171 Second operand 3 states. [2020-06-22 00:13:26,329 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-06-22 00:13:26,329 INFO L93 Difference]: Finished difference Result 6076 states and 10242 transitions. [2020-06-22 00:13:26,329 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-06-22 00:13:26,329 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6076 states and 10242 transitions. [2020-06-22 00:13:26,348 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 6004 [2020-06-22 00:13:26,366 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6076 states to 6076 states and 10242 transitions. [2020-06-22 00:13:26,366 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6076 [2020-06-22 00:13:26,371 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6076 [2020-06-22 00:13:26,371 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6076 states and 10242 transitions. [2020-06-22 00:13:26,376 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-06-22 00:13:26,376 INFO L706 BuchiCegarLoop]: Abstraction has 6076 states and 10242 transitions. [2020-06-22 00:13:26,379 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6076 states and 10242 transitions. [2020-06-22 00:13:26,430 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6076 to 6068. [2020-06-22 00:13:26,430 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6068 states. [2020-06-22 00:13:26,441 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6068 states to 6068 states and 10234 transitions. [2020-06-22 00:13:26,441 INFO L729 BuchiCegarLoop]: Abstraction has 6068 states and 10234 transitions. [2020-06-22 00:13:26,441 INFO L609 BuchiCegarLoop]: Abstraction has 6068 states and 10234 transitions. [2020-06-22 00:13:26,441 INFO L442 BuchiCegarLoop]: ======== Iteration 30============ [2020-06-22 00:13:26,442 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6068 states and 10234 transitions. [2020-06-22 00:13:26,458 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5996 [2020-06-22 00:13:26,459 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-06-22 00:13:26,459 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-06-22 00:13:26,461 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:26,461 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:26,462 INFO L794 eck$LassoCheckResult]: Stem: 72160#ULTIMATE.startENTRY [4266] ULTIMATE.startENTRY-->L444: Formula: (and (= 1 v_~t6_i~0_7) (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~M_E~0_37 2) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 0 v_~t6_pc~0_26) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_6~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= v_~T6_E~0_18 2) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~t6_st~0_24) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t6_pc~0=v_~t6_pc~0_26, ~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~T6_E~0=v_~T6_E~0_18, ~M_E~0=v_~M_E~0_37, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ~T4_E~0=v_~T4_E~0_18, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_4|, ~t6_i~0=v_~t6_i~0_7, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ULTIMATE.start_main_~__retres1~8=v_ULTIMATE.start_main_~__retres1~8_6, ~T2_E~0=v_~T2_E~0_18, ~t6_st~0=v_~t6_st~0_24, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_6~0=v_~E_6~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t6_pc~0, ~t5_i~0, ~t1_pc~0, ~t5_st~0, ~T6_E~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ~T4_E~0, ULTIMATE.start_start_simulation_#t~ret17, ~t6_i~0, ~t2_st~0, ~t2_pc~0, ULTIMATE.start_main_~__retres1~8, ~T2_E~0, ~t6_st~0, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_6~0, ULTIMATE.start_main_#res, ~E_2~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 71759#L444 [2453] L444-->L451-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 71760#L451-1 [3030] L451-1-->L456-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 71848#L456-1 [2574] L456-1-->L461-1: Formula: (and (= v_~t2_st~0_2 0) (= 1 v_~t2_i~0_3)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_2} AuxVars[] AssignedVars[~t2_st~0] 71849#L461-1 [2880] L461-1-->L466-1: Formula: (and (= v_~t3_st~0_3 0) (= v_~t3_i~0_3 1)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_3, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 71764#L466-1 [2457] L466-1-->L471-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 71765#L471-1 [3209] L471-1-->L476-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 72003#L476-1 [2761] L476-1-->L481-1: Formula: (and (= 1 v_~t6_i~0_3) (= v_~t6_st~0_4 0)) InVars {~t6_i~0=v_~t6_i~0_3} OutVars{~t6_st~0=v_~t6_st~0_4, ~t6_i~0=v_~t6_i~0_3} AuxVars[] AssignedVars[~t6_st~0] 72004#L481-1 [3652] L481-1-->L660-1: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 72176#L660-1 [3654] L660-1-->L665-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 71678#L665-1 [3655] L665-1-->L670-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 71679#L670-1 [3658] L670-1-->L675-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 71771#L675-1 [3659] L675-1-->L680-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 71772#L680-1 [3661] L680-1-->L685-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 72014#L685-1 [3663] L685-1-->L690-1: Formula: (< 0 v_~T6_E~0_4) InVars {~T6_E~0=v_~T6_E~0_4} OutVars{~T6_E~0=v_~T6_E~0_4} AuxVars[] AssignedVars[] 72015#L690-1 [3665] L690-1-->L695-1: Formula: (> v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 71888#L695-1 [3668] L695-1-->L700-1: Formula: (> v_~E_2~0_6 0) InVars {~E_2~0=v_~E_2~0_6} OutVars{~E_2~0=v_~E_2~0_6} AuxVars[] AssignedVars[] 71889#L700-1 [3670] L700-1-->L705-1: Formula: (> v_~E_3~0_6 0) InVars {~E_3~0=v_~E_3~0_6} OutVars{~E_3~0=v_~E_3~0_6} AuxVars[] AssignedVars[] 72143#L705-1 [3672] L705-1-->L710-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 71831#L710-1 [3674] L710-1-->L715-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 71832#L715-1 [3675] L715-1-->L720-1: Formula: (> v_~E_6~0_4 0) InVars {~E_6~0=v_~E_6~0_4} OutVars{~E_6~0=v_~E_6~0_4} AuxVars[] AssignedVars[] 71716#L720-1 [2412] L720-1-->L310: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_7, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_4|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_4|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_7, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_4, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_4, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_2|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_2|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_4|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_4|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_7, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_2|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_4} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 71717#L310 [3678] L310-->L310-2: Formula: (< v_~m_pc~0_5 1) InVars {~m_pc~0=v_~m_pc~0_5} OutVars{~m_pc~0=v_~m_pc~0_5} AuxVars[] AssignedVars[] 71861#L310-2 [2805] L310-2-->L321: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_11 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 71856#L321 [4267] L321-->L815: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 71857#L815 [2976] L815-->L815-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_12) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} AuxVars[] AssignedVars[] 72139#L815-2 [2961] L815-2-->L329: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 72070#L329 [3683] L329-->L329-2: Formula: (< v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 72071#L329-2 [2861] L329-2-->L340: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 72066#L340 [4268] L340-->L823: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 72067#L823 [3234] L823-->L823-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} AuxVars[] AssignedVars[] 72259#L823-2 [3235] L823-2-->L348: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_4|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 72234#L348 [3690] L348-->L348-2: Formula: (< v_~t2_pc~0_5 1) InVars {~t2_pc~0=v_~t2_pc~0_5} OutVars{~t2_pc~0=v_~t2_pc~0_5} AuxVars[] AssignedVars[] 72236#L348-2 [3153] L348-2-->L359: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 72231#L359 [4269] L359-->L831: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 71838#L831 [2537] L831-->L831-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} AuxVars[] AssignedVars[] 71826#L831-2 [2520] L831-2-->L367: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_4|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 71767#L367 [3695] L367-->L367-2: Formula: (> 1 v_~t3_pc~0_5) InVars {~t3_pc~0=v_~t3_pc~0_5} OutVars{~t3_pc~0=v_~t3_pc~0_5} AuxVars[] AssignedVars[] 71745#L367-2 [2438] L367-2-->L378: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 71746#L378 [4270] L378-->L839: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 71766#L839 [2791] L839-->L839-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} AuxVars[] AssignedVars[] 72026#L839-2 [2794] L839-2-->L386: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_7, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 71936#L386 [3702] L386-->L386-2: Formula: (< v_~t4_pc~0_5 1) InVars {~t4_pc~0=v_~t4_pc~0_5} OutVars{~t4_pc~0=v_~t4_pc~0_5} AuxVars[] AssignedVars[] 71937#L386-2 [2680] L386-2-->L397: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 71934#L397 [4271] L397-->L847: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 71935#L847 [3084] L847-->L847-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} AuxVars[] AssignedVars[] 72181#L847-2 [3064] L847-2-->L405: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_4|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 72182#L405 [3708] L405-->L405-2: Formula: (> 1 v_~t5_pc~0_5) InVars {~t5_pc~0=v_~t5_pc~0_5} OutVars{~t5_pc~0=v_~t5_pc~0_5} AuxVars[] AssignedVars[] 72097#L405-2 [2940] L405-2-->L416: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 72126#L416 [4272] L416-->L855: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 72194#L855 [3091] L855-->L855-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_12} AuxVars[] AssignedVars[] 72195#L855-2 [3093] L855-2-->L424: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_4|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 71809#L424 [3713] L424-->L424-2: Formula: (< v_~t6_pc~0_5 1) InVars {~t6_pc~0=v_~t6_pc~0_5} OutVars{~t6_pc~0=v_~t6_pc~0_5} AuxVars[] AssignedVars[] 71810#L424-2 [2503] L424-2-->L435: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 71806#L435 [4273] L435-->L863: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___5~0_49 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_28|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_28|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 71730#L863 [2425] L863-->L863-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___5~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} AuxVars[] AssignedVars[] 71702#L863-2 [3720] L863-2-->L733-1: Formula: (< v_~M_E~0_15 1) InVars {~M_E~0=v_~M_E~0_15} OutVars{~M_E~0=v_~M_E~0_15} AuxVars[] AssignedVars[] 71703#L733-1 [3722] L733-1-->L738-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 72141#L738-1 [3723] L738-1-->L743-1: Formula: (< 1 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 71829#L743-1 [3726] L743-1-->L748-1: Formula: (< 1 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 71830#L748-1 [3728] L748-1-->L753-1: Formula: (> v_~T4_E~0_10 1) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 71710#L753-1 [3729] L753-1-->L758-1: Formula: (< 1 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 71711#L758-1 [3732] L758-1-->L763-1: Formula: (< v_~T6_E~0_10 1) InVars {~T6_E~0=v_~T6_E~0_10} OutVars{~T6_E~0=v_~T6_E~0_10} AuxVars[] AssignedVars[] 71783#L763-1 [3733] L763-1-->L768-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 71784#L768-1 [3736] L768-1-->L773-1: Formula: (< 1 v_~E_2~0_14) InVars {~E_2~0=v_~E_2~0_14} OutVars{~E_2~0=v_~E_2~0_14} AuxVars[] AssignedVars[] 72007#L773-1 [3737] L773-1-->L778-1: Formula: (< 1 v_~E_3~0_14) InVars {~E_3~0=v_~E_3~0_14} OutVars{~E_3~0=v_~E_3~0_14} AuxVars[] AssignedVars[] 72008#L778-1 [3740] L778-1-->L783-1: Formula: (< 1 v_~E_4~0_14) InVars {~E_4~0=v_~E_4~0_14} OutVars{~E_4~0=v_~E_4~0_14} AuxVars[] AssignedVars[] 71880#L783-1 [3741] L783-1-->L788-1: Formula: (< 1 v_~E_5~0_14) InVars {~E_5~0=v_~E_5~0_14} OutVars{~E_5~0=v_~E_5~0_14} AuxVars[] AssignedVars[] 71881#L788-1 [3744] L788-1-->L1014-1: Formula: (< 1 v_~E_6~0_14) InVars {~E_6~0=v_~E_6~0_14} OutVars{~E_6~0=v_~E_6~0_14} AuxVars[] AssignedVars[] 71724#L1014-1 [2020-06-22 00:13:26,463 INFO L796 eck$LassoCheckResult]: Loop: 71724#L1014-1 [4274] L1014-1-->L635: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp_ndt_7~0=v_ULTIMATE.start_eval_~tmp_ndt_7~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp_ndt_7~0] 71910#L635 [4275] L635-->L494: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_37} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 72093#L494 [2876] L494-->L531: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21 1) (= v_~m_st~0_8 0)) InVars {~m_st~0=v_~m_st~0_8} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21, ~m_st~0=v_~m_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 71755#L531 [4276] L531-->L546: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 71995#L546 [4278] L546-->L660-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 72243#L660-2 [3747] L660-2-->L660-4: Formula: (> v_~M_E~0_30 0) InVars {~M_E~0=v_~M_E~0_30} OutVars{~M_E~0=v_~M_E~0_30} AuxVars[] AssignedVars[] 77538#L660-4 [3058] L660-4-->L665-3: Formula: (and (= v_~T1_E~0_11 1) (= v_~T1_E~0_12 0)) InVars {~T1_E~0=v_~T1_E~0_12} OutVars{~T1_E~0=v_~T1_E~0_11} AuxVars[] AssignedVars[~T1_E~0] 77535#L665-3 [3756] L665-3-->L670-3: Formula: (< 0 v_~T2_E~0_13) InVars {~T2_E~0=v_~T2_E~0_13} OutVars{~T2_E~0=v_~T2_E~0_13} AuxVars[] AssignedVars[] 77533#L670-3 [3762] L670-3-->L675-3: Formula: (< 0 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 77532#L675-3 [3768] L675-3-->L680-3: Formula: (> v_~T4_E~0_13 0) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 77529#L680-3 [3776] L680-3-->L685-3: Formula: (< 0 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 77527#L685-3 [3785] L685-3-->L690-3: Formula: (> v_~T6_E~0_13 0) InVars {~T6_E~0=v_~T6_E~0_13} OutVars{~T6_E~0=v_~T6_E~0_13} AuxVars[] AssignedVars[] 77525#L690-3 [3795] L690-3-->L695-3: Formula: (< 0 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 77523#L695-3 [3805] L695-3-->L700-3: Formula: (< 0 v_~E_2~0_31) InVars {~E_2~0=v_~E_2~0_31} OutVars{~E_2~0=v_~E_2~0_31} AuxVars[] AssignedVars[] 77521#L700-3 [3818] L700-3-->L705-3: Formula: (< 0 v_~E_3~0_31) InVars {~E_3~0=v_~E_3~0_31} OutVars{~E_3~0=v_~E_3~0_31} AuxVars[] AssignedVars[] 77520#L705-3 [2688] L705-3-->L710-3: Formula: (and (= v_~E_4~0_29 1) (= 0 v_~E_4~0_30)) InVars {~E_4~0=v_~E_4~0_30} OutVars{~E_4~0=v_~E_4~0_29} AuxVars[] AssignedVars[~E_4~0] 77517#L710-3 [3844] L710-3-->L715-3: Formula: (< 0 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 77515#L715-3 [3854] L715-3-->L720-3: Formula: (< 0 v_~E_6~0_31) InVars {~E_6~0=v_~E_6~0_31} OutVars{~E_6~0=v_~E_6~0_31} AuxVars[] AssignedVars[] 77513#L720-3 [2388] L720-3-->L310-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_43, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_43, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_25|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_25|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_25|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_43, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_43, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_43, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_25|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_25|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_25|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_25|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_43, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_25|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_43, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_43} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 77512#L310-21 [3870] L310-21-->L310-23: Formula: (< v_~m_pc~0_24 1) InVars {~m_pc~0=v_~m_pc~0_24} OutVars{~m_pc~0=v_~m_pc~0_24} AuxVars[] AssignedVars[] 77151#L310-23 [2785] L310-23-->L321-7: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_47 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_47} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 77506#L321-7 [4303] L321-7-->L815-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 77505#L815-21 [2667] L815-21-->L815-23: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_48) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_48} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_48} AuxVars[] AssignedVars[] 77504#L815-23 [2638] L815-23-->L329-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 77238#L329-21 [3911] L329-21-->L329-23: Formula: (< v_~t1_pc~0_24 1) InVars {~t1_pc~0=v_~t1_pc~0_24} OutVars{~t1_pc~0=v_~t1_pc~0_24} AuxVars[] AssignedVars[] 77237#L329-23 [3052] L329-23-->L340-7: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 77235#L340-7 [4310] L340-7-->L823-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 77233#L823-21 [2931] L823-21-->L823-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} AuxVars[] AssignedVars[] 77231#L823-23 [2934] L823-23-->L348-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_25|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 77227#L348-21 [3953] L348-21-->L348-23: Formula: (> 1 v_~t2_pc~0_24) InVars {~t2_pc~0=v_~t2_pc~0_24} OutVars{~t2_pc~0=v_~t2_pc~0_24} AuxVars[] AssignedVars[] 77223#L348-23 [3319] L348-23-->L359-7: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 77219#L359-7 [4317] L359-7-->L831-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 77214#L831-21 [2490] L831-21-->L831-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} AuxVars[] AssignedVars[] 77210#L831-23 [3197] L831-23-->L367-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_25|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 77206#L367-21 [3995] L367-21-->L367-23: Formula: (> v_~t3_pc~0_24 1) InVars {~t3_pc~0=v_~t3_pc~0_24} OutVars{~t3_pc~0=v_~t3_pc~0_24} AuxVars[] AssignedVars[] 71680#L367-23 [2385] L367-23-->L378-7: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 71681#L378-7 [4324] L378-7-->L839-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 71737#L839-21 [4023] L839-21-->L839-23: Formula: (and (= v_~t3_st~0_21 0) (> v_ULTIMATE.start_activate_threads_~tmp___2~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} OutVars{~t3_st~0=v_~t3_st~0_21, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} AuxVars[] AssignedVars[~t3_st~0] 71965#L839-23 [2722] L839-23-->L386-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_49, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 71884#L386-21 [4038] L386-21-->L386-23: Formula: (> 1 v_~t4_pc~0_24) InVars {~t4_pc~0=v_~t4_pc~0_24} OutVars{~t4_pc~0=v_~t4_pc~0_24} AuxVars[] AssignedVars[] 71885#L386-23 [2623] L386-23-->L397-7: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 71890#L397-7 [4331] L397-7-->L847-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 71925#L847-21 [4065] L847-21-->L847-23: Formula: (and (= v_~t4_st~0_22 0) (< v_ULTIMATE.start_activate_threads_~tmp___3~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47, ~t4_st~0=v_~t4_st~0_22} AuxVars[] AssignedVars[~t4_st~0] 72150#L847-23 [2983] L847-23-->L405-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_25|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 72106#L405-21 [4080] L405-21-->L405-23: Formula: (> v_~t5_pc~0_24 1) InVars {~t5_pc~0=v_~t5_pc~0_24} OutVars{~t5_pc~0=v_~t5_pc~0_24} AuxVars[] AssignedVars[] 72092#L405-23 [2891] L405-23-->L416-7: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 72100#L416-7 [4338] L416-7-->L855-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 72113#L855-21 [3251] L855-21-->L855-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} AuxVars[] AssignedVars[] 72262#L855-23 [3257] L855-23-->L424-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_25|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 72246#L424-21 [4122] L424-21-->L424-23: Formula: (> 1 v_~t6_pc~0_24) InVars {~t6_pc~0=v_~t6_pc~0_24} OutVars{~t6_pc~0=v_~t6_pc~0_24} AuxVars[] AssignedVars[] 72247#L424-23 [3177] L424-23-->L435-7: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 71796#L435-7 [4340] L435-7-->L863-21: Formula: (and (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___5~0_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_35|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_41|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 71797#L863-21 [4135] L863-21-->L863-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___5~0_47 0) (= v_~t6_st~0_22 0)) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} OutVars{~t6_st~0=v_~t6_st~0_22, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} AuxVars[] AssignedVars[~t6_st~0] 71839#L863-23 [4137] L863-23-->L733-3: Formula: (< v_~M_E~0_35 1) InVars {~M_E~0=v_~M_E~0_35} OutVars{~M_E~0=v_~M_E~0_35} AuxVars[] AssignedVars[] 71840#L733-3 [3184] L733-3-->L738-3: Formula: (and (= v_~T1_E~0_15 1) (= v_~T1_E~0_14 2)) InVars {~T1_E~0=v_~T1_E~0_15} OutVars{~T1_E~0=v_~T1_E~0_14} AuxVars[] AssignedVars[~T1_E~0] 72144#L738-3 [4142] L738-3-->L743-3: Formula: (< 1 v_~T2_E~0_16) InVars {~T2_E~0=v_~T2_E~0_16} OutVars{~T2_E~0=v_~T2_E~0_16} AuxVars[] AssignedVars[] 71818#L743-3 [4143] L743-3-->L748-3: Formula: (< 1 v_~T3_E~0_16) InVars {~T3_E~0=v_~T3_E~0_16} OutVars{~T3_E~0=v_~T3_E~0_16} AuxVars[] AssignedVars[] 71819#L748-3 [4145] L748-3-->L753-3: Formula: (> v_~T4_E~0_16 1) InVars {~T4_E~0=v_~T4_E~0_16} OutVars{~T4_E~0=v_~T4_E~0_16} AuxVars[] AssignedVars[] 71676#L753-3 [4148] L753-3-->L758-3: Formula: (< 1 v_~T5_E~0_16) InVars {~T5_E~0=v_~T5_E~0_16} OutVars{~T5_E~0=v_~T5_E~0_16} AuxVars[] AssignedVars[] 71677#L758-3 [4149] L758-3-->L763-3: Formula: (> v_~T6_E~0_16 1) InVars {~T6_E~0=v_~T6_E~0_16} OutVars{~T6_E~0=v_~T6_E~0_16} AuxVars[] AssignedVars[] 71769#L763-3 [4151] L763-3-->L768-3: Formula: (< 1 v_~E_1~0_36) InVars {~E_1~0=v_~E_1~0_36} OutVars{~E_1~0=v_~E_1~0_36} AuxVars[] AssignedVars[] 71770#L768-3 [4154] L768-3-->L773-3: Formula: (< 1 v_~E_2~0_36) InVars {~E_2~0=v_~E_2~0_36} OutVars{~E_2~0=v_~E_2~0_36} AuxVars[] AssignedVars[] 72012#L773-3 [4156] L773-3-->L778-3: Formula: (< 1 v_~E_3~0_36) InVars {~E_3~0=v_~E_3~0_36} OutVars{~E_3~0=v_~E_3~0_36} AuxVars[] AssignedVars[] 72013#L778-3 [3308] L778-3-->L783-3: Formula: (and (= 1 v_~E_4~0_35) (= v_~E_4~0_34 2)) InVars {~E_4~0=v_~E_4~0_35} OutVars{~E_4~0=v_~E_4~0_34} AuxVars[] AssignedVars[~E_4~0] 71886#L783-3 [4160] L783-3-->L788-3: Formula: (< 1 v_~E_5~0_36) InVars {~E_5~0=v_~E_5~0_36} OutVars{~E_5~0=v_~E_5~0_36} AuxVars[] AssignedVars[] 71887#L788-3 [4162] L788-3-->L793-3: Formula: (< 1 v_~E_6~0_36) InVars {~E_6~0=v_~E_6~0_36} OutVars{~E_6~0=v_~E_6~0_36} AuxVars[] AssignedVars[] 72142#L793-3 [2966] L793-3-->L494-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_30} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 72094#L494-1 [2878] L494-1-->L531-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33 1) (= 0 v_~m_st~0_21)) InVars {~m_st~0=v_~m_st~0_21} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33, ~m_st~0=v_~m_st~0_21} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 71757#L531-1 [4341] L531-1-->L1033: Formula: (and (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp~3] 71998#L1033 [4169] L1033-->L1033-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_6) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} AuxVars[] AssignedVars[] 71727#L1033-1 [2919] L1033-1-->L494-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_3|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_6, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_exists_runnable_thread_~__retres1~7, ULTIMATE.start_stop_simulation_#res] 72095#L494-2 [2882] L494-2-->L531-2: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9 1) (= v_~m_st~0_6 0)) InVars {~m_st~0=v_~m_st~0_6} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9, ~m_st~0=v_~m_st~0_6} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 71763#L531-2 [4343] L531-2-->L988: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 72002#L988 [3240] L988-->L995: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 71723#L995 [4354] L995-->L1014-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_6|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_#t~ret17, ULTIMATE.start_stop_simulation_#res] 71724#L1014-1 [2020-06-22 00:13:26,464 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:26,464 INFO L82 PathProgramCache]: Analyzing trace with hash -1338499342, now seen corresponding path program 1 times [2020-06-22 00:13:26,464 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:26,464 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:26,465 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:26,465 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2020-06-22 00:13:26,465 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:26,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:26,498 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:26,499 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:26,499 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-06-22 00:13:26,499 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-06-22 00:13:26,499 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:26,500 INFO L82 PathProgramCache]: Analyzing trace with hash 1764968256, now seen corresponding path program 1 times [2020-06-22 00:13:26,500 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:26,500 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:26,501 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:26,501 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:26,501 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:26,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:26,523 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:26,523 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:26,523 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2020-06-22 00:13:26,524 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-06-22 00:13:26,524 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2020-06-22 00:13:26,524 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2020-06-22 00:13:26,524 INFO L87 Difference]: Start difference. First operand 6068 states and 10234 transitions. cyclomatic complexity: 4167 Second operand 4 states. [2020-06-22 00:13:26,999 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-06-22 00:13:26,999 INFO L93 Difference]: Finished difference Result 6280 states and 10346 transitions. [2020-06-22 00:13:27,000 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2020-06-22 00:13:27,000 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6280 states and 10346 transitions. [2020-06-22 00:13:27,018 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 6208 [2020-06-22 00:13:27,032 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6280 states to 6280 states and 10346 transitions. [2020-06-22 00:13:27,032 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6280 [2020-06-22 00:13:27,036 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6280 [2020-06-22 00:13:27,036 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6280 states and 10346 transitions. [2020-06-22 00:13:27,040 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-06-22 00:13:27,040 INFO L706 BuchiCegarLoop]: Abstraction has 6280 states and 10346 transitions. [2020-06-22 00:13:27,044 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6280 states and 10346 transitions. [2020-06-22 00:13:27,099 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6280 to 6280. [2020-06-22 00:13:27,099 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6280 states. [2020-06-22 00:13:27,110 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6280 states to 6280 states and 10346 transitions. [2020-06-22 00:13:27,111 INFO L729 BuchiCegarLoop]: Abstraction has 6280 states and 10346 transitions. [2020-06-22 00:13:27,111 INFO L609 BuchiCegarLoop]: Abstraction has 6280 states and 10346 transitions. [2020-06-22 00:13:27,111 INFO L442 BuchiCegarLoop]: ======== Iteration 31============ [2020-06-22 00:13:27,111 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6280 states and 10346 transitions. [2020-06-22 00:13:27,128 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 6208 [2020-06-22 00:13:27,128 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-06-22 00:13:27,128 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-06-22 00:13:27,130 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:27,130 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:27,131 INFO L794 eck$LassoCheckResult]: Stem: 84517#ULTIMATE.startENTRY [4266] ULTIMATE.startENTRY-->L444: Formula: (and (= 1 v_~t6_i~0_7) (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~M_E~0_37 2) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 0 v_~t6_pc~0_26) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_6~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= v_~T6_E~0_18 2) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~t6_st~0_24) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t6_pc~0=v_~t6_pc~0_26, ~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~T6_E~0=v_~T6_E~0_18, ~M_E~0=v_~M_E~0_37, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ~T4_E~0=v_~T4_E~0_18, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_4|, ~t6_i~0=v_~t6_i~0_7, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ULTIMATE.start_main_~__retres1~8=v_ULTIMATE.start_main_~__retres1~8_6, ~T2_E~0=v_~T2_E~0_18, ~t6_st~0=v_~t6_st~0_24, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_6~0=v_~E_6~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t6_pc~0, ~t5_i~0, ~t1_pc~0, ~t5_st~0, ~T6_E~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ~T4_E~0, ULTIMATE.start_start_simulation_#t~ret17, ~t6_i~0, ~t2_st~0, ~t2_pc~0, ULTIMATE.start_main_~__retres1~8, ~T2_E~0, ~t6_st~0, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_6~0, ULTIMATE.start_main_#res, ~E_2~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 84120#L444 [2453] L444-->L451-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 84121#L451-1 [3030] L451-1-->L456-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 84206#L456-1 [2574] L456-1-->L461-1: Formula: (and (= v_~t2_st~0_2 0) (= 1 v_~t2_i~0_3)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_2} AuxVars[] AssignedVars[~t2_st~0] 84207#L461-1 [2880] L461-1-->L466-1: Formula: (and (= v_~t3_st~0_3 0) (= v_~t3_i~0_3 1)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_3, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 84122#L466-1 [2457] L466-1-->L471-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 84123#L471-1 [3209] L471-1-->L476-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 84358#L476-1 [2761] L476-1-->L481-1: Formula: (and (= 1 v_~t6_i~0_3) (= v_~t6_st~0_4 0)) InVars {~t6_i~0=v_~t6_i~0_3} OutVars{~t6_st~0=v_~t6_st~0_4, ~t6_i~0=v_~t6_i~0_3} AuxVars[] AssignedVars[~t6_st~0] 84359#L481-1 [3652] L481-1-->L660-1: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 84534#L660-1 [3654] L660-1-->L665-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 84037#L665-1 [3655] L665-1-->L670-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 84038#L670-1 [3658] L670-1-->L675-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 84129#L675-1 [3659] L675-1-->L680-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 84130#L680-1 [3661] L680-1-->L685-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 84371#L685-1 [3663] L685-1-->L690-1: Formula: (< 0 v_~T6_E~0_4) InVars {~T6_E~0=v_~T6_E~0_4} OutVars{~T6_E~0=v_~T6_E~0_4} AuxVars[] AssignedVars[] 84372#L690-1 [3665] L690-1-->L695-1: Formula: (> v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 84246#L695-1 [3668] L695-1-->L700-1: Formula: (> v_~E_2~0_6 0) InVars {~E_2~0=v_~E_2~0_6} OutVars{~E_2~0=v_~E_2~0_6} AuxVars[] AssignedVars[] 84247#L700-1 [3670] L700-1-->L705-1: Formula: (> v_~E_3~0_6 0) InVars {~E_3~0=v_~E_3~0_6} OutVars{~E_3~0=v_~E_3~0_6} AuxVars[] AssignedVars[] 84500#L705-1 [3672] L705-1-->L710-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 84189#L710-1 [3674] L710-1-->L715-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 84190#L715-1 [3675] L715-1-->L720-1: Formula: (> v_~E_6~0_4 0) InVars {~E_6~0=v_~E_6~0_4} OutVars{~E_6~0=v_~E_6~0_4} AuxVars[] AssignedVars[] 84071#L720-1 [2412] L720-1-->L310: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_7, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_4|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_4|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_7, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_4, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_4, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_2|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_2|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_4|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_4|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_7, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_2|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_4} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 84072#L310 [3678] L310-->L310-2: Formula: (< v_~m_pc~0_5 1) InVars {~m_pc~0=v_~m_pc~0_5} OutVars{~m_pc~0=v_~m_pc~0_5} AuxVars[] AssignedVars[] 84219#L310-2 [2805] L310-2-->L321: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_11 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 84217#L321 [4267] L321-->L815: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 84218#L815 [2976] L815-->L815-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_12) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} AuxVars[] AssignedVars[] 84496#L815-2 [2961] L815-2-->L329: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 84422#L329 [3683] L329-->L329-2: Formula: (< v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 84423#L329-2 [2861] L329-2-->L340: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 84420#L340 [4268] L340-->L823: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 84421#L823 [3234] L823-->L823-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} AuxVars[] AssignedVars[] 84619#L823-2 [3235] L823-2-->L348: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_4|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 84590#L348 [3690] L348-->L348-2: Formula: (< v_~t2_pc~0_5 1) InVars {~t2_pc~0=v_~t2_pc~0_5} OutVars{~t2_pc~0=v_~t2_pc~0_5} AuxVars[] AssignedVars[] 84592#L348-2 [3153] L348-2-->L359: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 84588#L359 [4269] L359-->L831: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 84196#L831 [2537] L831-->L831-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} AuxVars[] AssignedVars[] 84184#L831-2 [2520] L831-2-->L367: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_4|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 84125#L367 [3695] L367-->L367-2: Formula: (> 1 v_~t3_pc~0_5) InVars {~t3_pc~0=v_~t3_pc~0_5} OutVars{~t3_pc~0=v_~t3_pc~0_5} AuxVars[] AssignedVars[] 84103#L367-2 [2438] L367-2-->L378: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 84104#L378 [4270] L378-->L839: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 84124#L839 [2791] L839-->L839-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} AuxVars[] AssignedVars[] 84383#L839-2 [2794] L839-2-->L386: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_7, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 84296#L386 [3702] L386-->L386-2: Formula: (< v_~t4_pc~0_5 1) InVars {~t4_pc~0=v_~t4_pc~0_5} OutVars{~t4_pc~0=v_~t4_pc~0_5} AuxVars[] AssignedVars[] 84297#L386-2 [2680] L386-2-->L397: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 84294#L397 [4271] L397-->L847: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 84295#L847 [3084] L847-->L847-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} AuxVars[] AssignedVars[] 84541#L847-2 [3064] L847-2-->L405: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_4|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 84542#L405 [3708] L405-->L405-2: Formula: (> 1 v_~t5_pc~0_5) InVars {~t5_pc~0=v_~t5_pc~0_5} OutVars{~t5_pc~0=v_~t5_pc~0_5} AuxVars[] AssignedVars[] 84449#L405-2 [2940] L405-2-->L416: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 84482#L416 [4272] L416-->L855: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 84553#L855 [3091] L855-->L855-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_12} AuxVars[] AssignedVars[] 84554#L855-2 [3093] L855-2-->L424: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_4|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 84169#L424 [3713] L424-->L424-2: Formula: (< v_~t6_pc~0_5 1) InVars {~t6_pc~0=v_~t6_pc~0_5} OutVars{~t6_pc~0=v_~t6_pc~0_5} AuxVars[] AssignedVars[] 84170#L424-2 [2503] L424-2-->L435: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 84166#L435 [4273] L435-->L863: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___5~0_49 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_28|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_28|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 84087#L863 [2425] L863-->L863-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___5~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} AuxVars[] AssignedVars[] 84061#L863-2 [3719] L863-2-->L733-1: Formula: (> v_~M_E~0_15 1) InVars {~M_E~0=v_~M_E~0_15} OutVars{~M_E~0=v_~M_E~0_15} AuxVars[] AssignedVars[] 84062#L733-1 [3722] L733-1-->L738-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 84498#L738-1 [3723] L738-1-->L743-1: Formula: (< 1 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 84187#L743-1 [3726] L743-1-->L748-1: Formula: (< 1 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 84188#L748-1 [3728] L748-1-->L753-1: Formula: (> v_~T4_E~0_10 1) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 84066#L753-1 [3729] L753-1-->L758-1: Formula: (< 1 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 84067#L758-1 [3732] L758-1-->L763-1: Formula: (< v_~T6_E~0_10 1) InVars {~T6_E~0=v_~T6_E~0_10} OutVars{~T6_E~0=v_~T6_E~0_10} AuxVars[] AssignedVars[] 84141#L763-1 [3733] L763-1-->L768-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 84142#L768-1 [3736] L768-1-->L773-1: Formula: (< 1 v_~E_2~0_14) InVars {~E_2~0=v_~E_2~0_14} OutVars{~E_2~0=v_~E_2~0_14} AuxVars[] AssignedVars[] 84362#L773-1 [3737] L773-1-->L778-1: Formula: (< 1 v_~E_3~0_14) InVars {~E_3~0=v_~E_3~0_14} OutVars{~E_3~0=v_~E_3~0_14} AuxVars[] AssignedVars[] 84363#L778-1 [3740] L778-1-->L783-1: Formula: (< 1 v_~E_4~0_14) InVars {~E_4~0=v_~E_4~0_14} OutVars{~E_4~0=v_~E_4~0_14} AuxVars[] AssignedVars[] 84240#L783-1 [3741] L783-1-->L788-1: Formula: (< 1 v_~E_5~0_14) InVars {~E_5~0=v_~E_5~0_14} OutVars{~E_5~0=v_~E_5~0_14} AuxVars[] AssignedVars[] 84241#L788-1 [3744] L788-1-->L1014-1: Formula: (< 1 v_~E_6~0_14) InVars {~E_6~0=v_~E_6~0_14} OutVars{~E_6~0=v_~E_6~0_14} AuxVars[] AssignedVars[] 84604#L1014-1 [2020-06-22 00:13:27,132 INFO L796 eck$LassoCheckResult]: Loop: 84604#L1014-1 [4274] L1014-1-->L635: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp_ndt_7~0=v_ULTIMATE.start_eval_~tmp_ndt_7~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp_ndt_7~0] 85691#L635 [4275] L635-->L494: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_37} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 85690#L494 [2876] L494-->L531: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21 1) (= v_~m_st~0_8 0)) InVars {~m_st~0=v_~m_st~0_8} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21, ~m_st~0=v_~m_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 85683#L531 [4276] L531-->L546: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 85681#L546 [4278] L546-->L660-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 85682#L660-2 [3747] L660-2-->L660-4: Formula: (> v_~M_E~0_30 0) InVars {~M_E~0=v_~M_E~0_30} OutVars{~M_E~0=v_~M_E~0_30} AuxVars[] AssignedVars[] 90269#L660-4 [3058] L660-4-->L665-3: Formula: (and (= v_~T1_E~0_11 1) (= v_~T1_E~0_12 0)) InVars {~T1_E~0=v_~T1_E~0_12} OutVars{~T1_E~0=v_~T1_E~0_11} AuxVars[] AssignedVars[~T1_E~0] 90192#L665-3 [3756] L665-3-->L670-3: Formula: (< 0 v_~T2_E~0_13) InVars {~T2_E~0=v_~T2_E~0_13} OutVars{~T2_E~0=v_~T2_E~0_13} AuxVars[] AssignedVars[] 90173#L670-3 [3762] L670-3-->L675-3: Formula: (< 0 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 90172#L675-3 [3768] L675-3-->L680-3: Formula: (> v_~T4_E~0_13 0) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 90171#L680-3 [3776] L680-3-->L685-3: Formula: (< 0 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 90170#L685-3 [3785] L685-3-->L690-3: Formula: (> v_~T6_E~0_13 0) InVars {~T6_E~0=v_~T6_E~0_13} OutVars{~T6_E~0=v_~T6_E~0_13} AuxVars[] AssignedVars[] 90169#L690-3 [3795] L690-3-->L695-3: Formula: (< 0 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 90167#L695-3 [3805] L695-3-->L700-3: Formula: (< 0 v_~E_2~0_31) InVars {~E_2~0=v_~E_2~0_31} OutVars{~E_2~0=v_~E_2~0_31} AuxVars[] AssignedVars[] 90166#L700-3 [3818] L700-3-->L705-3: Formula: (< 0 v_~E_3~0_31) InVars {~E_3~0=v_~E_3~0_31} OutVars{~E_3~0=v_~E_3~0_31} AuxVars[] AssignedVars[] 90165#L705-3 [2688] L705-3-->L710-3: Formula: (and (= v_~E_4~0_29 1) (= 0 v_~E_4~0_30)) InVars {~E_4~0=v_~E_4~0_30} OutVars{~E_4~0=v_~E_4~0_29} AuxVars[] AssignedVars[~E_4~0] 90164#L710-3 [3844] L710-3-->L715-3: Formula: (< 0 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 90163#L715-3 [3854] L715-3-->L720-3: Formula: (< 0 v_~E_6~0_31) InVars {~E_6~0=v_~E_6~0_31} OutVars{~E_6~0=v_~E_6~0_31} AuxVars[] AssignedVars[] 90162#L720-3 [2388] L720-3-->L310-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_43, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_43, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_25|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_25|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_25|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_43, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_43, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_43, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_25|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_25|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_25|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_25|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_43, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_25|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_43, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_43} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 84373#L310-21 [3870] L310-21-->L310-23: Formula: (< v_~m_pc~0_24 1) InVars {~m_pc~0=v_~m_pc~0_24} OutVars{~m_pc~0=v_~m_pc~0_24} AuxVars[] AssignedVars[] 84374#L310-23 [2785] L310-23-->L321-7: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_47 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_47} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 90168#L321-7 [4303] L321-7-->L815-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 89850#L815-21 [2667] L815-21-->L815-23: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_48) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_48} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_48} AuxVars[] AssignedVars[] 89849#L815-23 [2638] L815-23-->L329-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 89837#L329-21 [3911] L329-21-->L329-23: Formula: (< v_~t1_pc~0_24 1) InVars {~t1_pc~0=v_~t1_pc~0_24} OutVars{~t1_pc~0=v_~t1_pc~0_24} AuxVars[] AssignedVars[] 89836#L329-23 [3052] L329-23-->L340-7: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 89835#L340-7 [4310] L340-7-->L823-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 89834#L823-21 [2931] L823-21-->L823-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} AuxVars[] AssignedVars[] 89833#L823-23 [2934] L823-23-->L348-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_25|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 89831#L348-21 [3953] L348-21-->L348-23: Formula: (> 1 v_~t2_pc~0_24) InVars {~t2_pc~0=v_~t2_pc~0_24} OutVars{~t2_pc~0=v_~t2_pc~0_24} AuxVars[] AssignedVars[] 89830#L348-23 [3319] L348-23-->L359-7: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 89829#L359-7 [4317] L359-7-->L831-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 89826#L831-21 [2490] L831-21-->L831-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} AuxVars[] AssignedVars[] 89825#L831-23 [3197] L831-23-->L367-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_25|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 89823#L367-21 [3995] L367-21-->L367-23: Formula: (> v_~t3_pc~0_24 1) InVars {~t3_pc~0=v_~t3_pc~0_24} OutVars{~t3_pc~0=v_~t3_pc~0_24} AuxVars[] AssignedVars[] 89820#L367-23 [2385] L367-23-->L378-7: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 84092#L378-7 [4324] L378-7-->L839-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 84093#L839-21 [4023] L839-21-->L839-23: Formula: (and (= v_~t3_st~0_21 0) (> v_ULTIMATE.start_activate_threads_~tmp___2~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} OutVars{~t3_st~0=v_~t3_st~0_21, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} AuxVars[] AssignedVars[~t3_st~0] 84327#L839-23 [2722] L839-23-->L386-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_49, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 84242#L386-21 [4038] L386-21-->L386-23: Formula: (> 1 v_~t4_pc~0_24) InVars {~t4_pc~0=v_~t4_pc~0_24} OutVars{~t4_pc~0=v_~t4_pc~0_24} AuxVars[] AssignedVars[] 84243#L386-23 [2623] L386-23-->L397-7: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 89403#L397-7 [4331] L397-7-->L847-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 89401#L847-21 [4065] L847-21-->L847-23: Formula: (and (= v_~t4_st~0_22 0) (< v_ULTIMATE.start_activate_threads_~tmp___3~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47, ~t4_st~0=v_~t4_st~0_22} AuxVars[] AssignedVars[~t4_st~0] 89354#L847-23 [2983] L847-23-->L405-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_25|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 89352#L405-21 [4080] L405-21-->L405-23: Formula: (> v_~t5_pc~0_24 1) InVars {~t5_pc~0=v_~t5_pc~0_24} OutVars{~t5_pc~0=v_~t5_pc~0_24} AuxVars[] AssignedVars[] 89351#L405-23 [2891] L405-23-->L416-7: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 89349#L416-7 [4338] L416-7-->L855-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 84623#L855-21 [3251] L855-21-->L855-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} AuxVars[] AssignedVars[] 84624#L855-23 [3257] L855-23-->L424-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_25|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 84627#L424-21 [4122] L424-21-->L424-23: Formula: (> 1 v_~t6_pc~0_24) InVars {~t6_pc~0=v_~t6_pc~0_24} OutVars{~t6_pc~0=v_~t6_pc~0_24} AuxVars[] AssignedVars[] 86647#L424-23 [3177] L424-23-->L435-7: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 86646#L435-7 [4340] L435-7-->L863-21: Formula: (and (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___5~0_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_35|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_41|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 86645#L863-21 [4135] L863-21-->L863-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___5~0_47 0) (= v_~t6_st~0_22 0)) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} OutVars{~t6_st~0=v_~t6_st~0_22, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} AuxVars[] AssignedVars[~t6_st~0] 86644#L863-23 [4138] L863-23-->L733-3: Formula: (> v_~M_E~0_35 1) InVars {~M_E~0=v_~M_E~0_35} OutVars{~M_E~0=v_~M_E~0_35} AuxVars[] AssignedVars[] 86640#L733-3 [3184] L733-3-->L738-3: Formula: (and (= v_~T1_E~0_15 1) (= v_~T1_E~0_14 2)) InVars {~T1_E~0=v_~T1_E~0_15} OutVars{~T1_E~0=v_~T1_E~0_14} AuxVars[] AssignedVars[~T1_E~0] 86635#L738-3 [4142] L738-3-->L743-3: Formula: (< 1 v_~T2_E~0_16) InVars {~T2_E~0=v_~T2_E~0_16} OutVars{~T2_E~0=v_~T2_E~0_16} AuxVars[] AssignedVars[] 86632#L743-3 [4143] L743-3-->L748-3: Formula: (< 1 v_~T3_E~0_16) InVars {~T3_E~0=v_~T3_E~0_16} OutVars{~T3_E~0=v_~T3_E~0_16} AuxVars[] AssignedVars[] 86627#L748-3 [4145] L748-3-->L753-3: Formula: (> v_~T4_E~0_16 1) InVars {~T4_E~0=v_~T4_E~0_16} OutVars{~T4_E~0=v_~T4_E~0_16} AuxVars[] AssignedVars[] 86625#L753-3 [4148] L753-3-->L758-3: Formula: (< 1 v_~T5_E~0_16) InVars {~T5_E~0=v_~T5_E~0_16} OutVars{~T5_E~0=v_~T5_E~0_16} AuxVars[] AssignedVars[] 86622#L758-3 [4149] L758-3-->L763-3: Formula: (> v_~T6_E~0_16 1) InVars {~T6_E~0=v_~T6_E~0_16} OutVars{~T6_E~0=v_~T6_E~0_16} AuxVars[] AssignedVars[] 86621#L763-3 [4151] L763-3-->L768-3: Formula: (< 1 v_~E_1~0_36) InVars {~E_1~0=v_~E_1~0_36} OutVars{~E_1~0=v_~E_1~0_36} AuxVars[] AssignedVars[] 86620#L768-3 [4154] L768-3-->L773-3: Formula: (< 1 v_~E_2~0_36) InVars {~E_2~0=v_~E_2~0_36} OutVars{~E_2~0=v_~E_2~0_36} AuxVars[] AssignedVars[] 86619#L773-3 [4156] L773-3-->L778-3: Formula: (< 1 v_~E_3~0_36) InVars {~E_3~0=v_~E_3~0_36} OutVars{~E_3~0=v_~E_3~0_36} AuxVars[] AssignedVars[] 85731#L778-3 [3308] L778-3-->L783-3: Formula: (and (= 1 v_~E_4~0_35) (= v_~E_4~0_34 2)) InVars {~E_4~0=v_~E_4~0_35} OutVars{~E_4~0=v_~E_4~0_34} AuxVars[] AssignedVars[~E_4~0] 85730#L783-3 [4160] L783-3-->L788-3: Formula: (< 1 v_~E_5~0_36) InVars {~E_5~0=v_~E_5~0_36} OutVars{~E_5~0=v_~E_5~0_36} AuxVars[] AssignedVars[] 85727#L788-3 [4162] L788-3-->L793-3: Formula: (< 1 v_~E_6~0_36) InVars {~E_6~0=v_~E_6~0_36} OutVars{~E_6~0=v_~E_6~0_36} AuxVars[] AssignedVars[] 85725#L793-3 [2966] L793-3-->L494-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_30} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 85723#L494-1 [2878] L494-1-->L531-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33 1) (= 0 v_~m_st~0_21)) InVars {~m_st~0=v_~m_st~0_21} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33, ~m_st~0=v_~m_st~0_21} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 85715#L531-1 [4341] L531-1-->L1033: Formula: (and (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp~3] 85713#L1033 [4169] L1033-->L1033-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_6) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} AuxVars[] AssignedVars[] 85710#L1033-1 [2919] L1033-1-->L494-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_3|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_6, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_exists_runnable_thread_~__retres1~7, ULTIMATE.start_stop_simulation_#res] 85703#L494-2 [2882] L494-2-->L531-2: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9 1) (= v_~m_st~0_6 0)) InVars {~m_st~0=v_~m_st~0_6} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9, ~m_st~0=v_~m_st~0_6} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 85700#L531-2 [4343] L531-2-->L988: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 85699#L988 [3240] L988-->L995: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 85698#L995 [4354] L995-->L1014-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_6|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_#t~ret17, ULTIMATE.start_stop_simulation_#res] 84604#L1014-1 [2020-06-22 00:13:27,132 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:27,133 INFO L82 PathProgramCache]: Analyzing trace with hash -1045096335, now seen corresponding path program 1 times [2020-06-22 00:13:27,133 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:27,133 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:27,134 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:27,134 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:27,134 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:27,139 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:27,167 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:27,167 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:27,167 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-06-22 00:13:27,168 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-06-22 00:13:27,168 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:27,168 INFO L82 PathProgramCache]: Analyzing trace with hash -273088033, now seen corresponding path program 1 times [2020-06-22 00:13:27,168 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:27,168 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:27,169 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:27,169 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:27,169 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:27,171 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:27,197 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:27,197 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:27,197 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2020-06-22 00:13:27,197 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-06-22 00:13:27,198 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2020-06-22 00:13:27,198 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2020-06-22 00:13:27,198 INFO L87 Difference]: Start difference. First operand 6280 states and 10346 transitions. cyclomatic complexity: 4067 Second operand 4 states. [2020-06-22 00:13:27,620 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-06-22 00:13:27,620 INFO L93 Difference]: Finished difference Result 6280 states and 10246 transitions. [2020-06-22 00:13:27,621 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-06-22 00:13:27,621 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6280 states and 10246 transitions. [2020-06-22 00:13:27,641 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 6208 [2020-06-22 00:13:27,654 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6280 states to 6280 states and 10246 transitions. [2020-06-22 00:13:27,654 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6280 [2020-06-22 00:13:27,658 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6280 [2020-06-22 00:13:27,658 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6280 states and 10246 transitions. [2020-06-22 00:13:27,662 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-06-22 00:13:27,663 INFO L706 BuchiCegarLoop]: Abstraction has 6280 states and 10246 transitions. [2020-06-22 00:13:27,665 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6280 states and 10246 transitions. [2020-06-22 00:13:27,714 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6280 to 6280. [2020-06-22 00:13:27,715 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6280 states. [2020-06-22 00:13:27,726 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6280 states to 6280 states and 10246 transitions. [2020-06-22 00:13:27,726 INFO L729 BuchiCegarLoop]: Abstraction has 6280 states and 10246 transitions. [2020-06-22 00:13:27,726 INFO L609 BuchiCegarLoop]: Abstraction has 6280 states and 10246 transitions. [2020-06-22 00:13:27,726 INFO L442 BuchiCegarLoop]: ======== Iteration 32============ [2020-06-22 00:13:27,726 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6280 states and 10246 transitions. [2020-06-22 00:13:27,744 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 6208 [2020-06-22 00:13:27,744 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-06-22 00:13:27,744 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-06-22 00:13:27,746 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:27,746 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:27,747 INFO L794 eck$LassoCheckResult]: Stem: 97082#ULTIMATE.startENTRY [4266] ULTIMATE.startENTRY-->L444: Formula: (and (= 1 v_~t6_i~0_7) (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~M_E~0_37 2) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 0 v_~t6_pc~0_26) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_6~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= v_~T6_E~0_18 2) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~t6_st~0_24) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t6_pc~0=v_~t6_pc~0_26, ~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~T6_E~0=v_~T6_E~0_18, ~M_E~0=v_~M_E~0_37, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ~T4_E~0=v_~T4_E~0_18, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_4|, ~t6_i~0=v_~t6_i~0_7, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ULTIMATE.start_main_~__retres1~8=v_ULTIMATE.start_main_~__retres1~8_6, ~T2_E~0=v_~T2_E~0_18, ~t6_st~0=v_~t6_st~0_24, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_6~0=v_~E_6~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t6_pc~0, ~t5_i~0, ~t1_pc~0, ~t5_st~0, ~T6_E~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ~T4_E~0, ULTIMATE.start_start_simulation_#t~ret17, ~t6_i~0, ~t2_st~0, ~t2_pc~0, ULTIMATE.start_main_~__retres1~8, ~T2_E~0, ~t6_st~0, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_6~0, ULTIMATE.start_main_#res, ~E_2~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 96685#L444 [2453] L444-->L451-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 96686#L451-1 [3030] L451-1-->L456-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 96774#L456-1 [2574] L456-1-->L461-1: Formula: (and (= v_~t2_st~0_2 0) (= 1 v_~t2_i~0_3)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_2} AuxVars[] AssignedVars[~t2_st~0] 96775#L461-1 [2880] L461-1-->L466-1: Formula: (and (= v_~t3_st~0_3 0) (= v_~t3_i~0_3 1)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_3, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 96690#L466-1 [2457] L466-1-->L471-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 96691#L471-1 [3209] L471-1-->L476-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 96928#L476-1 [2761] L476-1-->L481-1: Formula: (and (= 1 v_~t6_i~0_3) (= v_~t6_st~0_4 0)) InVars {~t6_i~0=v_~t6_i~0_3} OutVars{~t6_st~0=v_~t6_st~0_4, ~t6_i~0=v_~t6_i~0_3} AuxVars[] AssignedVars[~t6_st~0] 96929#L481-1 [3652] L481-1-->L660-1: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 97099#L660-1 [3654] L660-1-->L665-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 96604#L665-1 [3655] L665-1-->L670-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 96605#L670-1 [3658] L670-1-->L675-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 96697#L675-1 [3659] L675-1-->L680-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 96698#L680-1 [3661] L680-1-->L685-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 96940#L685-1 [3663] L685-1-->L690-1: Formula: (< 0 v_~T6_E~0_4) InVars {~T6_E~0=v_~T6_E~0_4} OutVars{~T6_E~0=v_~T6_E~0_4} AuxVars[] AssignedVars[] 96941#L690-1 [3665] L690-1-->L695-1: Formula: (> v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 96814#L695-1 [3668] L695-1-->L700-1: Formula: (> v_~E_2~0_6 0) InVars {~E_2~0=v_~E_2~0_6} OutVars{~E_2~0=v_~E_2~0_6} AuxVars[] AssignedVars[] 96815#L700-1 [3670] L700-1-->L705-1: Formula: (> v_~E_3~0_6 0) InVars {~E_3~0=v_~E_3~0_6} OutVars{~E_3~0=v_~E_3~0_6} AuxVars[] AssignedVars[] 97063#L705-1 [3672] L705-1-->L710-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 96757#L710-1 [3674] L710-1-->L715-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 96758#L715-1 [3675] L715-1-->L720-1: Formula: (> v_~E_6~0_4 0) InVars {~E_6~0=v_~E_6~0_4} OutVars{~E_6~0=v_~E_6~0_4} AuxVars[] AssignedVars[] 96640#L720-1 [2412] L720-1-->L310: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_7, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_4|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_4|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_7, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_4, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_4, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_2|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_2|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_4|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_4|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_7, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_2|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_4} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 96641#L310 [3678] L310-->L310-2: Formula: (< v_~m_pc~0_5 1) InVars {~m_pc~0=v_~m_pc~0_5} OutVars{~m_pc~0=v_~m_pc~0_5} AuxVars[] AssignedVars[] 96787#L310-2 [2805] L310-2-->L321: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_11 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 96782#L321 [4267] L321-->L815: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 96783#L815 [2976] L815-->L815-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_12) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} AuxVars[] AssignedVars[] 97059#L815-2 [2961] L815-2-->L329: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 96988#L329 [3683] L329-->L329-2: Formula: (< v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 96989#L329-2 [2861] L329-2-->L340: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 96984#L340 [4268] L340-->L823: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 96985#L823 [3234] L823-->L823-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} AuxVars[] AssignedVars[] 97184#L823-2 [3235] L823-2-->L348: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_4|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 97151#L348 [3690] L348-->L348-2: Formula: (< v_~t2_pc~0_5 1) InVars {~t2_pc~0=v_~t2_pc~0_5} OutVars{~t2_pc~0=v_~t2_pc~0_5} AuxVars[] AssignedVars[] 97153#L348-2 [3153] L348-2-->L359: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 97149#L359 [4269] L359-->L831: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 96765#L831 [2537] L831-->L831-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} AuxVars[] AssignedVars[] 96752#L831-2 [2520] L831-2-->L367: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_4|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 96693#L367 [3695] L367-->L367-2: Formula: (> 1 v_~t3_pc~0_5) InVars {~t3_pc~0=v_~t3_pc~0_5} OutVars{~t3_pc~0=v_~t3_pc~0_5} AuxVars[] AssignedVars[] 96670#L367-2 [2438] L367-2-->L378: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 96671#L378 [4270] L378-->L839: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 96692#L839 [2791] L839-->L839-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} AuxVars[] AssignedVars[] 96951#L839-2 [2794] L839-2-->L386: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_7, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 96867#L386 [3702] L386-->L386-2: Formula: (< v_~t4_pc~0_5 1) InVars {~t4_pc~0=v_~t4_pc~0_5} OutVars{~t4_pc~0=v_~t4_pc~0_5} AuxVars[] AssignedVars[] 96868#L386-2 [2680] L386-2-->L397: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 96865#L397 [4271] L397-->L847: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 96866#L847 [3084] L847-->L847-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} AuxVars[] AssignedVars[] 97106#L847-2 [3064] L847-2-->L405: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_4|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 97107#L405 [3708] L405-->L405-2: Formula: (> 1 v_~t5_pc~0_5) InVars {~t5_pc~0=v_~t5_pc~0_5} OutVars{~t5_pc~0=v_~t5_pc~0_5} AuxVars[] AssignedVars[] 97014#L405-2 [2940] L405-2-->L416: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 97046#L416 [4272] L416-->L855: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 97115#L855 [3091] L855-->L855-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_12} AuxVars[] AssignedVars[] 97116#L855-2 [3093] L855-2-->L424: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_4|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 96736#L424 [3713] L424-->L424-2: Formula: (< v_~t6_pc~0_5 1) InVars {~t6_pc~0=v_~t6_pc~0_5} OutVars{~t6_pc~0=v_~t6_pc~0_5} AuxVars[] AssignedVars[] 96737#L424-2 [2503] L424-2-->L435: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 96733#L435 [4273] L435-->L863: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___5~0_49 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_28|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_28|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 96654#L863 [2425] L863-->L863-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___5~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} AuxVars[] AssignedVars[] 96627#L863-2 [3719] L863-2-->L733-1: Formula: (> v_~M_E~0_15 1) InVars {~M_E~0=v_~M_E~0_15} OutVars{~M_E~0=v_~M_E~0_15} AuxVars[] AssignedVars[] 96628#L733-1 [3722] L733-1-->L738-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 97061#L738-1 [3723] L738-1-->L743-1: Formula: (< 1 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 96755#L743-1 [3726] L743-1-->L748-1: Formula: (< 1 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 96756#L748-1 [3728] L748-1-->L753-1: Formula: (> v_~T4_E~0_10 1) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 96635#L753-1 [3729] L753-1-->L758-1: Formula: (< 1 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 96636#L758-1 [3731] L758-1-->L763-1: Formula: (> v_~T6_E~0_10 1) InVars {~T6_E~0=v_~T6_E~0_10} OutVars{~T6_E~0=v_~T6_E~0_10} AuxVars[] AssignedVars[] 96709#L763-1 [3733] L763-1-->L768-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 96710#L768-1 [3736] L768-1-->L773-1: Formula: (< 1 v_~E_2~0_14) InVars {~E_2~0=v_~E_2~0_14} OutVars{~E_2~0=v_~E_2~0_14} AuxVars[] AssignedVars[] 96932#L773-1 [3737] L773-1-->L778-1: Formula: (< 1 v_~E_3~0_14) InVars {~E_3~0=v_~E_3~0_14} OutVars{~E_3~0=v_~E_3~0_14} AuxVars[] AssignedVars[] 96933#L778-1 [3740] L778-1-->L783-1: Formula: (< 1 v_~E_4~0_14) InVars {~E_4~0=v_~E_4~0_14} OutVars{~E_4~0=v_~E_4~0_14} AuxVars[] AssignedVars[] 96806#L783-1 [3741] L783-1-->L788-1: Formula: (< 1 v_~E_5~0_14) InVars {~E_5~0=v_~E_5~0_14} OutVars{~E_5~0=v_~E_5~0_14} AuxVars[] AssignedVars[] 96807#L788-1 [3744] L788-1-->L1014-1: Formula: (< 1 v_~E_6~0_14) InVars {~E_6~0=v_~E_6~0_14} OutVars{~E_6~0=v_~E_6~0_14} AuxVars[] AssignedVars[] 97164#L1014-1 [2020-06-22 00:13:27,748 INFO L796 eck$LassoCheckResult]: Loop: 97164#L1014-1 [4274] L1014-1-->L635: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp_ndt_7~0=v_ULTIMATE.start_eval_~tmp_ndt_7~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp_ndt_7~0] 99434#L635 [4275] L635-->L494: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_37} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 99429#L494 [2876] L494-->L531: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21 1) (= v_~m_st~0_8 0)) InVars {~m_st~0=v_~m_st~0_8} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21, ~m_st~0=v_~m_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 99421#L531 [4276] L531-->L546: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 99418#L546 [4278] L546-->L660-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 99419#L660-2 [3747] L660-2-->L660-4: Formula: (> v_~M_E~0_30 0) InVars {~M_E~0=v_~M_E~0_30} OutVars{~M_E~0=v_~M_E~0_30} AuxVars[] AssignedVars[] 102864#L660-4 [3058] L660-4-->L665-3: Formula: (and (= v_~T1_E~0_11 1) (= v_~T1_E~0_12 0)) InVars {~T1_E~0=v_~T1_E~0_12} OutVars{~T1_E~0=v_~T1_E~0_11} AuxVars[] AssignedVars[~T1_E~0] 102862#L665-3 [3756] L665-3-->L670-3: Formula: (< 0 v_~T2_E~0_13) InVars {~T2_E~0=v_~T2_E~0_13} OutVars{~T2_E~0=v_~T2_E~0_13} AuxVars[] AssignedVars[] 102860#L670-3 [3762] L670-3-->L675-3: Formula: (< 0 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 102858#L675-3 [3768] L675-3-->L680-3: Formula: (> v_~T4_E~0_13 0) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 102856#L680-3 [3776] L680-3-->L685-3: Formula: (< 0 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 102854#L685-3 [3785] L685-3-->L690-3: Formula: (> v_~T6_E~0_13 0) InVars {~T6_E~0=v_~T6_E~0_13} OutVars{~T6_E~0=v_~T6_E~0_13} AuxVars[] AssignedVars[] 102850#L690-3 [3795] L690-3-->L695-3: Formula: (< 0 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 102849#L695-3 [3805] L695-3-->L700-3: Formula: (< 0 v_~E_2~0_31) InVars {~E_2~0=v_~E_2~0_31} OutVars{~E_2~0=v_~E_2~0_31} AuxVars[] AssignedVars[] 102848#L700-3 [3818] L700-3-->L705-3: Formula: (< 0 v_~E_3~0_31) InVars {~E_3~0=v_~E_3~0_31} OutVars{~E_3~0=v_~E_3~0_31} AuxVars[] AssignedVars[] 102847#L705-3 [2688] L705-3-->L710-3: Formula: (and (= v_~E_4~0_29 1) (= 0 v_~E_4~0_30)) InVars {~E_4~0=v_~E_4~0_30} OutVars{~E_4~0=v_~E_4~0_29} AuxVars[] AssignedVars[~E_4~0] 102846#L710-3 [3844] L710-3-->L715-3: Formula: (< 0 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 102844#L715-3 [3854] L715-3-->L720-3: Formula: (< 0 v_~E_6~0_31) InVars {~E_6~0=v_~E_6~0_31} OutVars{~E_6~0=v_~E_6~0_31} AuxVars[] AssignedVars[] 102842#L720-3 [2388] L720-3-->L310-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_43, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_43, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_25|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_25|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_25|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_43, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_43, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_43, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_25|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_25|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_25|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_25|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_43, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_25|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_43, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_43} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 102840#L310-21 [3870] L310-21-->L310-23: Formula: (< v_~m_pc~0_24 1) InVars {~m_pc~0=v_~m_pc~0_24} OutVars{~m_pc~0=v_~m_pc~0_24} AuxVars[] AssignedVars[] 102830#L310-23 [2785] L310-23-->L321-7: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_47 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_47} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 102838#L321-7 [4303] L321-7-->L815-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 102836#L815-21 [2667] L815-21-->L815-23: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_48) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_48} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_48} AuxVars[] AssignedVars[] 96831#L815-23 [2638] L815-23-->L329-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 96832#L329-21 [3911] L329-21-->L329-23: Formula: (< v_~t1_pc~0_24 1) InVars {~t1_pc~0=v_~t1_pc~0_24} OutVars{~t1_pc~0=v_~t1_pc~0_24} AuxVars[] AssignedVars[] 97096#L329-23 [3052] L329-23-->L340-7: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 102795#L340-7 [4310] L340-7-->L823-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 102792#L823-21 [2931] L823-21-->L823-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} AuxVars[] AssignedVars[] 97039#L823-23 [2934] L823-23-->L348-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_25|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 97040#L348-21 [3953] L348-21-->L348-23: Formula: (> 1 v_~t2_pc~0_24) InVars {~t2_pc~0=v_~t2_pc~0_24} OutVars{~t2_pc~0=v_~t2_pc~0_24} AuxVars[] AssignedVars[] 97189#L348-23 [3319] L348-23-->L359-7: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 97145#L359-7 [4317] L359-7-->L831-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 96728#L831-21 [2490] L831-21-->L831-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} AuxVars[] AssignedVars[] 96729#L831-23 [3197] L831-23-->L367-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_25|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 97174#L367-21 [3995] L367-21-->L367-23: Formula: (> v_~t3_pc~0_24 1) InVars {~t3_pc~0=v_~t3_pc~0_24} OutVars{~t3_pc~0=v_~t3_pc~0_24} AuxVars[] AssignedVars[] 102033#L367-23 [2385] L367-23-->L378-7: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 102031#L378-7 [4324] L378-7-->L839-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 102029#L839-21 [4023] L839-21-->L839-23: Formula: (and (= v_~t3_st~0_21 0) (> v_ULTIMATE.start_activate_threads_~tmp___2~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} OutVars{~t3_st~0=v_~t3_st~0_21, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} AuxVars[] AssignedVars[~t3_st~0] 102027#L839-23 [2722] L839-23-->L386-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_49, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 101400#L386-21 [4038] L386-21-->L386-23: Formula: (> 1 v_~t4_pc~0_24) InVars {~t4_pc~0=v_~t4_pc~0_24} OutVars{~t4_pc~0=v_~t4_pc~0_24} AuxVars[] AssignedVars[] 101396#L386-23 [2623] L386-23-->L397-7: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 100760#L397-7 [4331] L397-7-->L847-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 100759#L847-21 [4065] L847-21-->L847-23: Formula: (and (= v_~t4_st~0_22 0) (< v_ULTIMATE.start_activate_threads_~tmp___3~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47, ~t4_st~0=v_~t4_st~0_22} AuxVars[] AssignedVars[~t4_st~0] 100758#L847-23 [2983] L847-23-->L405-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_25|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 100753#L405-21 [4080] L405-21-->L405-23: Formula: (> v_~t5_pc~0_24 1) InVars {~t5_pc~0=v_~t5_pc~0_24} OutVars{~t5_pc~0=v_~t5_pc~0_24} AuxVars[] AssignedVars[] 100750#L405-23 [2891] L405-23-->L416-7: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 100747#L416-7 [4338] L416-7-->L855-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 100746#L855-21 [3251] L855-21-->L855-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} AuxVars[] AssignedVars[] 100741#L855-23 [3257] L855-23-->L424-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_25|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 99535#L424-21 [4122] L424-21-->L424-23: Formula: (> 1 v_~t6_pc~0_24) InVars {~t6_pc~0=v_~t6_pc~0_24} OutVars{~t6_pc~0=v_~t6_pc~0_24} AuxVars[] AssignedVars[] 99534#L424-23 [3177] L424-23-->L435-7: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 99533#L435-7 [4340] L435-7-->L863-21: Formula: (and (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___5~0_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_35|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_41|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 99532#L863-21 [4135] L863-21-->L863-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___5~0_47 0) (= v_~t6_st~0_22 0)) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} OutVars{~t6_st~0=v_~t6_st~0_22, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} AuxVars[] AssignedVars[~t6_st~0] 99530#L863-23 [4138] L863-23-->L733-3: Formula: (> v_~M_E~0_35 1) InVars {~M_E~0=v_~M_E~0_35} OutVars{~M_E~0=v_~M_E~0_35} AuxVars[] AssignedVars[] 99528#L733-3 [3184] L733-3-->L738-3: Formula: (and (= v_~T1_E~0_15 1) (= v_~T1_E~0_14 2)) InVars {~T1_E~0=v_~T1_E~0_15} OutVars{~T1_E~0=v_~T1_E~0_14} AuxVars[] AssignedVars[~T1_E~0] 99526#L738-3 [4142] L738-3-->L743-3: Formula: (< 1 v_~T2_E~0_16) InVars {~T2_E~0=v_~T2_E~0_16} OutVars{~T2_E~0=v_~T2_E~0_16} AuxVars[] AssignedVars[] 99524#L743-3 [4143] L743-3-->L748-3: Formula: (< 1 v_~T3_E~0_16) InVars {~T3_E~0=v_~T3_E~0_16} OutVars{~T3_E~0=v_~T3_E~0_16} AuxVars[] AssignedVars[] 99522#L748-3 [4145] L748-3-->L753-3: Formula: (> v_~T4_E~0_16 1) InVars {~T4_E~0=v_~T4_E~0_16} OutVars{~T4_E~0=v_~T4_E~0_16} AuxVars[] AssignedVars[] 99520#L753-3 [4148] L753-3-->L758-3: Formula: (< 1 v_~T5_E~0_16) InVars {~T5_E~0=v_~T5_E~0_16} OutVars{~T5_E~0=v_~T5_E~0_16} AuxVars[] AssignedVars[] 99518#L758-3 [4149] L758-3-->L763-3: Formula: (> v_~T6_E~0_16 1) InVars {~T6_E~0=v_~T6_E~0_16} OutVars{~T6_E~0=v_~T6_E~0_16} AuxVars[] AssignedVars[] 99516#L763-3 [4151] L763-3-->L768-3: Formula: (< 1 v_~E_1~0_36) InVars {~E_1~0=v_~E_1~0_36} OutVars{~E_1~0=v_~E_1~0_36} AuxVars[] AssignedVars[] 99514#L768-3 [4154] L768-3-->L773-3: Formula: (< 1 v_~E_2~0_36) InVars {~E_2~0=v_~E_2~0_36} OutVars{~E_2~0=v_~E_2~0_36} AuxVars[] AssignedVars[] 99512#L773-3 [4156] L773-3-->L778-3: Formula: (< 1 v_~E_3~0_36) InVars {~E_3~0=v_~E_3~0_36} OutVars{~E_3~0=v_~E_3~0_36} AuxVars[] AssignedVars[] 99510#L778-3 [3308] L778-3-->L783-3: Formula: (and (= 1 v_~E_4~0_35) (= v_~E_4~0_34 2)) InVars {~E_4~0=v_~E_4~0_35} OutVars{~E_4~0=v_~E_4~0_34} AuxVars[] AssignedVars[~E_4~0] 99508#L783-3 [4160] L783-3-->L788-3: Formula: (< 1 v_~E_5~0_36) InVars {~E_5~0=v_~E_5~0_36} OutVars{~E_5~0=v_~E_5~0_36} AuxVars[] AssignedVars[] 99506#L788-3 [4162] L788-3-->L793-3: Formula: (< 1 v_~E_6~0_36) InVars {~E_6~0=v_~E_6~0_36} OutVars{~E_6~0=v_~E_6~0_36} AuxVars[] AssignedVars[] 99504#L793-3 [2966] L793-3-->L494-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_30} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 99502#L494-1 [2878] L494-1-->L531-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33 1) (= 0 v_~m_st~0_21)) InVars {~m_st~0=v_~m_st~0_21} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33, ~m_st~0=v_~m_st~0_21} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 99494#L531-1 [4341] L531-1-->L1033: Formula: (and (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp~3] 99492#L1033 [4169] L1033-->L1033-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_6) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} AuxVars[] AssignedVars[] 99490#L1033-1 [2919] L1033-1-->L494-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_3|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_6, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_exists_runnable_thread_~__retres1~7, ULTIMATE.start_stop_simulation_#res] 99483#L494-2 [2882] L494-2-->L531-2: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9 1) (= v_~m_st~0_6 0)) InVars {~m_st~0=v_~m_st~0_6} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9, ~m_st~0=v_~m_st~0_6} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 99482#L531-2 [4343] L531-2-->L988: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 99481#L988 [3240] L988-->L995: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 99480#L995 [4354] L995-->L1014-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_6|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_#t~ret17, ULTIMATE.start_stop_simulation_#res] 97164#L1014-1 [2020-06-22 00:13:27,749 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:27,749 INFO L82 PathProgramCache]: Analyzing trace with hash -1932600016, now seen corresponding path program 1 times [2020-06-22 00:13:27,749 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:27,749 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:27,750 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:27,750 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:27,750 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:27,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:13:27,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:13:27,803 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:27,804 INFO L82 PathProgramCache]: Analyzing trace with hash -273088033, now seen corresponding path program 2 times [2020-06-22 00:13:27,804 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:27,804 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:27,804 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:27,805 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:27,805 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:27,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:27,826 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:27,826 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:27,827 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2020-06-22 00:13:27,827 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-06-22 00:13:27,827 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2020-06-22 00:13:27,827 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2020-06-22 00:13:27,827 INFO L87 Difference]: Start difference. First operand 6280 states and 10246 transitions. cyclomatic complexity: 3967 Second operand 4 states. [2020-06-22 00:13:28,679 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-06-22 00:13:28,679 INFO L93 Difference]: Finished difference Result 11256 states and 18282 transitions. [2020-06-22 00:13:28,679 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2020-06-22 00:13:28,680 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11256 states and 18282 transitions. [2020-06-22 00:13:28,723 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 11184 [2020-06-22 00:13:28,747 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11256 states to 11256 states and 18282 transitions. [2020-06-22 00:13:28,748 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11256 [2020-06-22 00:13:28,756 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11256 [2020-06-22 00:13:28,756 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11256 states and 18282 transitions. [2020-06-22 00:13:28,765 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-06-22 00:13:28,765 INFO L706 BuchiCegarLoop]: Abstraction has 11256 states and 18282 transitions. [2020-06-22 00:13:28,770 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11256 states and 18282 transitions. [2020-06-22 00:13:28,838 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11256 to 6312. [2020-06-22 00:13:28,838 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6312 states. [2020-06-22 00:13:28,849 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6312 states to 6312 states and 10294 transitions. [2020-06-22 00:13:28,849 INFO L729 BuchiCegarLoop]: Abstraction has 6312 states and 10294 transitions. [2020-06-22 00:13:28,849 INFO L609 BuchiCegarLoop]: Abstraction has 6312 states and 10294 transitions. [2020-06-22 00:13:28,849 INFO L442 BuchiCegarLoop]: ======== Iteration 33============ [2020-06-22 00:13:28,849 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6312 states and 10294 transitions. [2020-06-22 00:13:28,863 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 6240 [2020-06-22 00:13:28,864 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-06-22 00:13:28,864 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-06-22 00:13:28,866 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:28,866 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:28,867 INFO L794 eck$LassoCheckResult]: Stem: 114662#ULTIMATE.startENTRY [4266] ULTIMATE.startENTRY-->L444: Formula: (and (= 1 v_~t6_i~0_7) (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~M_E~0_37 2) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 0 v_~t6_pc~0_26) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_6~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= v_~T6_E~0_18 2) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~t6_st~0_24) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t6_pc~0=v_~t6_pc~0_26, ~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~T6_E~0=v_~T6_E~0_18, ~M_E~0=v_~M_E~0_37, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ~T4_E~0=v_~T4_E~0_18, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_4|, ~t6_i~0=v_~t6_i~0_7, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ULTIMATE.start_main_~__retres1~8=v_ULTIMATE.start_main_~__retres1~8_6, ~T2_E~0=v_~T2_E~0_18, ~t6_st~0=v_~t6_st~0_24, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_6~0=v_~E_6~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t6_pc~0, ~t5_i~0, ~t1_pc~0, ~t5_st~0, ~T6_E~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ~T4_E~0, ULTIMATE.start_start_simulation_#t~ret17, ~t6_i~0, ~t2_st~0, ~t2_pc~0, ULTIMATE.start_main_~__retres1~8, ~T2_E~0, ~t6_st~0, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_6~0, ULTIMATE.start_main_#res, ~E_2~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 114231#L444 [2453] L444-->L451-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 114232#L451-1 [3030] L451-1-->L456-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 114321#L456-1 [2574] L456-1-->L461-1: Formula: (and (= v_~t2_st~0_2 0) (= 1 v_~t2_i~0_3)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_2} AuxVars[] AssignedVars[~t2_st~0] 114322#L461-1 [2880] L461-1-->L466-1: Formula: (and (= v_~t3_st~0_3 0) (= v_~t3_i~0_3 1)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_3, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 114236#L466-1 [2457] L466-1-->L471-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 114237#L471-1 [3209] L471-1-->L476-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 114483#L476-1 [2761] L476-1-->L481-1: Formula: (and (= 1 v_~t6_i~0_3) (= v_~t6_st~0_4 0)) InVars {~t6_i~0=v_~t6_i~0_3} OutVars{~t6_st~0=v_~t6_st~0_4, ~t6_i~0=v_~t6_i~0_3} AuxVars[] AssignedVars[~t6_st~0] 114484#L481-1 [3652] L481-1-->L660-1: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 114684#L660-1 [3654] L660-1-->L665-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 114149#L665-1 [3655] L665-1-->L670-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 114150#L670-1 [3658] L670-1-->L675-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 114243#L675-1 [3659] L675-1-->L680-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 114244#L680-1 [3661] L680-1-->L685-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 114496#L685-1 [3663] L685-1-->L690-1: Formula: (< 0 v_~T6_E~0_4) InVars {~T6_E~0=v_~T6_E~0_4} OutVars{~T6_E~0=v_~T6_E~0_4} AuxVars[] AssignedVars[] 114497#L690-1 [3665] L690-1-->L695-1: Formula: (> v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 114361#L695-1 [3668] L695-1-->L700-1: Formula: (> v_~E_2~0_6 0) InVars {~E_2~0=v_~E_2~0_6} OutVars{~E_2~0=v_~E_2~0_6} AuxVars[] AssignedVars[] 114362#L700-1 [3670] L700-1-->L705-1: Formula: (> v_~E_3~0_6 0) InVars {~E_3~0=v_~E_3~0_6} OutVars{~E_3~0=v_~E_3~0_6} AuxVars[] AssignedVars[] 114641#L705-1 [3672] L705-1-->L710-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 114303#L710-1 [3674] L710-1-->L715-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 114304#L715-1 [3675] L715-1-->L720-1: Formula: (> v_~E_6~0_4 0) InVars {~E_6~0=v_~E_6~0_4} OutVars{~E_6~0=v_~E_6~0_4} AuxVars[] AssignedVars[] 114186#L720-1 [2412] L720-1-->L310: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_7, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_4|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_4|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_7, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_4, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_4, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_2|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_2|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_4|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_4|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_7, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_2|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_4} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 114187#L310 [3678] L310-->L310-2: Formula: (< v_~m_pc~0_5 1) InVars {~m_pc~0=v_~m_pc~0_5} OutVars{~m_pc~0=v_~m_pc~0_5} AuxVars[] AssignedVars[] 114334#L310-2 [2805] L310-2-->L321: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_11 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 114329#L321 [4267] L321-->L815: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 114330#L815 [2976] L815-->L815-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_12) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} AuxVars[] AssignedVars[] 114636#L815-2 [2961] L815-2-->L329: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 114551#L329 [3683] L329-->L329-2: Formula: (< v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 114552#L329-2 [2861] L329-2-->L340: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 114547#L340 [4268] L340-->L823: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 114548#L823 [3234] L823-->L823-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} AuxVars[] AssignedVars[] 114784#L823-2 [3235] L823-2-->L348: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_4|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 114745#L348 [3690] L348-->L348-2: Formula: (< v_~t2_pc~0_5 1) InVars {~t2_pc~0=v_~t2_pc~0_5} OutVars{~t2_pc~0=v_~t2_pc~0_5} AuxVars[] AssignedVars[] 114747#L348-2 [3153] L348-2-->L359: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 114742#L359 [4269] L359-->L831: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 114310#L831 [2537] L831-->L831-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} AuxVars[] AssignedVars[] 114298#L831-2 [2520] L831-2-->L367: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_4|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 114239#L367 [3695] L367-->L367-2: Formula: (> 1 v_~t3_pc~0_5) InVars {~t3_pc~0=v_~t3_pc~0_5} OutVars{~t3_pc~0=v_~t3_pc~0_5} AuxVars[] AssignedVars[] 114216#L367-2 [2438] L367-2-->L378: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 114217#L378 [4270] L378-->L839: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 114238#L839 [2791] L839-->L839-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} AuxVars[] AssignedVars[] 114508#L839-2 [2794] L839-2-->L386: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_7, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 114417#L386 [3702] L386-->L386-2: Formula: (< v_~t4_pc~0_5 1) InVars {~t4_pc~0=v_~t4_pc~0_5} OutVars{~t4_pc~0=v_~t4_pc~0_5} AuxVars[] AssignedVars[] 114418#L386-2 [2680] L386-2-->L397: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 114415#L397 [4271] L397-->L847: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 114416#L847 [3084] L847-->L847-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} AuxVars[] AssignedVars[] 114696#L847-2 [3064] L847-2-->L405: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_4|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 114697#L405 [3708] L405-->L405-2: Formula: (> 1 v_~t5_pc~0_5) InVars {~t5_pc~0=v_~t5_pc~0_5} OutVars{~t5_pc~0=v_~t5_pc~0_5} AuxVars[] AssignedVars[] 114580#L405-2 [2940] L405-2-->L416: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 114620#L416 [4272] L416-->L855: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 114710#L855 [3091] L855-->L855-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_12} AuxVars[] AssignedVars[] 114711#L855-2 [3093] L855-2-->L424: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_4|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 114282#L424 [3713] L424-->L424-2: Formula: (< v_~t6_pc~0_5 1) InVars {~t6_pc~0=v_~t6_pc~0_5} OutVars{~t6_pc~0=v_~t6_pc~0_5} AuxVars[] AssignedVars[] 114283#L424-2 [2503] L424-2-->L435: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 114279#L435 [4273] L435-->L863: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___5~0_49 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_28|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_28|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 114200#L863 [2425] L863-->L863-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___5~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} AuxVars[] AssignedVars[] 114172#L863-2 [3719] L863-2-->L733-1: Formula: (> v_~M_E~0_15 1) InVars {~M_E~0=v_~M_E~0_15} OutVars{~M_E~0=v_~M_E~0_15} AuxVars[] AssignedVars[] 114173#L733-1 [3722] L733-1-->L738-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 114638#L738-1 [3723] L738-1-->L743-1: Formula: (< 1 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 114301#L743-1 [3726] L743-1-->L748-1: Formula: (< 1 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 114302#L748-1 [3728] L748-1-->L753-1: Formula: (> v_~T4_E~0_10 1) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 114181#L753-1 [3729] L753-1-->L758-1: Formula: (< 1 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 114182#L758-1 [3731] L758-1-->L763-1: Formula: (> v_~T6_E~0_10 1) InVars {~T6_E~0=v_~T6_E~0_10} OutVars{~T6_E~0=v_~T6_E~0_10} AuxVars[] AssignedVars[] 114255#L763-1 [3733] L763-1-->L768-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 114256#L768-1 [3736] L768-1-->L773-1: Formula: (< 1 v_~E_2~0_14) InVars {~E_2~0=v_~E_2~0_14} OutVars{~E_2~0=v_~E_2~0_14} AuxVars[] AssignedVars[] 114487#L773-1 [3737] L773-1-->L778-1: Formula: (< 1 v_~E_3~0_14) InVars {~E_3~0=v_~E_3~0_14} OutVars{~E_3~0=v_~E_3~0_14} AuxVars[] AssignedVars[] 114488#L778-1 [3740] L778-1-->L783-1: Formula: (< 1 v_~E_4~0_14) InVars {~E_4~0=v_~E_4~0_14} OutVars{~E_4~0=v_~E_4~0_14} AuxVars[] AssignedVars[] 114353#L783-1 [3741] L783-1-->L788-1: Formula: (< 1 v_~E_5~0_14) InVars {~E_5~0=v_~E_5~0_14} OutVars{~E_5~0=v_~E_5~0_14} AuxVars[] AssignedVars[] 114354#L788-1 [3744] L788-1-->L1014-1: Formula: (< 1 v_~E_6~0_14) InVars {~E_6~0=v_~E_6~0_14} OutVars{~E_6~0=v_~E_6~0_14} AuxVars[] AssignedVars[] 114757#L1014-1 [2020-06-22 00:13:28,868 INFO L796 eck$LassoCheckResult]: Loop: 114757#L1014-1 [4274] L1014-1-->L635: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp_ndt_7~0=v_ULTIMATE.start_eval_~tmp_ndt_7~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp_ndt_7~0] 117994#L635 [4275] L635-->L494: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_37} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 117945#L494 [3745] L494-->L498: Formula: (< v_~m_st~0_9 0) InVars {~m_st~0=v_~m_st~0_9} OutVars{~m_st~0=v_~m_st~0_9} AuxVars[] AssignedVars[] 117939#L498 [3749] L498-->L502: Formula: (< v_~t1_st~0_9 0) InVars {~t1_st~0=v_~t1_st~0_9} OutVars{~t1_st~0=v_~t1_st~0_9} AuxVars[] AssignedVars[] 117940#L502 [3753] L502-->L506: Formula: (> v_~t2_st~0_9 0) InVars {~t2_st~0=v_~t2_st~0_9} OutVars{~t2_st~0=v_~t2_st~0_9} AuxVars[] AssignedVars[] 117941#L506 [3760] L506-->L510: Formula: (< 0 v_~t3_st~0_10) InVars {~t3_st~0=v_~t3_st~0_10} OutVars{~t3_st~0=v_~t3_st~0_10} AuxVars[] AssignedVars[] 117942#L510 [3765] L510-->L514: Formula: (> 0 v_~t4_st~0_11) InVars {~t4_st~0=v_~t4_st~0_11} OutVars{~t4_st~0=v_~t4_st~0_11} AuxVars[] AssignedVars[] 117944#L514 [3773] L514-->L518: Formula: (> v_~t5_st~0_11 0) InVars {~t5_st~0=v_~t5_st~0_11} OutVars{~t5_st~0=v_~t5_st~0_11} AuxVars[] AssignedVars[] 117943#L518 [3783] L518-->L531: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_28 0) (< 0 v_~t6_st~0_11)) InVars {~t6_st~0=v_~t6_st~0_11} OutVars{~t6_st~0=v_~t6_st~0_11, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_28} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 116257#L531 [4276] L531-->L546: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 116258#L546 [4278] L546-->L660-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 117919#L660-2 [3747] L660-2-->L660-4: Formula: (> v_~M_E~0_30 0) InVars {~M_E~0=v_~M_E~0_30} OutVars{~M_E~0=v_~M_E~0_30} AuxVars[] AssignedVars[] 117917#L660-4 [3058] L660-4-->L665-3: Formula: (and (= v_~T1_E~0_11 1) (= v_~T1_E~0_12 0)) InVars {~T1_E~0=v_~T1_E~0_12} OutVars{~T1_E~0=v_~T1_E~0_11} AuxVars[] AssignedVars[~T1_E~0] 117915#L665-3 [3756] L665-3-->L670-3: Formula: (< 0 v_~T2_E~0_13) InVars {~T2_E~0=v_~T2_E~0_13} OutVars{~T2_E~0=v_~T2_E~0_13} AuxVars[] AssignedVars[] 117913#L670-3 [3762] L670-3-->L675-3: Formula: (< 0 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 117911#L675-3 [3768] L675-3-->L680-3: Formula: (> v_~T4_E~0_13 0) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 117909#L680-3 [3776] L680-3-->L685-3: Formula: (< 0 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 117907#L685-3 [3785] L685-3-->L690-3: Formula: (> v_~T6_E~0_13 0) InVars {~T6_E~0=v_~T6_E~0_13} OutVars{~T6_E~0=v_~T6_E~0_13} AuxVars[] AssignedVars[] 117905#L690-3 [3795] L690-3-->L695-3: Formula: (< 0 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 117903#L695-3 [3805] L695-3-->L700-3: Formula: (< 0 v_~E_2~0_31) InVars {~E_2~0=v_~E_2~0_31} OutVars{~E_2~0=v_~E_2~0_31} AuxVars[] AssignedVars[] 117901#L700-3 [3818] L700-3-->L705-3: Formula: (< 0 v_~E_3~0_31) InVars {~E_3~0=v_~E_3~0_31} OutVars{~E_3~0=v_~E_3~0_31} AuxVars[] AssignedVars[] 117899#L705-3 [2688] L705-3-->L710-3: Formula: (and (= v_~E_4~0_29 1) (= 0 v_~E_4~0_30)) InVars {~E_4~0=v_~E_4~0_30} OutVars{~E_4~0=v_~E_4~0_29} AuxVars[] AssignedVars[~E_4~0] 117897#L710-3 [3844] L710-3-->L715-3: Formula: (< 0 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 117895#L715-3 [3854] L715-3-->L720-3: Formula: (< 0 v_~E_6~0_31) InVars {~E_6~0=v_~E_6~0_31} OutVars{~E_6~0=v_~E_6~0_31} AuxVars[] AssignedVars[] 117893#L720-3 [2388] L720-3-->L310-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_43, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_43, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_25|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_25|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_25|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_43, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_43, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_43, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_25|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_25|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_25|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_25|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_43, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_25|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_43, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_43} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 117891#L310-21 [3870] L310-21-->L310-23: Formula: (< v_~m_pc~0_24 1) InVars {~m_pc~0=v_~m_pc~0_24} OutVars{~m_pc~0=v_~m_pc~0_24} AuxVars[] AssignedVars[] 114827#L310-23 [2785] L310-23-->L321-7: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_47 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_47} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 117889#L321-7 [4303] L321-7-->L815-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 117887#L815-21 [2667] L815-21-->L815-23: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_48) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_48} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_48} AuxVars[] AssignedVars[] 117885#L815-23 [2638] L815-23-->L329-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 117883#L329-21 [3911] L329-21-->L329-23: Formula: (< v_~t1_pc~0_24 1) InVars {~t1_pc~0=v_~t1_pc~0_24} OutVars{~t1_pc~0=v_~t1_pc~0_24} AuxVars[] AssignedVars[] 117882#L329-23 [3052] L329-23-->L340-7: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 114540#L340-7 [4310] L340-7-->L823-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 114541#L823-21 [2931] L823-21-->L823-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} AuxVars[] AssignedVars[] 114611#L823-23 [2934] L823-23-->L348-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_25|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 114613#L348-21 [3953] L348-21-->L348-23: Formula: (> 1 v_~t2_pc~0_24) InVars {~t2_pc~0=v_~t2_pc~0_24} OutVars{~t2_pc~0=v_~t2_pc~0_24} AuxVars[] AssignedVars[] 114791#L348-23 [3319] L348-23-->L359-7: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 117796#L359-7 [4317] L359-7-->L831-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 117797#L831-21 [2490] L831-21-->L831-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} AuxVars[] AssignedVars[] 117743#L831-23 [3197] L831-23-->L367-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_25|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 117744#L367-21 [3995] L367-21-->L367-23: Formula: (> v_~t3_pc~0_24 1) InVars {~t3_pc~0=v_~t3_pc~0_24} OutVars{~t3_pc~0=v_~t3_pc~0_24} AuxVars[] AssignedVars[] 117735#L367-23 [2385] L367-23-->L378-7: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 117736#L378-7 [4324] L378-7-->L839-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 117731#L839-21 [4023] L839-21-->L839-23: Formula: (and (= v_~t3_st~0_21 0) (> v_ULTIMATE.start_activate_threads_~tmp___2~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} OutVars{~t3_st~0=v_~t3_st~0_21, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} AuxVars[] AssignedVars[~t3_st~0] 117732#L839-23 [2722] L839-23-->L386-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_49, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 117683#L386-21 [4038] L386-21-->L386-23: Formula: (> 1 v_~t4_pc~0_24) InVars {~t4_pc~0=v_~t4_pc~0_24} OutVars{~t4_pc~0=v_~t4_pc~0_24} AuxVars[] AssignedVars[] 117682#L386-23 [2623] L386-23-->L397-7: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 118283#L397-7 [4331] L397-7-->L847-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 118281#L847-21 [4065] L847-21-->L847-23: Formula: (and (= v_~t4_st~0_22 0) (< v_ULTIMATE.start_activate_threads_~tmp___3~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47, ~t4_st~0=v_~t4_st~0_22} AuxVars[] AssignedVars[~t4_st~0] 118279#L847-23 [2983] L847-23-->L405-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_25|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 118276#L405-21 [4080] L405-21-->L405-23: Formula: (> v_~t5_pc~0_24 1) InVars {~t5_pc~0=v_~t5_pc~0_24} OutVars{~t5_pc~0=v_~t5_pc~0_24} AuxVars[] AssignedVars[] 118273#L405-23 [2891] L405-23-->L416-7: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 118271#L416-7 [4338] L416-7-->L855-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 118269#L855-21 [3251] L855-21-->L855-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} AuxVars[] AssignedVars[] 114792#L855-23 [3257] L855-23-->L424-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_25|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 114758#L424-21 [4122] L424-21-->L424-23: Formula: (> 1 v_~t6_pc~0_24) InVars {~t6_pc~0=v_~t6_pc~0_24} OutVars{~t6_pc~0=v_~t6_pc~0_24} AuxVars[] AssignedVars[] 114759#L424-23 [3177] L424-23-->L435-7: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 118713#L435-7 [4340] L435-7-->L863-21: Formula: (and (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___5~0_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_35|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_41|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 118712#L863-21 [4135] L863-21-->L863-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___5~0_47 0) (= v_~t6_st~0_22 0)) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} OutVars{~t6_st~0=v_~t6_st~0_22, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} AuxVars[] AssignedVars[~t6_st~0] 118711#L863-23 [4138] L863-23-->L733-3: Formula: (> v_~M_E~0_35 1) InVars {~M_E~0=v_~M_E~0_35} OutVars{~M_E~0=v_~M_E~0_35} AuxVars[] AssignedVars[] 118710#L733-3 [3184] L733-3-->L738-3: Formula: (and (= v_~T1_E~0_15 1) (= v_~T1_E~0_14 2)) InVars {~T1_E~0=v_~T1_E~0_15} OutVars{~T1_E~0=v_~T1_E~0_14} AuxVars[] AssignedVars[~T1_E~0] 118709#L738-3 [4142] L738-3-->L743-3: Formula: (< 1 v_~T2_E~0_16) InVars {~T2_E~0=v_~T2_E~0_16} OutVars{~T2_E~0=v_~T2_E~0_16} AuxVars[] AssignedVars[] 118708#L743-3 [4143] L743-3-->L748-3: Formula: (< 1 v_~T3_E~0_16) InVars {~T3_E~0=v_~T3_E~0_16} OutVars{~T3_E~0=v_~T3_E~0_16} AuxVars[] AssignedVars[] 118707#L748-3 [4145] L748-3-->L753-3: Formula: (> v_~T4_E~0_16 1) InVars {~T4_E~0=v_~T4_E~0_16} OutVars{~T4_E~0=v_~T4_E~0_16} AuxVars[] AssignedVars[] 118706#L753-3 [4148] L753-3-->L758-3: Formula: (< 1 v_~T5_E~0_16) InVars {~T5_E~0=v_~T5_E~0_16} OutVars{~T5_E~0=v_~T5_E~0_16} AuxVars[] AssignedVars[] 118705#L758-3 [4149] L758-3-->L763-3: Formula: (> v_~T6_E~0_16 1) InVars {~T6_E~0=v_~T6_E~0_16} OutVars{~T6_E~0=v_~T6_E~0_16} AuxVars[] AssignedVars[] 118704#L763-3 [4151] L763-3-->L768-3: Formula: (< 1 v_~E_1~0_36) InVars {~E_1~0=v_~E_1~0_36} OutVars{~E_1~0=v_~E_1~0_36} AuxVars[] AssignedVars[] 118703#L768-3 [4154] L768-3-->L773-3: Formula: (< 1 v_~E_2~0_36) InVars {~E_2~0=v_~E_2~0_36} OutVars{~E_2~0=v_~E_2~0_36} AuxVars[] AssignedVars[] 118702#L773-3 [4156] L773-3-->L778-3: Formula: (< 1 v_~E_3~0_36) InVars {~E_3~0=v_~E_3~0_36} OutVars{~E_3~0=v_~E_3~0_36} AuxVars[] AssignedVars[] 118701#L778-3 [3308] L778-3-->L783-3: Formula: (and (= 1 v_~E_4~0_35) (= v_~E_4~0_34 2)) InVars {~E_4~0=v_~E_4~0_35} OutVars{~E_4~0=v_~E_4~0_34} AuxVars[] AssignedVars[~E_4~0] 118700#L783-3 [4160] L783-3-->L788-3: Formula: (< 1 v_~E_5~0_36) InVars {~E_5~0=v_~E_5~0_36} OutVars{~E_5~0=v_~E_5~0_36} AuxVars[] AssignedVars[] 118699#L788-3 [4162] L788-3-->L793-3: Formula: (< 1 v_~E_6~0_36) InVars {~E_6~0=v_~E_6~0_36} OutVars{~E_6~0=v_~E_6~0_36} AuxVars[] AssignedVars[] 118698#L793-3 [2966] L793-3-->L494-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_30} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 118697#L494-1 [2878] L494-1-->L531-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33 1) (= 0 v_~m_st~0_21)) InVars {~m_st~0=v_~m_st~0_21} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33, ~m_st~0=v_~m_st~0_21} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 118688#L531-1 [4341] L531-1-->L1033: Formula: (and (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp~3] 118684#L1033 [4169] L1033-->L1033-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_6) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} AuxVars[] AssignedVars[] 118681#L1033-1 [2919] L1033-1-->L494-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_3|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_6, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_exists_runnable_thread_~__retres1~7, ULTIMATE.start_stop_simulation_#res] 118674#L494-2 [2882] L494-2-->L531-2: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9 1) (= v_~m_st~0_6 0)) InVars {~m_st~0=v_~m_st~0_6} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9, ~m_st~0=v_~m_st~0_6} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 118672#L531-2 [4343] L531-2-->L988: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 118668#L988 [3240] L988-->L995: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 118664#L995 [4354] L995-->L1014-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_6|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_#t~ret17, ULTIMATE.start_stop_simulation_#res] 114757#L1014-1 [2020-06-22 00:13:28,868 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:28,868 INFO L82 PathProgramCache]: Analyzing trace with hash -1932600016, now seen corresponding path program 2 times [2020-06-22 00:13:28,868 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:28,869 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:28,870 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:28,870 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2020-06-22 00:13:28,870 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:28,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:13:28,881 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:13:28,895 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:28,895 INFO L82 PathProgramCache]: Analyzing trace with hash -16495337, now seen corresponding path program 1 times [2020-06-22 00:13:28,895 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:28,895 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:28,896 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:28,896 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2020-06-22 00:13:28,896 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:28,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:28,930 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:28,931 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:28,931 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2020-06-22 00:13:28,931 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-06-22 00:13:28,931 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2020-06-22 00:13:28,931 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2020-06-22 00:13:28,932 INFO L87 Difference]: Start difference. First operand 6312 states and 10294 transitions. cyclomatic complexity: 3983 Second operand 6 states. [2020-06-22 00:13:31,388 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-06-22 00:13:31,388 INFO L93 Difference]: Finished difference Result 25077 states and 42022 transitions. [2020-06-22 00:13:31,388 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2020-06-22 00:13:31,389 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 25077 states and 42022 transitions. [2020-06-22 00:13:31,501 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 25004 [2020-06-22 00:13:31,574 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 25077 states to 25077 states and 42022 transitions. [2020-06-22 00:13:31,574 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25077 [2020-06-22 00:13:31,592 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25077 [2020-06-22 00:13:31,593 INFO L73 IsDeterministic]: Start isDeterministic. Operand 25077 states and 42022 transitions. [2020-06-22 00:13:31,611 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-06-22 00:13:31,611 INFO L706 BuchiCegarLoop]: Abstraction has 25077 states and 42022 transitions. [2020-06-22 00:13:31,622 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25077 states and 42022 transitions. [2020-06-22 00:13:31,740 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25077 to 6344. [2020-06-22 00:13:31,740 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6344 states. [2020-06-22 00:13:31,751 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6344 states to 6344 states and 10229 transitions. [2020-06-22 00:13:31,751 INFO L729 BuchiCegarLoop]: Abstraction has 6344 states and 10229 transitions. [2020-06-22 00:13:31,751 INFO L609 BuchiCegarLoop]: Abstraction has 6344 states and 10229 transitions. [2020-06-22 00:13:31,751 INFO L442 BuchiCegarLoop]: ======== Iteration 34============ [2020-06-22 00:13:31,751 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6344 states and 10229 transitions. [2020-06-22 00:13:31,765 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 6272 [2020-06-22 00:13:31,766 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-06-22 00:13:31,766 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-06-22 00:13:31,767 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:31,767 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:31,768 INFO L794 eck$LassoCheckResult]: Stem: 146111#ULTIMATE.startENTRY [4266] ULTIMATE.startENTRY-->L444: Formula: (and (= 1 v_~t6_i~0_7) (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~M_E~0_37 2) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 0 v_~t6_pc~0_26) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_6~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= v_~T6_E~0_18 2) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~t6_st~0_24) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t6_pc~0=v_~t6_pc~0_26, ~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~T6_E~0=v_~T6_E~0_18, ~M_E~0=v_~M_E~0_37, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ~T4_E~0=v_~T4_E~0_18, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_4|, ~t6_i~0=v_~t6_i~0_7, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ULTIMATE.start_main_~__retres1~8=v_ULTIMATE.start_main_~__retres1~8_6, ~T2_E~0=v_~T2_E~0_18, ~t6_st~0=v_~t6_st~0_24, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_6~0=v_~E_6~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t6_pc~0, ~t5_i~0, ~t1_pc~0, ~t5_st~0, ~T6_E~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ~T4_E~0, ULTIMATE.start_start_simulation_#t~ret17, ~t6_i~0, ~t2_st~0, ~t2_pc~0, ULTIMATE.start_main_~__retres1~8, ~T2_E~0, ~t6_st~0, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_6~0, ULTIMATE.start_main_#res, ~E_2~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 145668#L444 [2453] L444-->L451-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 145669#L451-1 [3030] L451-1-->L456-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 145765#L456-1 [2574] L456-1-->L461-1: Formula: (and (= v_~t2_st~0_2 0) (= 1 v_~t2_i~0_3)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_2} AuxVars[] AssignedVars[~t2_st~0] 145766#L461-1 [2880] L461-1-->L466-1: Formula: (and (= v_~t3_st~0_3 0) (= v_~t3_i~0_3 1)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_3, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 145670#L466-1 [2457] L466-1-->L471-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 145671#L471-1 [3209] L471-1-->L476-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 145932#L476-1 [2761] L476-1-->L481-1: Formula: (and (= 1 v_~t6_i~0_3) (= v_~t6_st~0_4 0)) InVars {~t6_i~0=v_~t6_i~0_3} OutVars{~t6_st~0=v_~t6_st~0_4, ~t6_i~0=v_~t6_i~0_3} AuxVars[] AssignedVars[~t6_st~0] 145933#L481-1 [3652] L481-1-->L660-1: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 146138#L660-1 [3654] L660-1-->L665-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 145577#L665-1 [3655] L665-1-->L670-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 145578#L670-1 [3658] L670-1-->L675-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 145677#L675-1 [3659] L675-1-->L680-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 145678#L680-1 [3661] L680-1-->L685-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 145947#L685-1 [3663] L685-1-->L690-1: Formula: (< 0 v_~T6_E~0_4) InVars {~T6_E~0=v_~T6_E~0_4} OutVars{~T6_E~0=v_~T6_E~0_4} AuxVars[] AssignedVars[] 145948#L690-1 [3665] L690-1-->L695-1: Formula: (> v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 145806#L695-1 [3668] L695-1-->L700-1: Formula: (> v_~E_2~0_6 0) InVars {~E_2~0=v_~E_2~0_6} OutVars{~E_2~0=v_~E_2~0_6} AuxVars[] AssignedVars[] 145807#L700-1 [3670] L700-1-->L705-1: Formula: (> v_~E_3~0_6 0) InVars {~E_3~0=v_~E_3~0_6} OutVars{~E_3~0=v_~E_3~0_6} AuxVars[] AssignedVars[] 146087#L705-1 [3672] L705-1-->L710-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 145742#L710-1 [3674] L710-1-->L715-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 145743#L715-1 [3675] L715-1-->L720-1: Formula: (> v_~E_6~0_4 0) InVars {~E_6~0=v_~E_6~0_4} OutVars{~E_6~0=v_~E_6~0_4} AuxVars[] AssignedVars[] 145613#L720-1 [2412] L720-1-->L310: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_7, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_4|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_4|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_7, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_4, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_4, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_2|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_2|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_4|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_4|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_7, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_2|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_4} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 145614#L310 [3678] L310-->L310-2: Formula: (< v_~m_pc~0_5 1) InVars {~m_pc~0=v_~m_pc~0_5} OutVars{~m_pc~0=v_~m_pc~0_5} AuxVars[] AssignedVars[] 145779#L310-2 [2805] L310-2-->L321: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_11 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 145777#L321 [4267] L321-->L815: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 145778#L815 [2976] L815-->L815-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_12) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} AuxVars[] AssignedVars[] 146082#L815-2 [2961] L815-2-->L329: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 145999#L329 [3683] L329-->L329-2: Formula: (< v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 146000#L329-2 [2861] L329-2-->L340: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 145997#L340 [4268] L340-->L823: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 145998#L823 [3234] L823-->L823-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} AuxVars[] AssignedVars[] 146232#L823-2 [3235] L823-2-->L348: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_4|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 146192#L348 [3690] L348-->L348-2: Formula: (< v_~t2_pc~0_5 1) InVars {~t2_pc~0=v_~t2_pc~0_5} OutVars{~t2_pc~0=v_~t2_pc~0_5} AuxVars[] AssignedVars[] 146194#L348-2 [3153] L348-2-->L359: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 146191#L359 [4269] L359-->L831: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 145749#L831 [2537] L831-->L831-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} AuxVars[] AssignedVars[] 145737#L831-2 [2520] L831-2-->L367: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_4|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 145673#L367 [3695] L367-->L367-2: Formula: (> 1 v_~t3_pc~0_5) InVars {~t3_pc~0=v_~t3_pc~0_5} OutVars{~t3_pc~0=v_~t3_pc~0_5} AuxVars[] AssignedVars[] 145648#L367-2 [2438] L367-2-->L378: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 145649#L378 [4270] L378-->L839: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 145672#L839 [2791] L839-->L839-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} AuxVars[] AssignedVars[] 145964#L839-2 [2794] L839-2-->L386: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_7, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 145862#L386 [3702] L386-->L386-2: Formula: (< v_~t4_pc~0_5 1) InVars {~t4_pc~0=v_~t4_pc~0_5} OutVars{~t4_pc~0=v_~t4_pc~0_5} AuxVars[] AssignedVars[] 145863#L386-2 [2680] L386-2-->L397: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 145860#L397 [4271] L397-->L847: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 145861#L847 [3084] L847-->L847-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} AuxVars[] AssignedVars[] 146146#L847-2 [3064] L847-2-->L405: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_4|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 146147#L405 [3708] L405-->L405-2: Formula: (> 1 v_~t5_pc~0_5) InVars {~t5_pc~0=v_~t5_pc~0_5} OutVars{~t5_pc~0=v_~t5_pc~0_5} AuxVars[] AssignedVars[] 146025#L405-2 [2940] L405-2-->L416: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 146071#L416 [4272] L416-->L855: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 146155#L855 [3091] L855-->L855-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_12} AuxVars[] AssignedVars[] 146156#L855-2 [3093] L855-2-->L424: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_4|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 145718#L424 [3713] L424-->L424-2: Formula: (< v_~t6_pc~0_5 1) InVars {~t6_pc~0=v_~t6_pc~0_5} OutVars{~t6_pc~0=v_~t6_pc~0_5} AuxVars[] AssignedVars[] 145719#L424-2 [2503] L424-2-->L435: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 145717#L435 [4273] L435-->L863: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___5~0_49 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_28|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_28|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 145631#L863 [2425] L863-->L863-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___5~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} AuxVars[] AssignedVars[] 145601#L863-2 [3719] L863-2-->L733-1: Formula: (> v_~M_E~0_15 1) InVars {~M_E~0=v_~M_E~0_15} OutVars{~M_E~0=v_~M_E~0_15} AuxVars[] AssignedVars[] 145602#L733-1 [3722] L733-1-->L738-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 146084#L738-1 [3723] L738-1-->L743-1: Formula: (< 1 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 145740#L743-1 [3726] L743-1-->L748-1: Formula: (< 1 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 145741#L748-1 [3728] L748-1-->L753-1: Formula: (> v_~T4_E~0_10 1) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 145606#L753-1 [3729] L753-1-->L758-1: Formula: (< 1 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 145607#L758-1 [3731] L758-1-->L763-1: Formula: (> v_~T6_E~0_10 1) InVars {~T6_E~0=v_~T6_E~0_10} OutVars{~T6_E~0=v_~T6_E~0_10} AuxVars[] AssignedVars[] 145689#L763-1 [3733] L763-1-->L768-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 145690#L768-1 [3736] L768-1-->L773-1: Formula: (< 1 v_~E_2~0_14) InVars {~E_2~0=v_~E_2~0_14} OutVars{~E_2~0=v_~E_2~0_14} AuxVars[] AssignedVars[] 145938#L773-1 [3737] L773-1-->L778-1: Formula: (< 1 v_~E_3~0_14) InVars {~E_3~0=v_~E_3~0_14} OutVars{~E_3~0=v_~E_3~0_14} AuxVars[] AssignedVars[] 145939#L778-1 [3740] L778-1-->L783-1: Formula: (< 1 v_~E_4~0_14) InVars {~E_4~0=v_~E_4~0_14} OutVars{~E_4~0=v_~E_4~0_14} AuxVars[] AssignedVars[] 145800#L783-1 [3741] L783-1-->L788-1: Formula: (< 1 v_~E_5~0_14) InVars {~E_5~0=v_~E_5~0_14} OutVars{~E_5~0=v_~E_5~0_14} AuxVars[] AssignedVars[] 145801#L788-1 [3744] L788-1-->L1014-1: Formula: (< 1 v_~E_6~0_14) InVars {~E_6~0=v_~E_6~0_14} OutVars{~E_6~0=v_~E_6~0_14} AuxVars[] AssignedVars[] 146204#L1014-1 [2020-06-22 00:13:31,769 INFO L796 eck$LassoCheckResult]: Loop: 146204#L1014-1 [4274] L1014-1-->L635: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp_ndt_7~0=v_ULTIMATE.start_eval_~tmp_ndt_7~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp_ndt_7~0] 147536#L635 [4275] L635-->L494: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_37} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 147781#L494 [3745] L494-->L498: Formula: (< v_~m_st~0_9 0) InVars {~m_st~0=v_~m_st~0_9} OutVars{~m_st~0=v_~m_st~0_9} AuxVars[] AssignedVars[] 147775#L498 [3749] L498-->L502: Formula: (< v_~t1_st~0_9 0) InVars {~t1_st~0=v_~t1_st~0_9} OutVars{~t1_st~0=v_~t1_st~0_9} AuxVars[] AssignedVars[] 147776#L502 [3753] L502-->L506: Formula: (> v_~t2_st~0_9 0) InVars {~t2_st~0=v_~t2_st~0_9} OutVars{~t2_st~0=v_~t2_st~0_9} AuxVars[] AssignedVars[] 147777#L506 [3760] L506-->L510: Formula: (< 0 v_~t3_st~0_10) InVars {~t3_st~0=v_~t3_st~0_10} OutVars{~t3_st~0=v_~t3_st~0_10} AuxVars[] AssignedVars[] 147778#L510 [3765] L510-->L514: Formula: (> 0 v_~t4_st~0_11) InVars {~t4_st~0=v_~t4_st~0_11} OutVars{~t4_st~0=v_~t4_st~0_11} AuxVars[] AssignedVars[] 147780#L514 [3773] L514-->L518: Formula: (> v_~t5_st~0_11 0) InVars {~t5_st~0=v_~t5_st~0_11} OutVars{~t5_st~0=v_~t5_st~0_11} AuxVars[] AssignedVars[] 147779#L518 [3783] L518-->L531: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_28 0) (< 0 v_~t6_st~0_11)) InVars {~t6_st~0=v_~t6_st~0_11} OutVars{~t6_st~0=v_~t6_st~0_11, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_28} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 147774#L531 [4276] L531-->L546: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 147771#L546 [4278] L546-->L660-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 147772#L660-2 [3747] L660-2-->L660-4: Formula: (> v_~M_E~0_30 0) InVars {~M_E~0=v_~M_E~0_30} OutVars{~M_E~0=v_~M_E~0_30} AuxVars[] AssignedVars[] 148268#L660-4 [3058] L660-4-->L665-3: Formula: (and (= v_~T1_E~0_11 1) (= v_~T1_E~0_12 0)) InVars {~T1_E~0=v_~T1_E~0_12} OutVars{~T1_E~0=v_~T1_E~0_11} AuxVars[] AssignedVars[~T1_E~0] 148267#L665-3 [3756] L665-3-->L670-3: Formula: (< 0 v_~T2_E~0_13) InVars {~T2_E~0=v_~T2_E~0_13} OutVars{~T2_E~0=v_~T2_E~0_13} AuxVars[] AssignedVars[] 148266#L670-3 [3762] L670-3-->L675-3: Formula: (< 0 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 148265#L675-3 [3768] L675-3-->L680-3: Formula: (> v_~T4_E~0_13 0) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 148264#L680-3 [3776] L680-3-->L685-3: Formula: (< 0 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 145953#L685-3 [3785] L685-3-->L690-3: Formula: (> v_~T6_E~0_13 0) InVars {~T6_E~0=v_~T6_E~0_13} OutVars{~T6_E~0=v_~T6_E~0_13} AuxVars[] AssignedVars[] 145954#L690-3 [3795] L690-3-->L695-3: Formula: (< 0 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 145790#L695-3 [3805] L695-3-->L700-3: Formula: (< 0 v_~E_2~0_31) InVars {~E_2~0=v_~E_2~0_31} OutVars{~E_2~0=v_~E_2~0_31} AuxVars[] AssignedVars[] 145791#L700-3 [3818] L700-3-->L705-3: Formula: (< 0 v_~E_3~0_31) InVars {~E_3~0=v_~E_3~0_31} OutVars{~E_3~0=v_~E_3~0_31} AuxVars[] AssignedVars[] 145871#L705-3 [2688] L705-3-->L710-3: Formula: (and (= v_~E_4~0_29 1) (= 0 v_~E_4~0_30)) InVars {~E_4~0=v_~E_4~0_30} OutVars{~E_4~0=v_~E_4~0_29} AuxVars[] AssignedVars[~E_4~0] 145732#L710-3 [3844] L710-3-->L715-3: Formula: (< 0 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 145733#L715-3 [3854] L715-3-->L720-3: Formula: (< 0 v_~E_6~0_31) InVars {~E_6~0=v_~E_6~0_31} OutVars{~E_6~0=v_~E_6~0_31} AuxVars[] AssignedVars[] 145582#L720-3 [2388] L720-3-->L310-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_43, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_43, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_25|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_25|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_25|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_43, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_43, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_43, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_25|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_25|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_25|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_25|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_43, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_25|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_43, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_43} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 145583#L310-21 [3870] L310-21-->L310-23: Formula: (< v_~m_pc~0_24 1) InVars {~m_pc~0=v_~m_pc~0_24} OutVars{~m_pc~0=v_~m_pc~0_24} AuxVars[] AssignedVars[] 145955#L310-23 [2785] L310-23-->L321-7: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_47 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_47} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 145956#L321-7 [4303] L321-7-->L815-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 145853#L815-21 [2667] L815-21-->L815-23: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_48) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_48} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_48} AuxVars[] AssignedVars[] 145824#L815-23 [2638] L815-23-->L329-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 145825#L329-21 [3911] L329-21-->L329-23: Formula: (< v_~t1_pc~0_24 1) InVars {~t1_pc~0=v_~t1_pc~0_24} OutVars{~t1_pc~0=v_~t1_pc~0_24} AuxVars[] AssignedVars[] 146132#L329-23 [3052] L329-23-->L340-7: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 145988#L340-7 [4310] L340-7-->L823-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 145989#L823-21 [2931] L823-21-->L823-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} AuxVars[] AssignedVars[] 146060#L823-23 [2934] L823-23-->L348-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_25|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 146062#L348-21 [3953] L348-21-->L348-23: Formula: (> 1 v_~t2_pc~0_24) InVars {~t2_pc~0=v_~t2_pc~0_24} OutVars{~t2_pc~0=v_~t2_pc~0_24} AuxVars[] AssignedVars[] 146239#L348-23 [3319] L348-23-->L359-7: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 146259#L359-7 [4317] L359-7-->L831-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 148425#L831-21 [2490] L831-21-->L831-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} AuxVars[] AssignedVars[] 148426#L831-23 [3197] L831-23-->L367-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_25|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 148422#L367-21 [3995] L367-21-->L367-23: Formula: (> v_~t3_pc~0_24 1) InVars {~t3_pc~0=v_~t3_pc~0_24} OutVars{~t3_pc~0=v_~t3_pc~0_24} AuxVars[] AssignedVars[] 148421#L367-23 [2385] L367-23-->L378-7: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 148418#L378-7 [4324] L378-7-->L839-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 148419#L839-21 [4024] L839-21-->L839-23: Formula: (and (= v_~t3_st~0_21 0) (< v_ULTIMATE.start_activate_threads_~tmp___2~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} OutVars{~t3_st~0=v_~t3_st~0_21, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_47} AuxVars[] AssignedVars[~t3_st~0] 145897#L839-23 [2722] L839-23-->L386-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_49, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 145898#L386-21 [4038] L386-21-->L386-23: Formula: (> 1 v_~t4_pc~0_24) InVars {~t4_pc~0=v_~t4_pc~0_24} OutVars{~t4_pc~0=v_~t4_pc~0_24} AuxVars[] AssignedVars[] 149714#L386-23 [2623] L386-23-->L397-7: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 149713#L397-7 [4331] L397-7-->L847-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 149712#L847-21 [4065] L847-21-->L847-23: Formula: (and (= v_~t4_st~0_22 0) (< v_ULTIMATE.start_activate_threads_~tmp___3~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47, ~t4_st~0=v_~t4_st~0_22} AuxVars[] AssignedVars[~t4_st~0] 149711#L847-23 [2983] L847-23-->L405-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_25|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 149709#L405-21 [4080] L405-21-->L405-23: Formula: (> v_~t5_pc~0_24 1) InVars {~t5_pc~0=v_~t5_pc~0_24} OutVars{~t5_pc~0=v_~t5_pc~0_24} AuxVars[] AssignedVars[] 149708#L405-23 [2891] L405-23-->L416-7: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 149707#L416-7 [4338] L416-7-->L855-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 149706#L855-21 [3251] L855-21-->L855-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} AuxVars[] AssignedVars[] 149705#L855-23 [3257] L855-23-->L424-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_25|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 149704#L424-21 [4122] L424-21-->L424-23: Formula: (> 1 v_~t6_pc~0_24) InVars {~t6_pc~0=v_~t6_pc~0_24} OutVars{~t6_pc~0=v_~t6_pc~0_24} AuxVars[] AssignedVars[] 147330#L424-23 [3177] L424-23-->L435-7: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 149703#L435-7 [4340] L435-7-->L863-21: Formula: (and (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___5~0_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_35|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_41|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 149702#L863-21 [4135] L863-21-->L863-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___5~0_47 0) (= v_~t6_st~0_22 0)) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} OutVars{~t6_st~0=v_~t6_st~0_22, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} AuxVars[] AssignedVars[~t6_st~0] 149701#L863-23 [4138] L863-23-->L733-3: Formula: (> v_~M_E~0_35 1) InVars {~M_E~0=v_~M_E~0_35} OutVars{~M_E~0=v_~M_E~0_35} AuxVars[] AssignedVars[] 149700#L733-3 [3184] L733-3-->L738-3: Formula: (and (= v_~T1_E~0_15 1) (= v_~T1_E~0_14 2)) InVars {~T1_E~0=v_~T1_E~0_15} OutVars{~T1_E~0=v_~T1_E~0_14} AuxVars[] AssignedVars[~T1_E~0] 149699#L738-3 [4142] L738-3-->L743-3: Formula: (< 1 v_~T2_E~0_16) InVars {~T2_E~0=v_~T2_E~0_16} OutVars{~T2_E~0=v_~T2_E~0_16} AuxVars[] AssignedVars[] 149698#L743-3 [4143] L743-3-->L748-3: Formula: (< 1 v_~T3_E~0_16) InVars {~T3_E~0=v_~T3_E~0_16} OutVars{~T3_E~0=v_~T3_E~0_16} AuxVars[] AssignedVars[] 149697#L748-3 [4145] L748-3-->L753-3: Formula: (> v_~T4_E~0_16 1) InVars {~T4_E~0=v_~T4_E~0_16} OutVars{~T4_E~0=v_~T4_E~0_16} AuxVars[] AssignedVars[] 149696#L753-3 [4148] L753-3-->L758-3: Formula: (< 1 v_~T5_E~0_16) InVars {~T5_E~0=v_~T5_E~0_16} OutVars{~T5_E~0=v_~T5_E~0_16} AuxVars[] AssignedVars[] 149695#L758-3 [4149] L758-3-->L763-3: Formula: (> v_~T6_E~0_16 1) InVars {~T6_E~0=v_~T6_E~0_16} OutVars{~T6_E~0=v_~T6_E~0_16} AuxVars[] AssignedVars[] 149694#L763-3 [4151] L763-3-->L768-3: Formula: (< 1 v_~E_1~0_36) InVars {~E_1~0=v_~E_1~0_36} OutVars{~E_1~0=v_~E_1~0_36} AuxVars[] AssignedVars[] 149693#L768-3 [4154] L768-3-->L773-3: Formula: (< 1 v_~E_2~0_36) InVars {~E_2~0=v_~E_2~0_36} OutVars{~E_2~0=v_~E_2~0_36} AuxVars[] AssignedVars[] 149692#L773-3 [4156] L773-3-->L778-3: Formula: (< 1 v_~E_3~0_36) InVars {~E_3~0=v_~E_3~0_36} OutVars{~E_3~0=v_~E_3~0_36} AuxVars[] AssignedVars[] 149691#L778-3 [3308] L778-3-->L783-3: Formula: (and (= 1 v_~E_4~0_35) (= v_~E_4~0_34 2)) InVars {~E_4~0=v_~E_4~0_35} OutVars{~E_4~0=v_~E_4~0_34} AuxVars[] AssignedVars[~E_4~0] 149690#L783-3 [4160] L783-3-->L788-3: Formula: (< 1 v_~E_5~0_36) InVars {~E_5~0=v_~E_5~0_36} OutVars{~E_5~0=v_~E_5~0_36} AuxVars[] AssignedVars[] 149689#L788-3 [4162] L788-3-->L793-3: Formula: (< 1 v_~E_6~0_36) InVars {~E_6~0=v_~E_6~0_36} OutVars{~E_6~0=v_~E_6~0_36} AuxVars[] AssignedVars[] 149688#L793-3 [2966] L793-3-->L494-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_30} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 149687#L494-1 [2878] L494-1-->L531-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33 1) (= 0 v_~m_st~0_21)) InVars {~m_st~0=v_~m_st~0_21} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33, ~m_st~0=v_~m_st~0_21} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 149679#L531-1 [4341] L531-1-->L1033: Formula: (and (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp~3] 149676#L1033 [4169] L1033-->L1033-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_6) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} AuxVars[] AssignedVars[] 149674#L1033-1 [2919] L1033-1-->L494-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_3|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_6, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_exists_runnable_thread_~__retres1~7, ULTIMATE.start_stop_simulation_#res] 149667#L494-2 [2882] L494-2-->L531-2: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9 1) (= v_~m_st~0_6 0)) InVars {~m_st~0=v_~m_st~0_6} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9, ~m_st~0=v_~m_st~0_6} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 149666#L531-2 [4343] L531-2-->L988: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 149665#L988 [3240] L988-->L995: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 149664#L995 [4354] L995-->L1014-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_6|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_#t~ret17, ULTIMATE.start_stop_simulation_#res] 146204#L1014-1 [2020-06-22 00:13:31,770 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:31,770 INFO L82 PathProgramCache]: Analyzing trace with hash -1932600016, now seen corresponding path program 3 times [2020-06-22 00:13:31,770 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:31,770 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:31,771 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:31,771 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:31,771 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:31,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:13:31,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:13:31,794 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:31,794 INFO L82 PathProgramCache]: Analyzing trace with hash 1616308662, now seen corresponding path program 1 times [2020-06-22 00:13:31,794 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:31,794 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:31,795 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:31,795 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2020-06-22 00:13:31,795 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:31,800 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:31,830 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:31,830 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:31,831 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2020-06-22 00:13:31,831 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-06-22 00:13:31,831 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2020-06-22 00:13:31,831 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2020-06-22 00:13:31,831 INFO L87 Difference]: Start difference. First operand 6344 states and 10229 transitions. cyclomatic complexity: 3886 Second operand 6 states. [2020-06-22 00:13:32,503 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-06-22 00:13:32,503 INFO L93 Difference]: Finished difference Result 6506 states and 10454 transitions. [2020-06-22 00:13:32,503 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2020-06-22 00:13:32,504 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6506 states and 10454 transitions. [2020-06-22 00:13:32,524 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 6432 [2020-06-22 00:13:32,537 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6506 states to 6506 states and 10454 transitions. [2020-06-22 00:13:32,537 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6506 [2020-06-22 00:13:32,540 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6506 [2020-06-22 00:13:32,540 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6506 states and 10454 transitions. [2020-06-22 00:13:32,544 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-06-22 00:13:32,544 INFO L706 BuchiCegarLoop]: Abstraction has 6506 states and 10454 transitions. [2020-06-22 00:13:32,546 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6506 states and 10454 transitions. [2020-06-22 00:13:32,594 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6506 to 6344. [2020-06-22 00:13:32,594 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6344 states. [2020-06-22 00:13:32,604 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6344 states to 6344 states and 10068 transitions. [2020-06-22 00:13:32,605 INFO L729 BuchiCegarLoop]: Abstraction has 6344 states and 10068 transitions. [2020-06-22 00:13:32,605 INFO L609 BuchiCegarLoop]: Abstraction has 6344 states and 10068 transitions. [2020-06-22 00:13:32,605 INFO L442 BuchiCegarLoop]: ======== Iteration 35============ [2020-06-22 00:13:32,605 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6344 states and 10068 transitions. [2020-06-22 00:13:32,619 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 6272 [2020-06-22 00:13:32,619 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-06-22 00:13:32,619 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-06-22 00:13:32,621 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:32,621 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:32,622 INFO L794 eck$LassoCheckResult]: Stem: 158939#ULTIMATE.startENTRY [4266] ULTIMATE.startENTRY-->L444: Formula: (and (= 1 v_~t6_i~0_7) (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~M_E~0_37 2) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 0 v_~t6_pc~0_26) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_6~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= v_~T6_E~0_18 2) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~t6_st~0_24) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t6_pc~0=v_~t6_pc~0_26, ~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~T6_E~0=v_~T6_E~0_18, ~M_E~0=v_~M_E~0_37, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ~T4_E~0=v_~T4_E~0_18, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_4|, ~t6_i~0=v_~t6_i~0_7, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ULTIMATE.start_main_~__retres1~8=v_ULTIMATE.start_main_~__retres1~8_6, ~T2_E~0=v_~T2_E~0_18, ~t6_st~0=v_~t6_st~0_24, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_6~0=v_~E_6~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t6_pc~0, ~t5_i~0, ~t1_pc~0, ~t5_st~0, ~T6_E~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ~T4_E~0, ULTIMATE.start_start_simulation_#t~ret17, ~t6_i~0, ~t2_st~0, ~t2_pc~0, ULTIMATE.start_main_~__retres1~8, ~T2_E~0, ~t6_st~0, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_6~0, ULTIMATE.start_main_#res, ~E_2~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 158533#L444 [2453] L444-->L451-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 158534#L451-1 [3030] L451-1-->L456-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 158627#L456-1 [2574] L456-1-->L461-1: Formula: (and (= v_~t2_st~0_2 0) (= 1 v_~t2_i~0_3)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_2} AuxVars[] AssignedVars[~t2_st~0] 158628#L461-1 [2880] L461-1-->L466-1: Formula: (and (= v_~t3_st~0_3 0) (= v_~t3_i~0_3 1)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_3, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 158538#L466-1 [2457] L466-1-->L471-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 158539#L471-1 [3209] L471-1-->L476-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 158781#L476-1 [2761] L476-1-->L481-1: Formula: (and (= 1 v_~t6_i~0_3) (= v_~t6_st~0_4 0)) InVars {~t6_i~0=v_~t6_i~0_3} OutVars{~t6_st~0=v_~t6_st~0_4, ~t6_i~0=v_~t6_i~0_3} AuxVars[] AssignedVars[~t6_st~0] 158782#L481-1 [3652] L481-1-->L660-1: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 158960#L660-1 [3654] L660-1-->L665-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 158452#L665-1 [3655] L665-1-->L670-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 158453#L670-1 [3658] L670-1-->L675-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 158545#L675-1 [3659] L675-1-->L680-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 158546#L680-1 [3661] L680-1-->L685-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 158793#L685-1 [3663] L685-1-->L690-1: Formula: (< 0 v_~T6_E~0_4) InVars {~T6_E~0=v_~T6_E~0_4} OutVars{~T6_E~0=v_~T6_E~0_4} AuxVars[] AssignedVars[] 158794#L690-1 [3665] L690-1-->L695-1: Formula: (> v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 158667#L695-1 [3668] L695-1-->L700-1: Formula: (> v_~E_2~0_6 0) InVars {~E_2~0=v_~E_2~0_6} OutVars{~E_2~0=v_~E_2~0_6} AuxVars[] AssignedVars[] 158668#L700-1 [3670] L700-1-->L705-1: Formula: (> v_~E_3~0_6 0) InVars {~E_3~0=v_~E_3~0_6} OutVars{~E_3~0=v_~E_3~0_6} AuxVars[] AssignedVars[] 158921#L705-1 [3672] L705-1-->L710-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 158607#L710-1 [3674] L710-1-->L715-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 158608#L715-1 [3675] L715-1-->L720-1: Formula: (> v_~E_6~0_4 0) InVars {~E_6~0=v_~E_6~0_4} OutVars{~E_6~0=v_~E_6~0_4} AuxVars[] AssignedVars[] 158488#L720-1 [2412] L720-1-->L310: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_7, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_4|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_4|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_7, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_4, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_4, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_2|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_2|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_4|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_4|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_7, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_2|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_4} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 158489#L310 [3678] L310-->L310-2: Formula: (< v_~m_pc~0_5 1) InVars {~m_pc~0=v_~m_pc~0_5} OutVars{~m_pc~0=v_~m_pc~0_5} AuxVars[] AssignedVars[] 158640#L310-2 [2805] L310-2-->L321: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_11 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 158635#L321 [4267] L321-->L815: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 158636#L815 [2976] L815-->L815-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_12) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} AuxVars[] AssignedVars[] 158917#L815-2 [2961] L815-2-->L329: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 158841#L329 [3683] L329-->L329-2: Formula: (< v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 158842#L329-2 [2861] L329-2-->L340: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 158837#L340 [4268] L340-->L823: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 158838#L823 [3234] L823-->L823-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} AuxVars[] AssignedVars[] 159049#L823-2 [3235] L823-2-->L348: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_4|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 159021#L348 [3690] L348-->L348-2: Formula: (< v_~t2_pc~0_5 1) InVars {~t2_pc~0=v_~t2_pc~0_5} OutVars{~t2_pc~0=v_~t2_pc~0_5} AuxVars[] AssignedVars[] 159023#L348-2 [3153] L348-2-->L359: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 159019#L359 [4269] L359-->L831: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 158615#L831 [2537] L831-->L831-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} AuxVars[] AssignedVars[] 158602#L831-2 [2520] L831-2-->L367: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_4|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 158541#L367 [3695] L367-->L367-2: Formula: (> 1 v_~t3_pc~0_5) InVars {~t3_pc~0=v_~t3_pc~0_5} OutVars{~t3_pc~0=v_~t3_pc~0_5} AuxVars[] AssignedVars[] 158518#L367-2 [2438] L367-2-->L378: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 158519#L378 [4270] L378-->L839: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 158540#L839 [2791] L839-->L839-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} AuxVars[] AssignedVars[] 158803#L839-2 [2794] L839-2-->L386: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_7, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 158722#L386 [3702] L386-->L386-2: Formula: (< v_~t4_pc~0_5 1) InVars {~t4_pc~0=v_~t4_pc~0_5} OutVars{~t4_pc~0=v_~t4_pc~0_5} AuxVars[] AssignedVars[] 158723#L386-2 [2680] L386-2-->L397: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 158720#L397 [4271] L397-->L847: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 158721#L847 [3084] L847-->L847-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} AuxVars[] AssignedVars[] 158968#L847-2 [3064] L847-2-->L405: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_4|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 158969#L405 [3708] L405-->L405-2: Formula: (> 1 v_~t5_pc~0_5) InVars {~t5_pc~0=v_~t5_pc~0_5} OutVars{~t5_pc~0=v_~t5_pc~0_5} AuxVars[] AssignedVars[] 158869#L405-2 [2940] L405-2-->L416: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 158901#L416 [4272] L416-->L855: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 158981#L855 [3091] L855-->L855-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_12} AuxVars[] AssignedVars[] 158982#L855-2 [3093] L855-2-->L424: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_4|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 158587#L424 [3713] L424-->L424-2: Formula: (< v_~t6_pc~0_5 1) InVars {~t6_pc~0=v_~t6_pc~0_5} OutVars{~t6_pc~0=v_~t6_pc~0_5} AuxVars[] AssignedVars[] 158588#L424-2 [2503] L424-2-->L435: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 158584#L435 [4273] L435-->L863: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___5~0_49 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_28|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_28|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 158502#L863 [2425] L863-->L863-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___5~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} AuxVars[] AssignedVars[] 158475#L863-2 [3719] L863-2-->L733-1: Formula: (> v_~M_E~0_15 1) InVars {~M_E~0=v_~M_E~0_15} OutVars{~M_E~0=v_~M_E~0_15} AuxVars[] AssignedVars[] 158476#L733-1 [3722] L733-1-->L738-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 158919#L738-1 [3723] L738-1-->L743-1: Formula: (< 1 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 158605#L743-1 [3726] L743-1-->L748-1: Formula: (< 1 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 158606#L748-1 [3728] L748-1-->L753-1: Formula: (> v_~T4_E~0_10 1) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 158483#L753-1 [3729] L753-1-->L758-1: Formula: (< 1 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 158484#L758-1 [3731] L758-1-->L763-1: Formula: (> v_~T6_E~0_10 1) InVars {~T6_E~0=v_~T6_E~0_10} OutVars{~T6_E~0=v_~T6_E~0_10} AuxVars[] AssignedVars[] 158557#L763-1 [3733] L763-1-->L768-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 158558#L768-1 [3736] L768-1-->L773-1: Formula: (< 1 v_~E_2~0_14) InVars {~E_2~0=v_~E_2~0_14} OutVars{~E_2~0=v_~E_2~0_14} AuxVars[] AssignedVars[] 158785#L773-1 [3737] L773-1-->L778-1: Formula: (< 1 v_~E_3~0_14) InVars {~E_3~0=v_~E_3~0_14} OutVars{~E_3~0=v_~E_3~0_14} AuxVars[] AssignedVars[] 158786#L778-1 [3740] L778-1-->L783-1: Formula: (< 1 v_~E_4~0_14) InVars {~E_4~0=v_~E_4~0_14} OutVars{~E_4~0=v_~E_4~0_14} AuxVars[] AssignedVars[] 158659#L783-1 [3741] L783-1-->L788-1: Formula: (< 1 v_~E_5~0_14) InVars {~E_5~0=v_~E_5~0_14} OutVars{~E_5~0=v_~E_5~0_14} AuxVars[] AssignedVars[] 158660#L788-1 [3744] L788-1-->L1014-1: Formula: (< 1 v_~E_6~0_14) InVars {~E_6~0=v_~E_6~0_14} OutVars{~E_6~0=v_~E_6~0_14} AuxVars[] AssignedVars[] 158496#L1014-1 [2020-06-22 00:13:32,623 INFO L796 eck$LassoCheckResult]: Loop: 158496#L1014-1 [4274] L1014-1-->L635: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp_ndt_7~0=v_ULTIMATE.start_eval_~tmp_ndt_7~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp_ndt_7~0] 158694#L635 [4275] L635-->L494: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_37} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 160282#L494 [3745] L494-->L498: Formula: (< v_~m_st~0_9 0) InVars {~m_st~0=v_~m_st~0_9} OutVars{~m_st~0=v_~m_st~0_9} AuxVars[] AssignedVars[] 160275#L498 [3749] L498-->L502: Formula: (< v_~t1_st~0_9 0) InVars {~t1_st~0=v_~t1_st~0_9} OutVars{~t1_st~0=v_~t1_st~0_9} AuxVars[] AssignedVars[] 160276#L502 [3753] L502-->L506: Formula: (> v_~t2_st~0_9 0) InVars {~t2_st~0=v_~t2_st~0_9} OutVars{~t2_st~0=v_~t2_st~0_9} AuxVars[] AssignedVars[] 160277#L506 [3760] L506-->L510: Formula: (< 0 v_~t3_st~0_10) InVars {~t3_st~0=v_~t3_st~0_10} OutVars{~t3_st~0=v_~t3_st~0_10} AuxVars[] AssignedVars[] 160278#L510 [3765] L510-->L514: Formula: (> 0 v_~t4_st~0_11) InVars {~t4_st~0=v_~t4_st~0_11} OutVars{~t4_st~0=v_~t4_st~0_11} AuxVars[] AssignedVars[] 160281#L514 [3773] L514-->L518: Formula: (> v_~t5_st~0_11 0) InVars {~t5_st~0=v_~t5_st~0_11} OutVars{~t5_st~0=v_~t5_st~0_11} AuxVars[] AssignedVars[] 160279#L518 [3783] L518-->L531: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_28 0) (< 0 v_~t6_st~0_11)) InVars {~t6_st~0=v_~t6_st~0_11} OutVars{~t6_st~0=v_~t6_st~0_11, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_28} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 160280#L531 [4276] L531-->L546: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 164577#L546 [4278] L546-->L660-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 164576#L660-2 [3747] L660-2-->L660-4: Formula: (> v_~M_E~0_30 0) InVars {~M_E~0=v_~M_E~0_30} OutVars{~M_E~0=v_~M_E~0_30} AuxVars[] AssignedVars[] 164575#L660-4 [3058] L660-4-->L665-3: Formula: (and (= v_~T1_E~0_11 1) (= v_~T1_E~0_12 0)) InVars {~T1_E~0=v_~T1_E~0_12} OutVars{~T1_E~0=v_~T1_E~0_11} AuxVars[] AssignedVars[~T1_E~0] 164574#L665-3 [3756] L665-3-->L670-3: Formula: (< 0 v_~T2_E~0_13) InVars {~T2_E~0=v_~T2_E~0_13} OutVars{~T2_E~0=v_~T2_E~0_13} AuxVars[] AssignedVars[] 164573#L670-3 [3762] L670-3-->L675-3: Formula: (< 0 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 164572#L675-3 [3768] L675-3-->L680-3: Formula: (> v_~T4_E~0_13 0) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 164571#L680-3 [3776] L680-3-->L685-3: Formula: (< 0 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 164570#L685-3 [3785] L685-3-->L690-3: Formula: (> v_~T6_E~0_13 0) InVars {~T6_E~0=v_~T6_E~0_13} OutVars{~T6_E~0=v_~T6_E~0_13} AuxVars[] AssignedVars[] 164569#L690-3 [3795] L690-3-->L695-3: Formula: (< 0 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 164567#L695-3 [3805] L695-3-->L700-3: Formula: (< 0 v_~E_2~0_31) InVars {~E_2~0=v_~E_2~0_31} OutVars{~E_2~0=v_~E_2~0_31} AuxVars[] AssignedVars[] 164565#L700-3 [3818] L700-3-->L705-3: Formula: (< 0 v_~E_3~0_31) InVars {~E_3~0=v_~E_3~0_31} OutVars{~E_3~0=v_~E_3~0_31} AuxVars[] AssignedVars[] 164563#L705-3 [2688] L705-3-->L710-3: Formula: (and (= v_~E_4~0_29 1) (= 0 v_~E_4~0_30)) InVars {~E_4~0=v_~E_4~0_30} OutVars{~E_4~0=v_~E_4~0_29} AuxVars[] AssignedVars[~E_4~0] 164562#L710-3 [3844] L710-3-->L715-3: Formula: (< 0 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 158961#L715-3 [3854] L715-3-->L720-3: Formula: (< 0 v_~E_6~0_31) InVars {~E_6~0=v_~E_6~0_31} OutVars{~E_6~0=v_~E_6~0_31} AuxVars[] AssignedVars[] 158459#L720-3 [2388] L720-3-->L310-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_43, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_43, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_25|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_25|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_25|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_43, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_43, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_43, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_25|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_25|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_25|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_25|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_43, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_25|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_43, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_43} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 158460#L310-21 [3870] L310-21-->L310-23: Formula: (< v_~m_pc~0_24 1) InVars {~m_pc~0=v_~m_pc~0_24} OutVars{~m_pc~0=v_~m_pc~0_24} AuxVars[] AssignedVars[] 158795#L310-23 [2785] L310-23-->L321-7: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_47 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_47} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 164584#L321-7 [4303] L321-7-->L815-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 164406#L815-21 [2667] L815-21-->L815-23: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_48) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_48} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_48} AuxVars[] AssignedVars[] 164174#L815-23 [2638] L815-23-->L329-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 158955#L329-21 [3911] L329-21-->L329-23: Formula: (< v_~t1_pc~0_24 1) InVars {~t1_pc~0=v_~t1_pc~0_24} OutVars{~t1_pc~0=v_~t1_pc~0_24} AuxVars[] AssignedVars[] 158956#L329-23 [3052] L329-23-->L340-7: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 164202#L340-7 [4310] L340-7-->L823-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 164201#L823-21 [2931] L823-21-->L823-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} AuxVars[] AssignedVars[] 164200#L823-23 [2934] L823-23-->L348-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_25|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 164198#L348-21 [3953] L348-21-->L348-23: Formula: (> 1 v_~t2_pc~0_24) InVars {~t2_pc~0=v_~t2_pc~0_24} OutVars{~t2_pc~0=v_~t2_pc~0_24} AuxVars[] AssignedVars[] 164197#L348-23 [3319] L348-23-->L359-7: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 164196#L359-7 [4317] L359-7-->L831-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 164195#L831-21 [2490] L831-21-->L831-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} AuxVars[] AssignedVars[] 164194#L831-23 [3197] L831-23-->L367-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_25|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 158485#L367-21 [3995] L367-21-->L367-23: Formula: (> v_~t3_pc~0_24 1) InVars {~t3_pc~0=v_~t3_pc~0_24} OutVars{~t3_pc~0=v_~t3_pc~0_24} AuxVars[] AssignedVars[] 158454#L367-23 [2385] L367-23-->L378-7: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 158455#L378-7 [4324] L378-7-->L839-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 158510#L839-21 [2715] L839-21-->L839-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_48} AuxVars[] AssignedVars[] 158747#L839-23 [2722] L839-23-->L386-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_49, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 158663#L386-21 [4038] L386-21-->L386-23: Formula: (> 1 v_~t4_pc~0_24) InVars {~t4_pc~0=v_~t4_pc~0_24} OutVars{~t4_pc~0=v_~t4_pc~0_24} AuxVars[] AssignedVars[] 158664#L386-23 [2623] L386-23-->L397-7: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 164568#L397-7 [4331] L397-7-->L847-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 164566#L847-21 [4065] L847-21-->L847-23: Formula: (and (= v_~t4_st~0_22 0) (< v_ULTIMATE.start_activate_threads_~tmp___3~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47, ~t4_st~0=v_~t4_st~0_22} AuxVars[] AssignedVars[~t4_st~0] 164564#L847-23 [2983] L847-23-->L405-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_25|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 164536#L405-21 [4080] L405-21-->L405-23: Formula: (> v_~t5_pc~0_24 1) InVars {~t5_pc~0=v_~t5_pc~0_24} OutVars{~t5_pc~0=v_~t5_pc~0_24} AuxVars[] AssignedVars[] 164533#L405-23 [2891] L405-23-->L416-7: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 164531#L416-7 [4338] L416-7-->L855-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 164529#L855-21 [3251] L855-21-->L855-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} AuxVars[] AssignedVars[] 164527#L855-23 [3257] L855-23-->L424-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_25|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 159031#L424-21 [4122] L424-21-->L424-23: Formula: (> 1 v_~t6_pc~0_24) InVars {~t6_pc~0=v_~t6_pc~0_24} OutVars{~t6_pc~0=v_~t6_pc~0_24} AuxVars[] AssignedVars[] 159032#L424-23 [3177] L424-23-->L435-7: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 158571#L435-7 [4340] L435-7-->L863-21: Formula: (and (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___5~0_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_35|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_41|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 158572#L863-21 [4135] L863-21-->L863-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___5~0_47 0) (= v_~t6_st~0_22 0)) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} OutVars{~t6_st~0=v_~t6_st~0_22, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} AuxVars[] AssignedVars[~t6_st~0] 158616#L863-23 [4138] L863-23-->L733-3: Formula: (> v_~M_E~0_35 1) InVars {~M_E~0=v_~M_E~0_35} OutVars{~M_E~0=v_~M_E~0_35} AuxVars[] AssignedVars[] 158617#L733-3 [3184] L733-3-->L738-3: Formula: (and (= v_~T1_E~0_15 1) (= v_~T1_E~0_14 2)) InVars {~T1_E~0=v_~T1_E~0_15} OutVars{~T1_E~0=v_~T1_E~0_14} AuxVars[] AssignedVars[~T1_E~0] 158922#L738-3 [4142] L738-3-->L743-3: Formula: (< 1 v_~T2_E~0_16) InVars {~T2_E~0=v_~T2_E~0_16} OutVars{~T2_E~0=v_~T2_E~0_16} AuxVars[] AssignedVars[] 158595#L743-3 [4143] L743-3-->L748-3: Formula: (< 1 v_~T3_E~0_16) InVars {~T3_E~0=v_~T3_E~0_16} OutVars{~T3_E~0=v_~T3_E~0_16} AuxVars[] AssignedVars[] 158596#L748-3 [4145] L748-3-->L753-3: Formula: (> v_~T4_E~0_16 1) InVars {~T4_E~0=v_~T4_E~0_16} OutVars{~T4_E~0=v_~T4_E~0_16} AuxVars[] AssignedVars[] 158958#L753-3 [4148] L753-3-->L758-3: Formula: (< 1 v_~T5_E~0_16) InVars {~T5_E~0=v_~T5_E~0_16} OutVars{~T5_E~0=v_~T5_E~0_16} AuxVars[] AssignedVars[] 164446#L758-3 [4149] L758-3-->L763-3: Formula: (> v_~T6_E~0_16 1) InVars {~T6_E~0=v_~T6_E~0_16} OutVars{~T6_E~0=v_~T6_E~0_16} AuxVars[] AssignedVars[] 164444#L763-3 [4151] L763-3-->L768-3: Formula: (< 1 v_~E_1~0_36) InVars {~E_1~0=v_~E_1~0_36} OutVars{~E_1~0=v_~E_1~0_36} AuxVars[] AssignedVars[] 164442#L768-3 [4154] L768-3-->L773-3: Formula: (< 1 v_~E_2~0_36) InVars {~E_2~0=v_~E_2~0_36} OutVars{~E_2~0=v_~E_2~0_36} AuxVars[] AssignedVars[] 164440#L773-3 [4156] L773-3-->L778-3: Formula: (< 1 v_~E_3~0_36) InVars {~E_3~0=v_~E_3~0_36} OutVars{~E_3~0=v_~E_3~0_36} AuxVars[] AssignedVars[] 164439#L778-3 [3308] L778-3-->L783-3: Formula: (and (= 1 v_~E_4~0_35) (= v_~E_4~0_34 2)) InVars {~E_4~0=v_~E_4~0_35} OutVars{~E_4~0=v_~E_4~0_34} AuxVars[] AssignedVars[~E_4~0] 164437#L783-3 [4160] L783-3-->L788-3: Formula: (< 1 v_~E_5~0_36) InVars {~E_5~0=v_~E_5~0_36} OutVars{~E_5~0=v_~E_5~0_36} AuxVars[] AssignedVars[] 164435#L788-3 [4162] L788-3-->L793-3: Formula: (< 1 v_~E_6~0_36) InVars {~E_6~0=v_~E_6~0_36} OutVars{~E_6~0=v_~E_6~0_36} AuxVars[] AssignedVars[] 164223#L793-3 [2966] L793-3-->L494-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_30} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 164215#L494-1 [2878] L494-1-->L531-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33 1) (= 0 v_~m_st~0_21)) InVars {~m_st~0=v_~m_st~0_21} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33, ~m_st~0=v_~m_st~0_21} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 164207#L531-1 [4341] L531-1-->L1033: Formula: (and (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp~3] 164203#L1033 [4169] L1033-->L1033-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_6) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} AuxVars[] AssignedVars[] 158499#L1033-1 [2919] L1033-1-->L494-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_3|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_6, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_exists_runnable_thread_~__retres1~7, ULTIMATE.start_stop_simulation_#res] 158867#L494-2 [2882] L494-2-->L531-2: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9 1) (= v_~m_st~0_6 0)) InVars {~m_st~0=v_~m_st~0_6} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9, ~m_st~0=v_~m_st~0_6} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 158537#L531-2 [4343] L531-2-->L988: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 158780#L988 [3240] L988-->L995: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 158495#L995 [4354] L995-->L1014-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_6|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_#t~ret17, ULTIMATE.start_stop_simulation_#res] 158496#L1014-1 [2020-06-22 00:13:32,623 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:32,624 INFO L82 PathProgramCache]: Analyzing trace with hash -1932600016, now seen corresponding path program 4 times [2020-06-22 00:13:32,624 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:32,624 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:32,625 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:32,625 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:32,625 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:32,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:13:32,634 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:13:32,644 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:32,645 INFO L82 PathProgramCache]: Analyzing trace with hash -1125379917, now seen corresponding path program 1 times [2020-06-22 00:13:32,645 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:32,645 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:32,645 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:32,646 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2020-06-22 00:13:32,646 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:32,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:32,679 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:32,679 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:32,679 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2020-06-22 00:13:32,680 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-06-22 00:13:32,680 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2020-06-22 00:13:32,680 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2020-06-22 00:13:32,680 INFO L87 Difference]: Start difference. First operand 6344 states and 10068 transitions. cyclomatic complexity: 3725 Second operand 6 states. [2020-06-22 00:13:33,361 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-06-22 00:13:33,362 INFO L93 Difference]: Finished difference Result 6506 states and 10341 transitions. [2020-06-22 00:13:33,362 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2020-06-22 00:13:33,362 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6506 states and 10341 transitions. [2020-06-22 00:13:33,387 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 6432 [2020-06-22 00:13:33,403 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6506 states to 6506 states and 10341 transitions. [2020-06-22 00:13:33,403 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6506 [2020-06-22 00:13:33,406 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6506 [2020-06-22 00:13:33,406 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6506 states and 10341 transitions. [2020-06-22 00:13:33,411 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-06-22 00:13:33,411 INFO L706 BuchiCegarLoop]: Abstraction has 6506 states and 10341 transitions. [2020-06-22 00:13:33,414 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6506 states and 10341 transitions. [2020-06-22 00:13:33,528 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6506 to 6344. [2020-06-22 00:13:33,528 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6344 states. [2020-06-22 00:13:33,539 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6344 states to 6344 states and 9955 transitions. [2020-06-22 00:13:33,539 INFO L729 BuchiCegarLoop]: Abstraction has 6344 states and 9955 transitions. [2020-06-22 00:13:33,540 INFO L609 BuchiCegarLoop]: Abstraction has 6344 states and 9955 transitions. [2020-06-22 00:13:33,540 INFO L442 BuchiCegarLoop]: ======== Iteration 36============ [2020-06-22 00:13:33,540 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6344 states and 9955 transitions. [2020-06-22 00:13:33,556 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 6272 [2020-06-22 00:13:33,556 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-06-22 00:13:33,556 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-06-22 00:13:33,558 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:33,558 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:33,559 INFO L794 eck$LassoCheckResult]: Stem: 171804#ULTIMATE.startENTRY [4266] ULTIMATE.startENTRY-->L444: Formula: (and (= 1 v_~t6_i~0_7) (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~M_E~0_37 2) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 0 v_~t6_pc~0_26) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_6~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= v_~T6_E~0_18 2) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~t6_st~0_24) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t6_pc~0=v_~t6_pc~0_26, ~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~T6_E~0=v_~T6_E~0_18, ~M_E~0=v_~M_E~0_37, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ~T4_E~0=v_~T4_E~0_18, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_4|, ~t6_i~0=v_~t6_i~0_7, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ULTIMATE.start_main_~__retres1~8=v_ULTIMATE.start_main_~__retres1~8_6, ~T2_E~0=v_~T2_E~0_18, ~t6_st~0=v_~t6_st~0_24, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_6~0=v_~E_6~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t6_pc~0, ~t5_i~0, ~t1_pc~0, ~t5_st~0, ~T6_E~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ~T4_E~0, ULTIMATE.start_start_simulation_#t~ret17, ~t6_i~0, ~t2_st~0, ~t2_pc~0, ULTIMATE.start_main_~__retres1~8, ~T2_E~0, ~t6_st~0, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_6~0, ULTIMATE.start_main_#res, ~E_2~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 171409#L444 [2453] L444-->L451-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 171410#L451-1 [3030] L451-1-->L456-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 171494#L456-1 [2574] L456-1-->L461-1: Formula: (and (= v_~t2_st~0_2 0) (= 1 v_~t2_i~0_3)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_2} AuxVars[] AssignedVars[~t2_st~0] 171495#L461-1 [2880] L461-1-->L466-1: Formula: (and (= v_~t3_st~0_3 0) (= v_~t3_i~0_3 1)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_3, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 171414#L466-1 [2457] L466-1-->L471-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 171415#L471-1 [3209] L471-1-->L476-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 171644#L476-1 [2761] L476-1-->L481-1: Formula: (and (= 1 v_~t6_i~0_3) (= v_~t6_st~0_4 0)) InVars {~t6_i~0=v_~t6_i~0_3} OutVars{~t6_st~0=v_~t6_st~0_4, ~t6_i~0=v_~t6_i~0_3} AuxVars[] AssignedVars[~t6_st~0] 171645#L481-1 [3652] L481-1-->L660-1: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 171820#L660-1 [3654] L660-1-->L665-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 171329#L665-1 [3655] L665-1-->L670-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 171330#L670-1 [3658] L670-1-->L675-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 171421#L675-1 [3659] L675-1-->L680-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 171422#L680-1 [3661] L680-1-->L685-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 171657#L685-1 [3663] L685-1-->L690-1: Formula: (< 0 v_~T6_E~0_4) InVars {~T6_E~0=v_~T6_E~0_4} OutVars{~T6_E~0=v_~T6_E~0_4} AuxVars[] AssignedVars[] 171658#L690-1 [3665] L690-1-->L695-1: Formula: (> v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 171534#L695-1 [3668] L695-1-->L700-1: Formula: (> v_~E_2~0_6 0) InVars {~E_2~0=v_~E_2~0_6} OutVars{~E_2~0=v_~E_2~0_6} AuxVars[] AssignedVars[] 171535#L700-1 [3670] L700-1-->L705-1: Formula: (> v_~E_3~0_6 0) InVars {~E_3~0=v_~E_3~0_6} OutVars{~E_3~0=v_~E_3~0_6} AuxVars[] AssignedVars[] 171786#L705-1 [3672] L705-1-->L710-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 171478#L710-1 [3674] L710-1-->L715-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 171479#L715-1 [3675] L715-1-->L720-1: Formula: (> v_~E_6~0_4 0) InVars {~E_6~0=v_~E_6~0_4} OutVars{~E_6~0=v_~E_6~0_4} AuxVars[] AssignedVars[] 171365#L720-1 [2412] L720-1-->L310: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_7, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_4|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_4|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_7, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_4, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_4, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_2|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_2|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_4|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_4|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_7, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_2|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_4} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 171366#L310 [3678] L310-->L310-2: Formula: (< v_~m_pc~0_5 1) InVars {~m_pc~0=v_~m_pc~0_5} OutVars{~m_pc~0=v_~m_pc~0_5} AuxVars[] AssignedVars[] 171507#L310-2 [2805] L310-2-->L321: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_11 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 171502#L321 [4267] L321-->L815: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 171503#L815 [2976] L815-->L815-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_12) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} AuxVars[] AssignedVars[] 171782#L815-2 [2961] L815-2-->L329: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 171709#L329 [3683] L329-->L329-2: Formula: (< v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 171710#L329-2 [2861] L329-2-->L340: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 171705#L340 [4268] L340-->L823: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 171706#L823 [3234] L823-->L823-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} AuxVars[] AssignedVars[] 171901#L823-2 [3235] L823-2-->L348: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_4|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 171874#L348 [3690] L348-->L348-2: Formula: (< v_~t2_pc~0_5 1) InVars {~t2_pc~0=v_~t2_pc~0_5} OutVars{~t2_pc~0=v_~t2_pc~0_5} AuxVars[] AssignedVars[] 171876#L348-2 [3153] L348-2-->L359: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 171871#L359 [4269] L359-->L831: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 171485#L831 [2537] L831-->L831-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} AuxVars[] AssignedVars[] 171473#L831-2 [2520] L831-2-->L367: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_4|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 171417#L367 [3695] L367-->L367-2: Formula: (> 1 v_~t3_pc~0_5) InVars {~t3_pc~0=v_~t3_pc~0_5} OutVars{~t3_pc~0=v_~t3_pc~0_5} AuxVars[] AssignedVars[] 171394#L367-2 [2438] L367-2-->L378: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 171395#L378 [4270] L378-->L839: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 171416#L839 [2791] L839-->L839-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} AuxVars[] AssignedVars[] 171669#L839-2 [2794] L839-2-->L386: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_7, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 171584#L386 [3702] L386-->L386-2: Formula: (< v_~t4_pc~0_5 1) InVars {~t4_pc~0=v_~t4_pc~0_5} OutVars{~t4_pc~0=v_~t4_pc~0_5} AuxVars[] AssignedVars[] 171585#L386-2 [2680] L386-2-->L397: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 171582#L397 [4271] L397-->L847: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 171583#L847 [3084] L847-->L847-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} AuxVars[] AssignedVars[] 171827#L847-2 [3064] L847-2-->L405: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_4|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 171828#L405 [3708] L405-->L405-2: Formula: (> 1 v_~t5_pc~0_5) InVars {~t5_pc~0=v_~t5_pc~0_5} OutVars{~t5_pc~0=v_~t5_pc~0_5} AuxVars[] AssignedVars[] 171736#L405-2 [2940] L405-2-->L416: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 171767#L416 [4272] L416-->L855: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 171837#L855 [3091] L855-->L855-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_12} AuxVars[] AssignedVars[] 171838#L855-2 [3093] L855-2-->L424: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_4|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 171459#L424 [3713] L424-->L424-2: Formula: (< v_~t6_pc~0_5 1) InVars {~t6_pc~0=v_~t6_pc~0_5} OutVars{~t6_pc~0=v_~t6_pc~0_5} AuxVars[] AssignedVars[] 171460#L424-2 [2503] L424-2-->L435: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 171456#L435 [4273] L435-->L863: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___5~0_49 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_28|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_28|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 171379#L863 [2425] L863-->L863-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___5~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} AuxVars[] AssignedVars[] 171352#L863-2 [3719] L863-2-->L733-1: Formula: (> v_~M_E~0_15 1) InVars {~M_E~0=v_~M_E~0_15} OutVars{~M_E~0=v_~M_E~0_15} AuxVars[] AssignedVars[] 171353#L733-1 [3722] L733-1-->L738-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 171784#L738-1 [3723] L738-1-->L743-1: Formula: (< 1 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 171476#L743-1 [3726] L743-1-->L748-1: Formula: (< 1 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 171477#L748-1 [3728] L748-1-->L753-1: Formula: (> v_~T4_E~0_10 1) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 171360#L753-1 [3729] L753-1-->L758-1: Formula: (< 1 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 171361#L758-1 [3731] L758-1-->L763-1: Formula: (> v_~T6_E~0_10 1) InVars {~T6_E~0=v_~T6_E~0_10} OutVars{~T6_E~0=v_~T6_E~0_10} AuxVars[] AssignedVars[] 171433#L763-1 [3733] L763-1-->L768-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 171434#L768-1 [3736] L768-1-->L773-1: Formula: (< 1 v_~E_2~0_14) InVars {~E_2~0=v_~E_2~0_14} OutVars{~E_2~0=v_~E_2~0_14} AuxVars[] AssignedVars[] 171650#L773-1 [3737] L773-1-->L778-1: Formula: (< 1 v_~E_3~0_14) InVars {~E_3~0=v_~E_3~0_14} OutVars{~E_3~0=v_~E_3~0_14} AuxVars[] AssignedVars[] 171651#L778-1 [3740] L778-1-->L783-1: Formula: (< 1 v_~E_4~0_14) InVars {~E_4~0=v_~E_4~0_14} OutVars{~E_4~0=v_~E_4~0_14} AuxVars[] AssignedVars[] 171526#L783-1 [3741] L783-1-->L788-1: Formula: (< 1 v_~E_5~0_14) InVars {~E_5~0=v_~E_5~0_14} OutVars{~E_5~0=v_~E_5~0_14} AuxVars[] AssignedVars[] 171527#L788-1 [3744] L788-1-->L1014-1: Formula: (< 1 v_~E_6~0_14) InVars {~E_6~0=v_~E_6~0_14} OutVars{~E_6~0=v_~E_6~0_14} AuxVars[] AssignedVars[] 171373#L1014-1 [2020-06-22 00:13:33,560 INFO L796 eck$LassoCheckResult]: Loop: 171373#L1014-1 [4274] L1014-1-->L635: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp_ndt_7~0=v_ULTIMATE.start_eval_~tmp_ndt_7~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp_ndt_7~0] 171335#L635 [4275] L635-->L494: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_37} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 174011#L494 [3745] L494-->L498: Formula: (< v_~m_st~0_9 0) InVars {~m_st~0=v_~m_st~0_9} OutVars{~m_st~0=v_~m_st~0_9} AuxVars[] AssignedVars[] 174004#L498 [3749] L498-->L502: Formula: (< v_~t1_st~0_9 0) InVars {~t1_st~0=v_~t1_st~0_9} OutVars{~t1_st~0=v_~t1_st~0_9} AuxVars[] AssignedVars[] 174005#L502 [3753] L502-->L506: Formula: (> v_~t2_st~0_9 0) InVars {~t2_st~0=v_~t2_st~0_9} OutVars{~t2_st~0=v_~t2_st~0_9} AuxVars[] AssignedVars[] 174006#L506 [3760] L506-->L510: Formula: (< 0 v_~t3_st~0_10) InVars {~t3_st~0=v_~t3_st~0_10} OutVars{~t3_st~0=v_~t3_st~0_10} AuxVars[] AssignedVars[] 174007#L510 [3765] L510-->L514: Formula: (> 0 v_~t4_st~0_11) InVars {~t4_st~0=v_~t4_st~0_11} OutVars{~t4_st~0=v_~t4_st~0_11} AuxVars[] AssignedVars[] 174010#L514 [3773] L514-->L518: Formula: (> v_~t5_st~0_11 0) InVars {~t5_st~0=v_~t5_st~0_11} OutVars{~t5_st~0=v_~t5_st~0_11} AuxVars[] AssignedVars[] 174008#L518 [3783] L518-->L531: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_28 0) (< 0 v_~t6_st~0_11)) InVars {~t6_st~0=v_~t6_st~0_11} OutVars{~t6_st~0=v_~t6_st~0_11, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_28} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 174009#L531 [4276] L531-->L546: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 177331#L546 [4278] L546-->L660-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 177330#L660-2 [3747] L660-2-->L660-4: Formula: (> v_~M_E~0_30 0) InVars {~M_E~0=v_~M_E~0_30} OutVars{~M_E~0=v_~M_E~0_30} AuxVars[] AssignedVars[] 177329#L660-4 [3058] L660-4-->L665-3: Formula: (and (= v_~T1_E~0_11 1) (= v_~T1_E~0_12 0)) InVars {~T1_E~0=v_~T1_E~0_12} OutVars{~T1_E~0=v_~T1_E~0_11} AuxVars[] AssignedVars[~T1_E~0] 176891#L665-3 [3756] L665-3-->L670-3: Formula: (< 0 v_~T2_E~0_13) InVars {~T2_E~0=v_~T2_E~0_13} OutVars{~T2_E~0=v_~T2_E~0_13} AuxVars[] AssignedVars[] 176889#L670-3 [3762] L670-3-->L675-3: Formula: (< 0 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 176887#L675-3 [3768] L675-3-->L680-3: Formula: (> v_~T4_E~0_13 0) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 176885#L680-3 [3776] L680-3-->L685-3: Formula: (< 0 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 176883#L685-3 [3785] L685-3-->L690-3: Formula: (> v_~T6_E~0_13 0) InVars {~T6_E~0=v_~T6_E~0_13} OutVars{~T6_E~0=v_~T6_E~0_13} AuxVars[] AssignedVars[] 176881#L690-3 [3795] L690-3-->L695-3: Formula: (< 0 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 176879#L695-3 [3805] L695-3-->L700-3: Formula: (< 0 v_~E_2~0_31) InVars {~E_2~0=v_~E_2~0_31} OutVars{~E_2~0=v_~E_2~0_31} AuxVars[] AssignedVars[] 176877#L700-3 [3818] L700-3-->L705-3: Formula: (< 0 v_~E_3~0_31) InVars {~E_3~0=v_~E_3~0_31} OutVars{~E_3~0=v_~E_3~0_31} AuxVars[] AssignedVars[] 176876#L705-3 [2688] L705-3-->L710-3: Formula: (and (= v_~E_4~0_29 1) (= 0 v_~E_4~0_30)) InVars {~E_4~0=v_~E_4~0_30} OutVars{~E_4~0=v_~E_4~0_29} AuxVars[] AssignedVars[~E_4~0] 176875#L710-3 [3844] L710-3-->L715-3: Formula: (< 0 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 176874#L715-3 [3854] L715-3-->L720-3: Formula: (< 0 v_~E_6~0_31) InVars {~E_6~0=v_~E_6~0_31} OutVars{~E_6~0=v_~E_6~0_31} AuxVars[] AssignedVars[] 176873#L720-3 [2388] L720-3-->L310-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_43, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_43, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_25|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_25|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_25|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_43, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_43, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_43, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_25|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_25|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_25|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_25|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_43, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_25|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_43, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_43} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 171659#L310-21 [3870] L310-21-->L310-23: Formula: (< v_~m_pc~0_24 1) InVars {~m_pc~0=v_~m_pc~0_24} OutVars{~m_pc~0=v_~m_pc~0_24} AuxVars[] AssignedVars[] 171660#L310-23 [2785] L310-23-->L321-7: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_47 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_47} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 177174#L321-7 [4303] L321-7-->L815-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 177172#L815-21 [2667] L815-21-->L815-23: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_48) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_48} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_48} AuxVars[] AssignedVars[] 177170#L815-23 [2638] L815-23-->L329-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 171816#L329-21 [3911] L329-21-->L329-23: Formula: (< v_~t1_pc~0_24 1) InVars {~t1_pc~0=v_~t1_pc~0_24} OutVars{~t1_pc~0=v_~t1_pc~0_24} AuxVars[] AssignedVars[] 171817#L329-23 [3052] L329-23-->L340-7: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 171698#L340-7 [4310] L340-7-->L823-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 171699#L823-21 [2931] L823-21-->L823-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} AuxVars[] AssignedVars[] 171759#L823-23 [2934] L823-23-->L348-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_25|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 171761#L348-21 [3953] L348-21-->L348-23: Formula: (> 1 v_~t2_pc~0_24) InVars {~t2_pc~0=v_~t2_pc~0_24} OutVars{~t2_pc~0=v_~t2_pc~0_24} AuxVars[] AssignedVars[] 171907#L348-23 [3319] L348-23-->L359-7: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 171866#L359-7 [4317] L359-7-->L831-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 171451#L831-21 [2490] L831-21-->L831-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} AuxVars[] AssignedVars[] 171452#L831-23 [3197] L831-23-->L367-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_25|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 171362#L367-21 [3995] L367-21-->L367-23: Formula: (> v_~t3_pc~0_24 1) InVars {~t3_pc~0=v_~t3_pc~0_24} OutVars{~t3_pc~0=v_~t3_pc~0_24} AuxVars[] AssignedVars[] 171331#L367-23 [2385] L367-23-->L378-7: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 171332#L378-7 [4324] L378-7-->L839-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 171386#L839-21 [2715] L839-21-->L839-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_48} AuxVars[] AssignedVars[] 171611#L839-23 [2722] L839-23-->L386-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_49, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 171530#L386-21 [4038] L386-21-->L386-23: Formula: (> 1 v_~t4_pc~0_24) InVars {~t4_pc~0=v_~t4_pc~0_24} OutVars{~t4_pc~0=v_~t4_pc~0_24} AuxVars[] AssignedVars[] 171531#L386-23 [2623] L386-23-->L397-7: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 171536#L397-7 [4331] L397-7-->L847-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 171571#L847-21 [4066] L847-21-->L847-23: Formula: (and (> v_ULTIMATE.start_activate_threads_~tmp___3~0_47 0) (= v_~t4_st~0_22 0)) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_47, ~t4_st~0=v_~t4_st~0_22} AuxVars[] AssignedVars[~t4_st~0] 171793#L847-23 [2983] L847-23-->L405-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_25|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 171746#L405-21 [4080] L405-21-->L405-23: Formula: (> v_~t5_pc~0_24 1) InVars {~t5_pc~0=v_~t5_pc~0_24} OutVars{~t5_pc~0=v_~t5_pc~0_24} AuxVars[] AssignedVars[] 171731#L405-23 [2891] L405-23-->L416-7: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 171739#L416-7 [4338] L416-7-->L855-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 171754#L855-21 [3251] L855-21-->L855-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} AuxVars[] AssignedVars[] 171905#L855-23 [3257] L855-23-->L424-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_25|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 171884#L424-21 [4122] L424-21-->L424-23: Formula: (> 1 v_~t6_pc~0_24) InVars {~t6_pc~0=v_~t6_pc~0_24} OutVars{~t6_pc~0=v_~t6_pc~0_24} AuxVars[] AssignedVars[] 171885#L424-23 [3177] L424-23-->L435-7: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 171446#L435-7 [4340] L435-7-->L863-21: Formula: (and (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___5~0_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_35|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_41|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 171447#L863-21 [4135] L863-21-->L863-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___5~0_47 0) (= v_~t6_st~0_22 0)) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} OutVars{~t6_st~0=v_~t6_st~0_22, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} AuxVars[] AssignedVars[~t6_st~0] 171486#L863-23 [4138] L863-23-->L733-3: Formula: (> v_~M_E~0_35 1) InVars {~M_E~0=v_~M_E~0_35} OutVars{~M_E~0=v_~M_E~0_35} AuxVars[] AssignedVars[] 171487#L733-3 [3184] L733-3-->L738-3: Formula: (and (= v_~T1_E~0_15 1) (= v_~T1_E~0_14 2)) InVars {~T1_E~0=v_~T1_E~0_15} OutVars{~T1_E~0=v_~T1_E~0_14} AuxVars[] AssignedVars[~T1_E~0] 171787#L738-3 [4142] L738-3-->L743-3: Formula: (< 1 v_~T2_E~0_16) InVars {~T2_E~0=v_~T2_E~0_16} OutVars{~T2_E~0=v_~T2_E~0_16} AuxVars[] AssignedVars[] 171466#L743-3 [4143] L743-3-->L748-3: Formula: (< 1 v_~T3_E~0_16) InVars {~T3_E~0=v_~T3_E~0_16} OutVars{~T3_E~0=v_~T3_E~0_16} AuxVars[] AssignedVars[] 171467#L748-3 [4145] L748-3-->L753-3: Formula: (> v_~T4_E~0_16 1) InVars {~T4_E~0=v_~T4_E~0_16} OutVars{~T4_E~0=v_~T4_E~0_16} AuxVars[] AssignedVars[] 171327#L753-3 [4148] L753-3-->L758-3: Formula: (< 1 v_~T5_E~0_16) InVars {~T5_E~0=v_~T5_E~0_16} OutVars{~T5_E~0=v_~T5_E~0_16} AuxVars[] AssignedVars[] 171328#L758-3 [4149] L758-3-->L763-3: Formula: (> v_~T6_E~0_16 1) InVars {~T6_E~0=v_~T6_E~0_16} OutVars{~T6_E~0=v_~T6_E~0_16} AuxVars[] AssignedVars[] 171419#L763-3 [4151] L763-3-->L768-3: Formula: (< 1 v_~E_1~0_36) InVars {~E_1~0=v_~E_1~0_36} OutVars{~E_1~0=v_~E_1~0_36} AuxVars[] AssignedVars[] 171420#L768-3 [4154] L768-3-->L773-3: Formula: (< 1 v_~E_2~0_36) InVars {~E_2~0=v_~E_2~0_36} OutVars{~E_2~0=v_~E_2~0_36} AuxVars[] AssignedVars[] 171655#L773-3 [4156] L773-3-->L778-3: Formula: (< 1 v_~E_3~0_36) InVars {~E_3~0=v_~E_3~0_36} OutVars{~E_3~0=v_~E_3~0_36} AuxVars[] AssignedVars[] 171656#L778-3 [3308] L778-3-->L783-3: Formula: (and (= 1 v_~E_4~0_35) (= v_~E_4~0_34 2)) InVars {~E_4~0=v_~E_4~0_35} OutVars{~E_4~0=v_~E_4~0_34} AuxVars[] AssignedVars[~E_4~0] 171532#L783-3 [4160] L783-3-->L788-3: Formula: (< 1 v_~E_5~0_36) InVars {~E_5~0=v_~E_5~0_36} OutVars{~E_5~0=v_~E_5~0_36} AuxVars[] AssignedVars[] 171533#L788-3 [4162] L788-3-->L793-3: Formula: (< 1 v_~E_6~0_36) InVars {~E_6~0=v_~E_6~0_36} OutVars{~E_6~0=v_~E_6~0_36} AuxVars[] AssignedVars[] 171785#L793-3 [2966] L793-3-->L494-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_30} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 171733#L494-1 [2878] L494-1-->L531-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33 1) (= 0 v_~m_st~0_21)) InVars {~m_st~0=v_~m_st~0_21} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33, ~m_st~0=v_~m_st~0_21} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 171407#L531-1 [4341] L531-1-->L1033: Formula: (and (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp~3] 171638#L1033 [4169] L1033-->L1033-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_6) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} AuxVars[] AssignedVars[] 171748#L1033-1 [2919] L1033-1-->L494-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_3|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_6, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_exists_runnable_thread_~__retres1~7, ULTIMATE.start_stop_simulation_#res] 177349#L494-2 [2882] L494-2-->L531-2: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9 1) (= v_~m_st~0_6 0)) InVars {~m_st~0=v_~m_st~0_6} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9, ~m_st~0=v_~m_st~0_6} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 177348#L531-2 [4343] L531-2-->L988: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 171903#L988 [3240] L988-->L995: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 171372#L995 [4354] L995-->L1014-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_6|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_#t~ret17, ULTIMATE.start_stop_simulation_#res] 171373#L1014-1 [2020-06-22 00:13:33,560 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:33,560 INFO L82 PathProgramCache]: Analyzing trace with hash -1932600016, now seen corresponding path program 5 times [2020-06-22 00:13:33,560 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:33,560 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:33,561 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:33,561 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:33,561 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:33,566 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:13:33,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:13:33,580 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:33,580 INFO L82 PathProgramCache]: Analyzing trace with hash 985910452, now seen corresponding path program 1 times [2020-06-22 00:13:33,580 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:33,580 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:33,581 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:33,581 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2020-06-22 00:13:33,581 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:33,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:33,614 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:33,614 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:33,615 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2020-06-22 00:13:33,615 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-06-22 00:13:33,615 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2020-06-22 00:13:33,615 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2020-06-22 00:13:33,615 INFO L87 Difference]: Start difference. First operand 6344 states and 9955 transitions. cyclomatic complexity: 3612 Second operand 6 states. [2020-06-22 00:13:35,364 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-06-22 00:13:35,364 INFO L93 Difference]: Finished difference Result 13341 states and 20737 transitions. [2020-06-22 00:13:35,364 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2020-06-22 00:13:35,365 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13341 states and 20737 transitions. [2020-06-22 00:13:35,420 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 13268 [2020-06-22 00:13:35,454 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13341 states to 13341 states and 20737 transitions. [2020-06-22 00:13:35,454 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13341 [2020-06-22 00:13:35,462 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13341 [2020-06-22 00:13:35,463 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13341 states and 20737 transitions. [2020-06-22 00:13:35,472 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-06-22 00:13:35,473 INFO L706 BuchiCegarLoop]: Abstraction has 13341 states and 20737 transitions. [2020-06-22 00:13:35,478 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13341 states and 20737 transitions. [2020-06-22 00:13:35,552 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13341 to 6464. [2020-06-22 00:13:35,553 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6464 states. [2020-06-22 00:13:35,564 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6464 states to 6464 states and 10022 transitions. [2020-06-22 00:13:35,565 INFO L729 BuchiCegarLoop]: Abstraction has 6464 states and 10022 transitions. [2020-06-22 00:13:35,565 INFO L609 BuchiCegarLoop]: Abstraction has 6464 states and 10022 transitions. [2020-06-22 00:13:35,565 INFO L442 BuchiCegarLoop]: ======== Iteration 37============ [2020-06-22 00:13:35,565 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6464 states and 10022 transitions. [2020-06-22 00:13:35,582 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 6392 [2020-06-22 00:13:35,583 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-06-22 00:13:35,583 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-06-22 00:13:35,584 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:35,584 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:35,585 INFO L794 eck$LassoCheckResult]: Stem: 191559#ULTIMATE.startENTRY [4266] ULTIMATE.startENTRY-->L444: Formula: (and (= 1 v_~t6_i~0_7) (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~M_E~0_37 2) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 0 v_~t6_pc~0_26) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_6~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= v_~T6_E~0_18 2) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~t6_st~0_24) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t6_pc~0=v_~t6_pc~0_26, ~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~T6_E~0=v_~T6_E~0_18, ~M_E~0=v_~M_E~0_37, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ~T4_E~0=v_~T4_E~0_18, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_4|, ~t6_i~0=v_~t6_i~0_7, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ULTIMATE.start_main_~__retres1~8=v_ULTIMATE.start_main_~__retres1~8_6, ~T2_E~0=v_~T2_E~0_18, ~t6_st~0=v_~t6_st~0_24, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_6~0=v_~E_6~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t6_pc~0, ~t5_i~0, ~t1_pc~0, ~t5_st~0, ~T6_E~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ~T4_E~0, ULTIMATE.start_start_simulation_#t~ret17, ~t6_i~0, ~t2_st~0, ~t2_pc~0, ULTIMATE.start_main_~__retres1~8, ~T2_E~0, ~t6_st~0, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_6~0, ULTIMATE.start_main_#res, ~E_2~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 191130#L444 [2453] L444-->L451-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 191131#L451-1 [3030] L451-1-->L456-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 191222#L456-1 [2574] L456-1-->L461-1: Formula: (and (= v_~t2_st~0_2 0) (= 1 v_~t2_i~0_3)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_2} AuxVars[] AssignedVars[~t2_st~0] 191223#L461-1 [2880] L461-1-->L466-1: Formula: (and (= v_~t3_st~0_3 0) (= v_~t3_i~0_3 1)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_3, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 191135#L466-1 [2457] L466-1-->L471-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 191136#L471-1 [3209] L471-1-->L476-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 191388#L476-1 [2761] L476-1-->L481-1: Formula: (and (= 1 v_~t6_i~0_3) (= v_~t6_st~0_4 0)) InVars {~t6_i~0=v_~t6_i~0_3} OutVars{~t6_st~0=v_~t6_st~0_4, ~t6_i~0=v_~t6_i~0_3} AuxVars[] AssignedVars[~t6_st~0] 191389#L481-1 [3652] L481-1-->L660-1: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 191581#L660-1 [3654] L660-1-->L665-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 191050#L665-1 [3655] L665-1-->L670-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 191051#L670-1 [3658] L670-1-->L675-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 191142#L675-1 [3659] L675-1-->L680-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 191143#L680-1 [3661] L680-1-->L685-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 191400#L685-1 [3663] L685-1-->L690-1: Formula: (< 0 v_~T6_E~0_4) InVars {~T6_E~0=v_~T6_E~0_4} OutVars{~T6_E~0=v_~T6_E~0_4} AuxVars[] AssignedVars[] 191401#L690-1 [3665] L690-1-->L695-1: Formula: (> v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 191262#L695-1 [3668] L695-1-->L700-1: Formula: (> v_~E_2~0_6 0) InVars {~E_2~0=v_~E_2~0_6} OutVars{~E_2~0=v_~E_2~0_6} AuxVars[] AssignedVars[] 191263#L700-1 [3670] L700-1-->L705-1: Formula: (> v_~E_3~0_6 0) InVars {~E_3~0=v_~E_3~0_6} OutVars{~E_3~0=v_~E_3~0_6} AuxVars[] AssignedVars[] 191536#L705-1 [3672] L705-1-->L710-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 191201#L710-1 [3674] L710-1-->L715-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 191202#L715-1 [3675] L715-1-->L720-1: Formula: (> v_~E_6~0_4 0) InVars {~E_6~0=v_~E_6~0_4} OutVars{~E_6~0=v_~E_6~0_4} AuxVars[] AssignedVars[] 191086#L720-1 [2412] L720-1-->L310: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_7, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_4|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_4|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_7, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_4, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_4, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_2|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_2|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_4|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_4|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_7, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_2|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_4} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 191087#L310 [3678] L310-->L310-2: Formula: (< v_~m_pc~0_5 1) InVars {~m_pc~0=v_~m_pc~0_5} OutVars{~m_pc~0=v_~m_pc~0_5} AuxVars[] AssignedVars[] 191235#L310-2 [2805] L310-2-->L321: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_11 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 191230#L321 [4267] L321-->L815: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 191231#L815 [2976] L815-->L815-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_12) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} AuxVars[] AssignedVars[] 191530#L815-2 [2961] L815-2-->L329: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 191453#L329 [3683] L329-->L329-2: Formula: (< v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 191454#L329-2 [2861] L329-2-->L340: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 191449#L340 [4268] L340-->L823: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 191450#L823 [3234] L823-->L823-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} AuxVars[] AssignedVars[] 191669#L823-2 [3235] L823-2-->L348: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_4|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 191635#L348 [3690] L348-->L348-2: Formula: (< v_~t2_pc~0_5 1) InVars {~t2_pc~0=v_~t2_pc~0_5} OutVars{~t2_pc~0=v_~t2_pc~0_5} AuxVars[] AssignedVars[] 191637#L348-2 [3153] L348-2-->L359: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 191633#L359 [4269] L359-->L831: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 191208#L831 [2537] L831-->L831-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} AuxVars[] AssignedVars[] 191196#L831-2 [2520] L831-2-->L367: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_4|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 191138#L367 [3695] L367-->L367-2: Formula: (> 1 v_~t3_pc~0_5) InVars {~t3_pc~0=v_~t3_pc~0_5} OutVars{~t3_pc~0=v_~t3_pc~0_5} AuxVars[] AssignedVars[] 191115#L367-2 [2438] L367-2-->L378: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 191116#L378 [4270] L378-->L839: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 191137#L839 [2791] L839-->L839-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} AuxVars[] AssignedVars[] 191412#L839-2 [2794] L839-2-->L386: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_7, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 191321#L386 [3702] L386-->L386-2: Formula: (< v_~t4_pc~0_5 1) InVars {~t4_pc~0=v_~t4_pc~0_5} OutVars{~t4_pc~0=v_~t4_pc~0_5} AuxVars[] AssignedVars[] 191322#L386-2 [2680] L386-2-->L397: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 191319#L397 [4271] L397-->L847: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 191320#L847 [3084] L847-->L847-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} AuxVars[] AssignedVars[] 191589#L847-2 [3064] L847-2-->L405: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_4|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 191590#L405 [3708] L405-->L405-2: Formula: (> 1 v_~t5_pc~0_5) InVars {~t5_pc~0=v_~t5_pc~0_5} OutVars{~t5_pc~0=v_~t5_pc~0_5} AuxVars[] AssignedVars[] 191481#L405-2 [2940] L405-2-->L416: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 191515#L416 [4272] L416-->L855: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 191601#L855 [3091] L855-->L855-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_12} AuxVars[] AssignedVars[] 191602#L855-2 [3093] L855-2-->L424: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_4|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 191181#L424 [3713] L424-->L424-2: Formula: (< v_~t6_pc~0_5 1) InVars {~t6_pc~0=v_~t6_pc~0_5} OutVars{~t6_pc~0=v_~t6_pc~0_5} AuxVars[] AssignedVars[] 191182#L424-2 [2503] L424-2-->L435: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 191178#L435 [4273] L435-->L863: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___5~0_49 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_28|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_28|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 191100#L863 [2425] L863-->L863-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___5~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} AuxVars[] AssignedVars[] 191073#L863-2 [3719] L863-2-->L733-1: Formula: (> v_~M_E~0_15 1) InVars {~M_E~0=v_~M_E~0_15} OutVars{~M_E~0=v_~M_E~0_15} AuxVars[] AssignedVars[] 191074#L733-1 [3722] L733-1-->L738-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 191533#L738-1 [3723] L738-1-->L743-1: Formula: (< 1 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 191199#L743-1 [3726] L743-1-->L748-1: Formula: (< 1 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 191200#L748-1 [3728] L748-1-->L753-1: Formula: (> v_~T4_E~0_10 1) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 191081#L753-1 [3729] L753-1-->L758-1: Formula: (< 1 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 191082#L758-1 [3731] L758-1-->L763-1: Formula: (> v_~T6_E~0_10 1) InVars {~T6_E~0=v_~T6_E~0_10} OutVars{~T6_E~0=v_~T6_E~0_10} AuxVars[] AssignedVars[] 191154#L763-1 [3733] L763-1-->L768-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 191155#L768-1 [3736] L768-1-->L773-1: Formula: (< 1 v_~E_2~0_14) InVars {~E_2~0=v_~E_2~0_14} OutVars{~E_2~0=v_~E_2~0_14} AuxVars[] AssignedVars[] 191392#L773-1 [3737] L773-1-->L778-1: Formula: (< 1 v_~E_3~0_14) InVars {~E_3~0=v_~E_3~0_14} OutVars{~E_3~0=v_~E_3~0_14} AuxVars[] AssignedVars[] 191393#L778-1 [3740] L778-1-->L783-1: Formula: (< 1 v_~E_4~0_14) InVars {~E_4~0=v_~E_4~0_14} OutVars{~E_4~0=v_~E_4~0_14} AuxVars[] AssignedVars[] 191254#L783-1 [3741] L783-1-->L788-1: Formula: (< 1 v_~E_5~0_14) InVars {~E_5~0=v_~E_5~0_14} OutVars{~E_5~0=v_~E_5~0_14} AuxVars[] AssignedVars[] 191255#L788-1 [3744] L788-1-->L1014-1: Formula: (< 1 v_~E_6~0_14) InVars {~E_6~0=v_~E_6~0_14} OutVars{~E_6~0=v_~E_6~0_14} AuxVars[] AssignedVars[] 191644#L1014-1 [2020-06-22 00:13:35,587 INFO L796 eck$LassoCheckResult]: Loop: 191644#L1014-1 [4274] L1014-1-->L635: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp_ndt_7~0=v_ULTIMATE.start_eval_~tmp_ndt_7~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp_ndt_7~0] 192018#L635 [4275] L635-->L494: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_37} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 192002#L494 [3745] L494-->L498: Formula: (< v_~m_st~0_9 0) InVars {~m_st~0=v_~m_st~0_9} OutVars{~m_st~0=v_~m_st~0_9} AuxVars[] AssignedVars[] 191995#L498 [3749] L498-->L502: Formula: (< v_~t1_st~0_9 0) InVars {~t1_st~0=v_~t1_st~0_9} OutVars{~t1_st~0=v_~t1_st~0_9} AuxVars[] AssignedVars[] 191996#L502 [3753] L502-->L506: Formula: (> v_~t2_st~0_9 0) InVars {~t2_st~0=v_~t2_st~0_9} OutVars{~t2_st~0=v_~t2_st~0_9} AuxVars[] AssignedVars[] 191997#L506 [3760] L506-->L510: Formula: (< 0 v_~t3_st~0_10) InVars {~t3_st~0=v_~t3_st~0_10} OutVars{~t3_st~0=v_~t3_st~0_10} AuxVars[] AssignedVars[] 191998#L510 [3765] L510-->L514: Formula: (> 0 v_~t4_st~0_11) InVars {~t4_st~0=v_~t4_st~0_11} OutVars{~t4_st~0=v_~t4_st~0_11} AuxVars[] AssignedVars[] 192001#L514 [3773] L514-->L518: Formula: (> v_~t5_st~0_11 0) InVars {~t5_st~0=v_~t5_st~0_11} OutVars{~t5_st~0=v_~t5_st~0_11} AuxVars[] AssignedVars[] 191999#L518 [3783] L518-->L531: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_28 0) (< 0 v_~t6_st~0_11)) InVars {~t6_st~0=v_~t6_st~0_11} OutVars{~t6_st~0=v_~t6_st~0_11, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_28} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 192000#L531 [4276] L531-->L546: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 196528#L546 [4278] L546-->L660-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 196527#L660-2 [3747] L660-2-->L660-4: Formula: (> v_~M_E~0_30 0) InVars {~M_E~0=v_~M_E~0_30} OutVars{~M_E~0=v_~M_E~0_30} AuxVars[] AssignedVars[] 196526#L660-4 [3058] L660-4-->L665-3: Formula: (and (= v_~T1_E~0_11 1) (= v_~T1_E~0_12 0)) InVars {~T1_E~0=v_~T1_E~0_12} OutVars{~T1_E~0=v_~T1_E~0_11} AuxVars[] AssignedVars[~T1_E~0] 196525#L665-3 [3756] L665-3-->L670-3: Formula: (< 0 v_~T2_E~0_13) InVars {~T2_E~0=v_~T2_E~0_13} OutVars{~T2_E~0=v_~T2_E~0_13} AuxVars[] AssignedVars[] 196524#L670-3 [3762] L670-3-->L675-3: Formula: (< 0 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 196523#L675-3 [3768] L675-3-->L680-3: Formula: (> v_~T4_E~0_13 0) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 196522#L680-3 [3776] L680-3-->L685-3: Formula: (< 0 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 196521#L685-3 [3785] L685-3-->L690-3: Formula: (> v_~T6_E~0_13 0) InVars {~T6_E~0=v_~T6_E~0_13} OutVars{~T6_E~0=v_~T6_E~0_13} AuxVars[] AssignedVars[] 196520#L690-3 [3795] L690-3-->L695-3: Formula: (< 0 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 196519#L695-3 [3805] L695-3-->L700-3: Formula: (< 0 v_~E_2~0_31) InVars {~E_2~0=v_~E_2~0_31} OutVars{~E_2~0=v_~E_2~0_31} AuxVars[] AssignedVars[] 196518#L700-3 [3818] L700-3-->L705-3: Formula: (< 0 v_~E_3~0_31) InVars {~E_3~0=v_~E_3~0_31} OutVars{~E_3~0=v_~E_3~0_31} AuxVars[] AssignedVars[] 196517#L705-3 [2688] L705-3-->L710-3: Formula: (and (= v_~E_4~0_29 1) (= 0 v_~E_4~0_30)) InVars {~E_4~0=v_~E_4~0_30} OutVars{~E_4~0=v_~E_4~0_29} AuxVars[] AssignedVars[~E_4~0] 196516#L710-3 [3844] L710-3-->L715-3: Formula: (< 0 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 196515#L715-3 [3854] L715-3-->L720-3: Formula: (< 0 v_~E_6~0_31) InVars {~E_6~0=v_~E_6~0_31} OutVars{~E_6~0=v_~E_6~0_31} AuxVars[] AssignedVars[] 196487#L720-3 [2388] L720-3-->L310-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_43, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_43, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_25|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_25|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_25|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_43, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_43, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_43, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_25|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_25|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_25|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_25|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_43, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_25|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_43, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_43} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 196484#L310-21 [3870] L310-21-->L310-23: Formula: (< v_~m_pc~0_24 1) InVars {~m_pc~0=v_~m_pc~0_24} OutVars{~m_pc~0=v_~m_pc~0_24} AuxVars[] AssignedVars[] 196480#L310-23 [2785] L310-23-->L321-7: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_47 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_47} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 196477#L321-7 [4303] L321-7-->L815-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 196474#L815-21 [2667] L815-21-->L815-23: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_48) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_48} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_48} AuxVars[] AssignedVars[] 196470#L815-23 [2638] L815-23-->L329-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 196466#L329-21 [3911] L329-21-->L329-23: Formula: (< v_~t1_pc~0_24 1) InVars {~t1_pc~0=v_~t1_pc~0_24} OutVars{~t1_pc~0=v_~t1_pc~0_24} AuxVars[] AssignedVars[] 196462#L329-23 [3052] L329-23-->L340-7: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 196459#L340-7 [4310] L340-7-->L823-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 196454#L823-21 [2931] L823-21-->L823-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} AuxVars[] AssignedVars[] 196449#L823-23 [2934] L823-23-->L348-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_25|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 196443#L348-21 [3953] L348-21-->L348-23: Formula: (> 1 v_~t2_pc~0_24) InVars {~t2_pc~0=v_~t2_pc~0_24} OutVars{~t2_pc~0=v_~t2_pc~0_24} AuxVars[] AssignedVars[] 196435#L348-23 [3319] L348-23-->L359-7: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 196429#L359-7 [4317] L359-7-->L831-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 196424#L831-21 [2490] L831-21-->L831-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} AuxVars[] AssignedVars[] 196419#L831-23 [3197] L831-23-->L367-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_25|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 196414#L367-21 [3995] L367-21-->L367-23: Formula: (> v_~t3_pc~0_24 1) InVars {~t3_pc~0=v_~t3_pc~0_24} OutVars{~t3_pc~0=v_~t3_pc~0_24} AuxVars[] AssignedVars[] 196405#L367-23 [2385] L367-23-->L378-7: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 196399#L378-7 [4324] L378-7-->L839-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 196394#L839-21 [2715] L839-21-->L839-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_48} AuxVars[] AssignedVars[] 196389#L839-23 [2722] L839-23-->L386-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_49, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 193803#L386-21 [4038] L386-21-->L386-23: Formula: (> 1 v_~t4_pc~0_24) InVars {~t4_pc~0=v_~t4_pc~0_24} OutVars{~t4_pc~0=v_~t4_pc~0_24} AuxVars[] AssignedVars[] 193802#L386-23 [2623] L386-23-->L397-7: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 193801#L397-7 [4331] L397-7-->L847-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 193800#L847-21 [3021] L847-21-->L847-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_48} AuxVars[] AssignedVars[] 193799#L847-23 [2983] L847-23-->L405-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_25|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 193797#L405-21 [4080] L405-21-->L405-23: Formula: (> v_~t5_pc~0_24 1) InVars {~t5_pc~0=v_~t5_pc~0_24} OutVars{~t5_pc~0=v_~t5_pc~0_24} AuxVars[] AssignedVars[] 193796#L405-23 [2891] L405-23-->L416-7: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 193795#L416-7 [4338] L416-7-->L855-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 193794#L855-21 [3251] L855-21-->L855-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} AuxVars[] AssignedVars[] 193793#L855-23 [3257] L855-23-->L424-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_25|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 193792#L424-21 [4122] L424-21-->L424-23: Formula: (> 1 v_~t6_pc~0_24) InVars {~t6_pc~0=v_~t6_pc~0_24} OutVars{~t6_pc~0=v_~t6_pc~0_24} AuxVars[] AssignedVars[] 193064#L424-23 [3177] L424-23-->L435-7: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 193791#L435-7 [4340] L435-7-->L863-21: Formula: (and (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___5~0_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_35|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_41|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 193790#L863-21 [4135] L863-21-->L863-23: Formula: (and (< v_ULTIMATE.start_activate_threads_~tmp___5~0_47 0) (= v_~t6_st~0_22 0)) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} OutVars{~t6_st~0=v_~t6_st~0_22, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} AuxVars[] AssignedVars[~t6_st~0] 193789#L863-23 [4138] L863-23-->L733-3: Formula: (> v_~M_E~0_35 1) InVars {~M_E~0=v_~M_E~0_35} OutVars{~M_E~0=v_~M_E~0_35} AuxVars[] AssignedVars[] 193788#L733-3 [3184] L733-3-->L738-3: Formula: (and (= v_~T1_E~0_15 1) (= v_~T1_E~0_14 2)) InVars {~T1_E~0=v_~T1_E~0_15} OutVars{~T1_E~0=v_~T1_E~0_14} AuxVars[] AssignedVars[~T1_E~0] 193787#L738-3 [4142] L738-3-->L743-3: Formula: (< 1 v_~T2_E~0_16) InVars {~T2_E~0=v_~T2_E~0_16} OutVars{~T2_E~0=v_~T2_E~0_16} AuxVars[] AssignedVars[] 193786#L743-3 [4143] L743-3-->L748-3: Formula: (< 1 v_~T3_E~0_16) InVars {~T3_E~0=v_~T3_E~0_16} OutVars{~T3_E~0=v_~T3_E~0_16} AuxVars[] AssignedVars[] 193785#L748-3 [4145] L748-3-->L753-3: Formula: (> v_~T4_E~0_16 1) InVars {~T4_E~0=v_~T4_E~0_16} OutVars{~T4_E~0=v_~T4_E~0_16} AuxVars[] AssignedVars[] 193784#L753-3 [4148] L753-3-->L758-3: Formula: (< 1 v_~T5_E~0_16) InVars {~T5_E~0=v_~T5_E~0_16} OutVars{~T5_E~0=v_~T5_E~0_16} AuxVars[] AssignedVars[] 193783#L758-3 [4149] L758-3-->L763-3: Formula: (> v_~T6_E~0_16 1) InVars {~T6_E~0=v_~T6_E~0_16} OutVars{~T6_E~0=v_~T6_E~0_16} AuxVars[] AssignedVars[] 193782#L763-3 [4151] L763-3-->L768-3: Formula: (< 1 v_~E_1~0_36) InVars {~E_1~0=v_~E_1~0_36} OutVars{~E_1~0=v_~E_1~0_36} AuxVars[] AssignedVars[] 193781#L768-3 [4154] L768-3-->L773-3: Formula: (< 1 v_~E_2~0_36) InVars {~E_2~0=v_~E_2~0_36} OutVars{~E_2~0=v_~E_2~0_36} AuxVars[] AssignedVars[] 193780#L773-3 [4156] L773-3-->L778-3: Formula: (< 1 v_~E_3~0_36) InVars {~E_3~0=v_~E_3~0_36} OutVars{~E_3~0=v_~E_3~0_36} AuxVars[] AssignedVars[] 193779#L778-3 [3308] L778-3-->L783-3: Formula: (and (= 1 v_~E_4~0_35) (= v_~E_4~0_34 2)) InVars {~E_4~0=v_~E_4~0_35} OutVars{~E_4~0=v_~E_4~0_34} AuxVars[] AssignedVars[~E_4~0] 193778#L783-3 [4160] L783-3-->L788-3: Formula: (< 1 v_~E_5~0_36) InVars {~E_5~0=v_~E_5~0_36} OutVars{~E_5~0=v_~E_5~0_36} AuxVars[] AssignedVars[] 193777#L788-3 [4162] L788-3-->L793-3: Formula: (< 1 v_~E_6~0_36) InVars {~E_6~0=v_~E_6~0_36} OutVars{~E_6~0=v_~E_6~0_36} AuxVars[] AssignedVars[] 193776#L793-3 [2966] L793-3-->L494-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_30} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 193775#L494-1 [2878] L494-1-->L531-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33 1) (= 0 v_~m_st~0_21)) InVars {~m_st~0=v_~m_st~0_21} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33, ~m_st~0=v_~m_st~0_21} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 193767#L531-1 [4341] L531-1-->L1033: Formula: (and (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp~3] 193764#L1033 [4169] L1033-->L1033-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_6) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} AuxVars[] AssignedVars[] 193762#L1033-1 [2919] L1033-1-->L494-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_3|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_6, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_exists_runnable_thread_~__retres1~7, ULTIMATE.start_stop_simulation_#res] 193755#L494-2 [2882] L494-2-->L531-2: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9 1) (= v_~m_st~0_6 0)) InVars {~m_st~0=v_~m_st~0_6} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9, ~m_st~0=v_~m_st~0_6} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 193754#L531-2 [4343] L531-2-->L988: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 193753#L988 [3240] L988-->L995: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 193752#L995 [4354] L995-->L1014-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_6|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_#t~ret17, ULTIMATE.start_stop_simulation_#res] 191644#L1014-1 [2020-06-22 00:13:35,587 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:35,587 INFO L82 PathProgramCache]: Analyzing trace with hash -1932600016, now seen corresponding path program 6 times [2020-06-22 00:13:35,587 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:35,587 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:35,588 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:35,588 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:35,588 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:35,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:13:35,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:13:35,606 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:35,606 INFO L82 PathProgramCache]: Analyzing trace with hash -1994302305, now seen corresponding path program 1 times [2020-06-22 00:13:35,607 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:35,607 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:35,607 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:35,607 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2020-06-22 00:13:35,607 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:35,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:35,641 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:35,641 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:35,641 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2020-06-22 00:13:35,642 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-06-22 00:13:35,642 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2020-06-22 00:13:35,642 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2020-06-22 00:13:35,642 INFO L87 Difference]: Start difference. First operand 6464 states and 10022 transitions. cyclomatic complexity: 3559 Second operand 6 states. [2020-06-22 00:13:36,350 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-06-22 00:13:36,350 INFO L93 Difference]: Finished difference Result 6626 states and 10295 transitions. [2020-06-22 00:13:36,350 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2020-06-22 00:13:36,351 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6626 states and 10295 transitions. [2020-06-22 00:13:36,372 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 6552 [2020-06-22 00:13:36,385 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6626 states to 6626 states and 10295 transitions. [2020-06-22 00:13:36,385 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6626 [2020-06-22 00:13:36,388 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6626 [2020-06-22 00:13:36,389 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6626 states and 10295 transitions. [2020-06-22 00:13:36,392 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-06-22 00:13:36,392 INFO L706 BuchiCegarLoop]: Abstraction has 6626 states and 10295 transitions. [2020-06-22 00:13:36,394 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6626 states and 10295 transitions. [2020-06-22 00:13:36,441 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6626 to 6464. [2020-06-22 00:13:36,441 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6464 states. [2020-06-22 00:13:36,452 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6464 states to 6464 states and 9909 transitions. [2020-06-22 00:13:36,452 INFO L729 BuchiCegarLoop]: Abstraction has 6464 states and 9909 transitions. [2020-06-22 00:13:36,452 INFO L609 BuchiCegarLoop]: Abstraction has 6464 states and 9909 transitions. [2020-06-22 00:13:36,452 INFO L442 BuchiCegarLoop]: ======== Iteration 38============ [2020-06-22 00:13:36,452 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6464 states and 9909 transitions. [2020-06-22 00:13:36,467 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 6392 [2020-06-22 00:13:36,467 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-06-22 00:13:36,467 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-06-22 00:13:36,469 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:36,469 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:36,470 INFO L794 eck$LassoCheckResult]: Stem: 204667#ULTIMATE.startENTRY [4266] ULTIMATE.startENTRY-->L444: Formula: (and (= 1 v_~t6_i~0_7) (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~M_E~0_37 2) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 0 v_~t6_pc~0_26) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_6~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= v_~T6_E~0_18 2) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~t6_st~0_24) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t6_pc~0=v_~t6_pc~0_26, ~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~T6_E~0=v_~T6_E~0_18, ~M_E~0=v_~M_E~0_37, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ~T4_E~0=v_~T4_E~0_18, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_4|, ~t6_i~0=v_~t6_i~0_7, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ULTIMATE.start_main_~__retres1~8=v_ULTIMATE.start_main_~__retres1~8_6, ~T2_E~0=v_~T2_E~0_18, ~t6_st~0=v_~t6_st~0_24, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_6~0=v_~E_6~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t6_pc~0, ~t5_i~0, ~t1_pc~0, ~t5_st~0, ~T6_E~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ~T4_E~0, ULTIMATE.start_start_simulation_#t~ret17, ~t6_i~0, ~t2_st~0, ~t2_pc~0, ULTIMATE.start_main_~__retres1~8, ~T2_E~0, ~t6_st~0, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_6~0, ULTIMATE.start_main_#res, ~E_2~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 204248#L444 [2453] L444-->L451-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 204249#L451-1 [3030] L451-1-->L456-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 204338#L456-1 [2574] L456-1-->L461-1: Formula: (and (= v_~t2_st~0_2 0) (= 1 v_~t2_i~0_3)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_2} AuxVars[] AssignedVars[~t2_st~0] 204339#L461-1 [2880] L461-1-->L466-1: Formula: (and (= v_~t3_st~0_3 0) (= v_~t3_i~0_3 1)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_3, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 204253#L466-1 [2457] L466-1-->L471-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 204254#L471-1 [3209] L471-1-->L476-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 204496#L476-1 [2761] L476-1-->L481-1: Formula: (and (= 1 v_~t6_i~0_3) (= v_~t6_st~0_4 0)) InVars {~t6_i~0=v_~t6_i~0_3} OutVars{~t6_st~0=v_~t6_st~0_4, ~t6_i~0=v_~t6_i~0_3} AuxVars[] AssignedVars[~t6_st~0] 204497#L481-1 [3652] L481-1-->L660-1: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 204685#L660-1 [3654] L660-1-->L665-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 204167#L665-1 [3655] L665-1-->L670-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 204168#L670-1 [3658] L670-1-->L675-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 204260#L675-1 [3659] L675-1-->L680-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 204261#L680-1 [3661] L680-1-->L685-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 204509#L685-1 [3663] L685-1-->L690-1: Formula: (< 0 v_~T6_E~0_4) InVars {~T6_E~0=v_~T6_E~0_4} OutVars{~T6_E~0=v_~T6_E~0_4} AuxVars[] AssignedVars[] 204510#L690-1 [3665] L690-1-->L695-1: Formula: (> v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 204378#L695-1 [3668] L695-1-->L700-1: Formula: (> v_~E_2~0_6 0) InVars {~E_2~0=v_~E_2~0_6} OutVars{~E_2~0=v_~E_2~0_6} AuxVars[] AssignedVars[] 204379#L700-1 [3670] L700-1-->L705-1: Formula: (> v_~E_3~0_6 0) InVars {~E_3~0=v_~E_3~0_6} OutVars{~E_3~0=v_~E_3~0_6} AuxVars[] AssignedVars[] 204649#L705-1 [3672] L705-1-->L710-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 204318#L710-1 [3674] L710-1-->L715-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 204319#L715-1 [3675] L715-1-->L720-1: Formula: (> v_~E_6~0_4 0) InVars {~E_6~0=v_~E_6~0_4} OutVars{~E_6~0=v_~E_6~0_4} AuxVars[] AssignedVars[] 204204#L720-1 [2412] L720-1-->L310: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_7, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_4|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_4|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_7, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_4, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_4, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_2|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_2|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_4|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_4|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_7, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_2|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_4} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 204205#L310 [3678] L310-->L310-2: Formula: (< v_~m_pc~0_5 1) InVars {~m_pc~0=v_~m_pc~0_5} OutVars{~m_pc~0=v_~m_pc~0_5} AuxVars[] AssignedVars[] 204351#L310-2 [2805] L310-2-->L321: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_11 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 204346#L321 [4267] L321-->L815: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 204347#L815 [2976] L815-->L815-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_12) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} AuxVars[] AssignedVars[] 204644#L815-2 [2961] L815-2-->L329: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 204566#L329 [3683] L329-->L329-2: Formula: (< v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 204567#L329-2 [2861] L329-2-->L340: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 204562#L340 [4268] L340-->L823: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 204563#L823 [3234] L823-->L823-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} AuxVars[] AssignedVars[] 204775#L823-2 [3235] L823-2-->L348: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_4|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 204741#L348 [3690] L348-->L348-2: Formula: (< v_~t2_pc~0_5 1) InVars {~t2_pc~0=v_~t2_pc~0_5} OutVars{~t2_pc~0=v_~t2_pc~0_5} AuxVars[] AssignedVars[] 204743#L348-2 [3153] L348-2-->L359: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 204738#L359 [4269] L359-->L831: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 204327#L831 [2537] L831-->L831-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} AuxVars[] AssignedVars[] 204313#L831-2 [2520] L831-2-->L367: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_4|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 204256#L367 [3695] L367-->L367-2: Formula: (> 1 v_~t3_pc~0_5) InVars {~t3_pc~0=v_~t3_pc~0_5} OutVars{~t3_pc~0=v_~t3_pc~0_5} AuxVars[] AssignedVars[] 204234#L367-2 [2438] L367-2-->L378: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 204235#L378 [4270] L378-->L839: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 204255#L839 [2791] L839-->L839-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} AuxVars[] AssignedVars[] 204520#L839-2 [2794] L839-2-->L386: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_7, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 204431#L386 [3702] L386-->L386-2: Formula: (< v_~t4_pc~0_5 1) InVars {~t4_pc~0=v_~t4_pc~0_5} OutVars{~t4_pc~0=v_~t4_pc~0_5} AuxVars[] AssignedVars[] 204432#L386-2 [2680] L386-2-->L397: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 204429#L397 [4271] L397-->L847: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 204430#L847 [3084] L847-->L847-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} AuxVars[] AssignedVars[] 204692#L847-2 [3064] L847-2-->L405: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_4|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 204693#L405 [3708] L405-->L405-2: Formula: (> 1 v_~t5_pc~0_5) InVars {~t5_pc~0=v_~t5_pc~0_5} OutVars{~t5_pc~0=v_~t5_pc~0_5} AuxVars[] AssignedVars[] 204594#L405-2 [2940] L405-2-->L416: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 204630#L416 [4272] L416-->L855: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 204702#L855 [3091] L855-->L855-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_12} AuxVars[] AssignedVars[] 204703#L855-2 [3093] L855-2-->L424: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_4|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 204298#L424 [3713] L424-->L424-2: Formula: (< v_~t6_pc~0_5 1) InVars {~t6_pc~0=v_~t6_pc~0_5} OutVars{~t6_pc~0=v_~t6_pc~0_5} AuxVars[] AssignedVars[] 204299#L424-2 [2503] L424-2-->L435: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 204295#L435 [4273] L435-->L863: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___5~0_49 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_28|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_28|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 204218#L863 [2425] L863-->L863-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___5~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} AuxVars[] AssignedVars[] 204190#L863-2 [3719] L863-2-->L733-1: Formula: (> v_~M_E~0_15 1) InVars {~M_E~0=v_~M_E~0_15} OutVars{~M_E~0=v_~M_E~0_15} AuxVars[] AssignedVars[] 204191#L733-1 [3722] L733-1-->L738-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 204646#L738-1 [3723] L738-1-->L743-1: Formula: (< 1 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 204316#L743-1 [3726] L743-1-->L748-1: Formula: (< 1 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 204317#L748-1 [3728] L748-1-->L753-1: Formula: (> v_~T4_E~0_10 1) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 204198#L753-1 [3729] L753-1-->L758-1: Formula: (< 1 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 204199#L758-1 [3731] L758-1-->L763-1: Formula: (> v_~T6_E~0_10 1) InVars {~T6_E~0=v_~T6_E~0_10} OutVars{~T6_E~0=v_~T6_E~0_10} AuxVars[] AssignedVars[] 204272#L763-1 [3733] L763-1-->L768-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 204273#L768-1 [3736] L768-1-->L773-1: Formula: (< 1 v_~E_2~0_14) InVars {~E_2~0=v_~E_2~0_14} OutVars{~E_2~0=v_~E_2~0_14} AuxVars[] AssignedVars[] 204500#L773-1 [3737] L773-1-->L778-1: Formula: (< 1 v_~E_3~0_14) InVars {~E_3~0=v_~E_3~0_14} OutVars{~E_3~0=v_~E_3~0_14} AuxVars[] AssignedVars[] 204501#L778-1 [3740] L778-1-->L783-1: Formula: (< 1 v_~E_4~0_14) InVars {~E_4~0=v_~E_4~0_14} OutVars{~E_4~0=v_~E_4~0_14} AuxVars[] AssignedVars[] 204370#L783-1 [3741] L783-1-->L788-1: Formula: (< 1 v_~E_5~0_14) InVars {~E_5~0=v_~E_5~0_14} OutVars{~E_5~0=v_~E_5~0_14} AuxVars[] AssignedVars[] 204371#L788-1 [3744] L788-1-->L1014-1: Formula: (< 1 v_~E_6~0_14) InVars {~E_6~0=v_~E_6~0_14} OutVars{~E_6~0=v_~E_6~0_14} AuxVars[] AssignedVars[] 204212#L1014-1 [2020-06-22 00:13:36,471 INFO L796 eck$LassoCheckResult]: Loop: 204212#L1014-1 [4274] L1014-1-->L635: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp_ndt_7~0=v_ULTIMATE.start_eval_~tmp_ndt_7~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp_ndt_7~0] 204404#L635 [4275] L635-->L494: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_37} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 206834#L494 [3745] L494-->L498: Formula: (< v_~m_st~0_9 0) InVars {~m_st~0=v_~m_st~0_9} OutVars{~m_st~0=v_~m_st~0_9} AuxVars[] AssignedVars[] 206827#L498 [3749] L498-->L502: Formula: (< v_~t1_st~0_9 0) InVars {~t1_st~0=v_~t1_st~0_9} OutVars{~t1_st~0=v_~t1_st~0_9} AuxVars[] AssignedVars[] 206828#L502 [3753] L502-->L506: Formula: (> v_~t2_st~0_9 0) InVars {~t2_st~0=v_~t2_st~0_9} OutVars{~t2_st~0=v_~t2_st~0_9} AuxVars[] AssignedVars[] 206829#L506 [3760] L506-->L510: Formula: (< 0 v_~t3_st~0_10) InVars {~t3_st~0=v_~t3_st~0_10} OutVars{~t3_st~0=v_~t3_st~0_10} AuxVars[] AssignedVars[] 206830#L510 [3765] L510-->L514: Formula: (> 0 v_~t4_st~0_11) InVars {~t4_st~0=v_~t4_st~0_11} OutVars{~t4_st~0=v_~t4_st~0_11} AuxVars[] AssignedVars[] 206833#L514 [3773] L514-->L518: Formula: (> v_~t5_st~0_11 0) InVars {~t5_st~0=v_~t5_st~0_11} OutVars{~t5_st~0=v_~t5_st~0_11} AuxVars[] AssignedVars[] 206831#L518 [3783] L518-->L531: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_28 0) (< 0 v_~t6_st~0_11)) InVars {~t6_st~0=v_~t6_st~0_11} OutVars{~t6_st~0=v_~t6_st~0_11, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_28} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 206832#L531 [4276] L531-->L546: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 210596#L546 [4278] L546-->L660-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 210595#L660-2 [3747] L660-2-->L660-4: Formula: (> v_~M_E~0_30 0) InVars {~M_E~0=v_~M_E~0_30} OutVars{~M_E~0=v_~M_E~0_30} AuxVars[] AssignedVars[] 210594#L660-4 [3058] L660-4-->L665-3: Formula: (and (= v_~T1_E~0_11 1) (= v_~T1_E~0_12 0)) InVars {~T1_E~0=v_~T1_E~0_12} OutVars{~T1_E~0=v_~T1_E~0_11} AuxVars[] AssignedVars[~T1_E~0] 204183#L665-3 [3756] L665-3-->L670-3: Formula: (< 0 v_~T2_E~0_13) InVars {~T2_E~0=v_~T2_E~0_13} OutVars{~T2_E~0=v_~T2_E~0_13} AuxVars[] AssignedVars[] 204184#L670-3 [3762] L670-3-->L675-3: Formula: (< 0 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 210584#L675-3 [3768] L675-3-->L680-3: Formula: (> v_~T4_E~0_13 0) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 210583#L680-3 [3776] L680-3-->L685-3: Formula: (< 0 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 204513#L685-3 [3785] L685-3-->L690-3: Formula: (> v_~T6_E~0_13 0) InVars {~T6_E~0=v_~T6_E~0_13} OutVars{~T6_E~0=v_~T6_E~0_13} AuxVars[] AssignedVars[] 204514#L690-3 [3795] L690-3-->L695-3: Formula: (< 0 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 204365#L695-3 [3805] L695-3-->L700-3: Formula: (< 0 v_~E_2~0_31) InVars {~E_2~0=v_~E_2~0_31} OutVars{~E_2~0=v_~E_2~0_31} AuxVars[] AssignedVars[] 204366#L700-3 [3818] L700-3-->L705-3: Formula: (< 0 v_~E_3~0_31) InVars {~E_3~0=v_~E_3~0_31} OutVars{~E_3~0=v_~E_3~0_31} AuxVars[] AssignedVars[] 204443#L705-3 [2688] L705-3-->L710-3: Formula: (and (= v_~E_4~0_29 1) (= 0 v_~E_4~0_30)) InVars {~E_4~0=v_~E_4~0_30} OutVars{~E_4~0=v_~E_4~0_29} AuxVars[] AssignedVars[~E_4~0] 204310#L710-3 [3844] L710-3-->L715-3: Formula: (< 0 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 204311#L715-3 [3854] L715-3-->L720-3: Formula: (< 0 v_~E_6~0_31) InVars {~E_6~0=v_~E_6~0_31} OutVars{~E_6~0=v_~E_6~0_31} AuxVars[] AssignedVars[] 204174#L720-3 [2388] L720-3-->L310-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_43, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_43, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_25|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_25|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_25|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_43, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_43, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_43, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_25|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_25|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_25|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_25|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_43, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_25|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_43, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_43} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 204175#L310-21 [3870] L310-21-->L310-23: Formula: (< v_~m_pc~0_24 1) InVars {~m_pc~0=v_~m_pc~0_24} OutVars{~m_pc~0=v_~m_pc~0_24} AuxVars[] AssignedVars[] 204511#L310-23 [2785] L310-23-->L321-7: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_47 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_47} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 210593#L321-7 [4303] L321-7-->L815-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 210592#L815-21 [2667] L815-21-->L815-23: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_48) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_48} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_48} AuxVars[] AssignedVars[] 210591#L815-23 [2638] L815-23-->L329-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 210590#L329-21 [3911] L329-21-->L329-23: Formula: (< v_~t1_pc~0_24 1) InVars {~t1_pc~0=v_~t1_pc~0_24} OutVars{~t1_pc~0=v_~t1_pc~0_24} AuxVars[] AssignedVars[] 210422#L329-23 [3052] L329-23-->L340-7: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 210587#L340-7 [4310] L340-7-->L823-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 210588#L823-21 [2931] L823-21-->L823-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} AuxVars[] AssignedVars[] 210580#L823-23 [2934] L823-23-->L348-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_25|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 210581#L348-21 [3953] L348-21-->L348-23: Formula: (> 1 v_~t2_pc~0_24) InVars {~t2_pc~0=v_~t2_pc~0_24} OutVars{~t2_pc~0=v_~t2_pc~0_24} AuxVars[] AssignedVars[] 210573#L348-23 [3319] L348-23-->L359-7: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 210574#L359-7 [4317] L359-7-->L831-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 210569#L831-21 [2490] L831-21-->L831-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} AuxVars[] AssignedVars[] 210570#L831-23 [3197] L831-23-->L367-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_25|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 210566#L367-21 [3995] L367-21-->L367-23: Formula: (> v_~t3_pc~0_24 1) InVars {~t3_pc~0=v_~t3_pc~0_24} OutVars{~t3_pc~0=v_~t3_pc~0_24} AuxVars[] AssignedVars[] 210565#L367-23 [2385] L367-23-->L378-7: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 204225#L378-7 [4324] L378-7-->L839-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 204226#L839-21 [2715] L839-21-->L839-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_48} AuxVars[] AssignedVars[] 204462#L839-23 [2722] L839-23-->L386-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_49, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 204374#L386-21 [4038] L386-21-->L386-23: Formula: (> 1 v_~t4_pc~0_24) InVars {~t4_pc~0=v_~t4_pc~0_24} OutVars{~t4_pc~0=v_~t4_pc~0_24} AuxVars[] AssignedVars[] 204375#L386-23 [2623] L386-23-->L397-7: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 204380#L397-7 [4331] L397-7-->L847-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 204419#L847-21 [3021] L847-21-->L847-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_48} AuxVars[] AssignedVars[] 204656#L847-23 [2983] L847-23-->L405-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_25|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 204605#L405-21 [4080] L405-21-->L405-23: Formula: (> v_~t5_pc~0_24 1) InVars {~t5_pc~0=v_~t5_pc~0_24} OutVars{~t5_pc~0=v_~t5_pc~0_24} AuxVars[] AssignedVars[] 204589#L405-23 [2891] L405-23-->L416-7: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 204597#L416-7 [4338] L416-7-->L855-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 210538#L855-21 [3251] L855-21-->L855-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} AuxVars[] AssignedVars[] 204783#L855-23 [3257] L855-23-->L424-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_25|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 204755#L424-21 [4122] L424-21-->L424-23: Formula: (> 1 v_~t6_pc~0_24) InVars {~t6_pc~0=v_~t6_pc~0_24} OutVars{~t6_pc~0=v_~t6_pc~0_24} AuxVars[] AssignedVars[] 204756#L424-23 [3177] L424-23-->L435-7: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 210536#L435-7 [4340] L435-7-->L863-21: Formula: (and (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___5~0_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_35|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_41|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 210535#L863-21 [4136] L863-21-->L863-23: Formula: (and (= v_~t6_st~0_22 0) (> v_ULTIMATE.start_activate_threads_~tmp___5~0_47 0)) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} OutVars{~t6_st~0=v_~t6_st~0_22, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_47} AuxVars[] AssignedVars[~t6_st~0] 204328#L863-23 [4138] L863-23-->L733-3: Formula: (> v_~M_E~0_35 1) InVars {~M_E~0=v_~M_E~0_35} OutVars{~M_E~0=v_~M_E~0_35} AuxVars[] AssignedVars[] 204329#L733-3 [3184] L733-3-->L738-3: Formula: (and (= v_~T1_E~0_15 1) (= v_~T1_E~0_14 2)) InVars {~T1_E~0=v_~T1_E~0_15} OutVars{~T1_E~0=v_~T1_E~0_14} AuxVars[] AssignedVars[~T1_E~0] 204650#L738-3 [4142] L738-3-->L743-3: Formula: (< 1 v_~T2_E~0_16) InVars {~T2_E~0=v_~T2_E~0_16} OutVars{~T2_E~0=v_~T2_E~0_16} AuxVars[] AssignedVars[] 204306#L743-3 [4143] L743-3-->L748-3: Formula: (< 1 v_~T3_E~0_16) InVars {~T3_E~0=v_~T3_E~0_16} OutVars{~T3_E~0=v_~T3_E~0_16} AuxVars[] AssignedVars[] 204307#L748-3 [4145] L748-3-->L753-3: Formula: (> v_~T4_E~0_16 1) InVars {~T4_E~0=v_~T4_E~0_16} OutVars{~T4_E~0=v_~T4_E~0_16} AuxVars[] AssignedVars[] 204165#L753-3 [4148] L753-3-->L758-3: Formula: (< 1 v_~T5_E~0_16) InVars {~T5_E~0=v_~T5_E~0_16} OutVars{~T5_E~0=v_~T5_E~0_16} AuxVars[] AssignedVars[] 204166#L758-3 [4149] L758-3-->L763-3: Formula: (> v_~T6_E~0_16 1) InVars {~T6_E~0=v_~T6_E~0_16} OutVars{~T6_E~0=v_~T6_E~0_16} AuxVars[] AssignedVars[] 204258#L763-3 [4151] L763-3-->L768-3: Formula: (< 1 v_~E_1~0_36) InVars {~E_1~0=v_~E_1~0_36} OutVars{~E_1~0=v_~E_1~0_36} AuxVars[] AssignedVars[] 204259#L768-3 [4154] L768-3-->L773-3: Formula: (< 1 v_~E_2~0_36) InVars {~E_2~0=v_~E_2~0_36} OutVars{~E_2~0=v_~E_2~0_36} AuxVars[] AssignedVars[] 204507#L773-3 [4156] L773-3-->L778-3: Formula: (< 1 v_~E_3~0_36) InVars {~E_3~0=v_~E_3~0_36} OutVars{~E_3~0=v_~E_3~0_36} AuxVars[] AssignedVars[] 204508#L778-3 [3308] L778-3-->L783-3: Formula: (and (= 1 v_~E_4~0_35) (= v_~E_4~0_34 2)) InVars {~E_4~0=v_~E_4~0_35} OutVars{~E_4~0=v_~E_4~0_34} AuxVars[] AssignedVars[~E_4~0] 204376#L783-3 [4160] L783-3-->L788-3: Formula: (< 1 v_~E_5~0_36) InVars {~E_5~0=v_~E_5~0_36} OutVars{~E_5~0=v_~E_5~0_36} AuxVars[] AssignedVars[] 204377#L788-3 [4162] L788-3-->L793-3: Formula: (< 1 v_~E_6~0_36) InVars {~E_6~0=v_~E_6~0_36} OutVars{~E_6~0=v_~E_6~0_36} AuxVars[] AssignedVars[] 204647#L793-3 [2966] L793-3-->L494-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_30} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 204648#L494-1 [2878] L494-1-->L531-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33 1) (= 0 v_~m_st~0_21)) InVars {~m_st~0=v_~m_st~0_21} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33, ~m_st~0=v_~m_st~0_21} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 210317#L531-1 [4341] L531-1-->L1033: Formula: (and (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp~3] 204606#L1033 [4169] L1033-->L1033-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_6) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} AuxVars[] AssignedVars[] 204215#L1033-1 [2919] L1033-1-->L494-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_3|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_6, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_exists_runnable_thread_~__retres1~7, ULTIMATE.start_stop_simulation_#res] 204609#L494-2 [2882] L494-2-->L531-2: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9 1) (= v_~m_st~0_6 0)) InVars {~m_st~0=v_~m_st~0_6} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9, ~m_st~0=v_~m_st~0_6} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 210605#L531-2 [4343] L531-2-->L988: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 210604#L988 [3240] L988-->L995: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 204211#L995 [4354] L995-->L1014-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_6|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_#t~ret17, ULTIMATE.start_stop_simulation_#res] 204212#L1014-1 [2020-06-22 00:13:36,472 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:36,472 INFO L82 PathProgramCache]: Analyzing trace with hash -1932600016, now seen corresponding path program 7 times [2020-06-22 00:13:36,472 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:36,472 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:36,473 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:36,473 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:36,473 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:36,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:13:36,481 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:13:36,490 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:36,490 INFO L82 PathProgramCache]: Analyzing trace with hash -749537824, now seen corresponding path program 1 times [2020-06-22 00:13:36,490 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:36,490 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:36,491 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:36,491 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:36,491 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:36,495 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:36,521 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:36,521 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:36,521 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2020-06-22 00:13:36,522 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-06-22 00:13:36,522 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2020-06-22 00:13:36,522 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2020-06-22 00:13:36,522 INFO L87 Difference]: Start difference. First operand 6464 states and 9909 transitions. cyclomatic complexity: 3446 Second operand 6 states. [2020-06-22 00:13:37,838 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-06-22 00:13:37,838 INFO L93 Difference]: Finished difference Result 10401 states and 15871 transitions. [2020-06-22 00:13:37,838 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2020-06-22 00:13:37,838 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10401 states and 15871 transitions. [2020-06-22 00:13:37,874 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 10328 [2020-06-22 00:13:37,895 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10401 states to 10401 states and 15871 transitions. [2020-06-22 00:13:37,895 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10401 [2020-06-22 00:13:37,900 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10401 [2020-06-22 00:13:37,901 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10401 states and 15871 transitions. [2020-06-22 00:13:37,907 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-06-22 00:13:37,907 INFO L706 BuchiCegarLoop]: Abstraction has 10401 states and 15871 transitions. [2020-06-22 00:13:37,911 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10401 states and 15871 transitions. [2020-06-22 00:13:37,969 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10401 to 6480. [2020-06-22 00:13:37,969 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6480 states. [2020-06-22 00:13:37,980 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6480 states to 6480 states and 9820 transitions. [2020-06-22 00:13:37,980 INFO L729 BuchiCegarLoop]: Abstraction has 6480 states and 9820 transitions. [2020-06-22 00:13:37,980 INFO L609 BuchiCegarLoop]: Abstraction has 6480 states and 9820 transitions. [2020-06-22 00:13:37,980 INFO L442 BuchiCegarLoop]: ======== Iteration 39============ [2020-06-22 00:13:37,980 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6480 states and 9820 transitions. [2020-06-22 00:13:37,994 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 6408 [2020-06-22 00:13:37,995 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-06-22 00:13:37,995 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-06-22 00:13:37,996 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:37,996 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:37,997 INFO L794 eck$LassoCheckResult]: Stem: 221561#ULTIMATE.startENTRY [4266] ULTIMATE.startENTRY-->L444: Formula: (and (= 1 v_~t6_i~0_7) (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~M_E~0_37 2) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 0 v_~t6_pc~0_26) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_6~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= v_~T6_E~0_18 2) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~t6_st~0_24) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t6_pc~0=v_~t6_pc~0_26, ~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~T6_E~0=v_~T6_E~0_18, ~M_E~0=v_~M_E~0_37, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ~T4_E~0=v_~T4_E~0_18, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_4|, ~t6_i~0=v_~t6_i~0_7, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ULTIMATE.start_main_~__retres1~8=v_ULTIMATE.start_main_~__retres1~8_6, ~T2_E~0=v_~T2_E~0_18, ~t6_st~0=v_~t6_st~0_24, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_6~0=v_~E_6~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t6_pc~0, ~t5_i~0, ~t1_pc~0, ~t5_st~0, ~T6_E~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ~T4_E~0, ULTIMATE.start_start_simulation_#t~ret17, ~t6_i~0, ~t2_st~0, ~t2_pc~0, ULTIMATE.start_main_~__retres1~8, ~T2_E~0, ~t6_st~0, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_6~0, ULTIMATE.start_main_#res, ~E_2~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 221150#L444 [2453] L444-->L451-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 221151#L451-1 [3030] L451-1-->L456-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 221243#L456-1 [2574] L456-1-->L461-1: Formula: (and (= v_~t2_st~0_2 0) (= 1 v_~t2_i~0_3)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_2} AuxVars[] AssignedVars[~t2_st~0] 221244#L461-1 [2880] L461-1-->L466-1: Formula: (and (= v_~t3_st~0_3 0) (= v_~t3_i~0_3 1)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_3, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 221152#L466-1 [2457] L466-1-->L471-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 221153#L471-1 [3209] L471-1-->L476-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 221400#L476-1 [2761] L476-1-->L481-1: Formula: (and (= 1 v_~t6_i~0_3) (= v_~t6_st~0_4 0)) InVars {~t6_i~0=v_~t6_i~0_3} OutVars{~t6_st~0=v_~t6_st~0_4, ~t6_i~0=v_~t6_i~0_3} AuxVars[] AssignedVars[~t6_st~0] 221401#L481-1 [3652] L481-1-->L660-1: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 221582#L660-1 [3654] L660-1-->L665-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 221067#L665-1 [3655] L665-1-->L670-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 221068#L670-1 [3658] L670-1-->L675-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 221159#L675-1 [3659] L675-1-->L680-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 221160#L680-1 [3661] L680-1-->L685-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 221412#L685-1 [3663] L685-1-->L690-1: Formula: (< 0 v_~T6_E~0_4) InVars {~T6_E~0=v_~T6_E~0_4} OutVars{~T6_E~0=v_~T6_E~0_4} AuxVars[] AssignedVars[] 221413#L690-1 [3665] L690-1-->L695-1: Formula: (> v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 221286#L695-1 [3668] L695-1-->L700-1: Formula: (> v_~E_2~0_6 0) InVars {~E_2~0=v_~E_2~0_6} OutVars{~E_2~0=v_~E_2~0_6} AuxVars[] AssignedVars[] 221287#L700-1 [3670] L700-1-->L705-1: Formula: (> v_~E_3~0_6 0) InVars {~E_3~0=v_~E_3~0_6} OutVars{~E_3~0=v_~E_3~0_6} AuxVars[] AssignedVars[] 221542#L705-1 [3672] L705-1-->L710-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 221221#L710-1 [3674] L710-1-->L715-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 221222#L715-1 [3675] L715-1-->L720-1: Formula: (> v_~E_6~0_4 0) InVars {~E_6~0=v_~E_6~0_4} OutVars{~E_6~0=v_~E_6~0_4} AuxVars[] AssignedVars[] 221103#L720-1 [2412] L720-1-->L310: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_7, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_4|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_4|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_7, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_4, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_4, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_2|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_2|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_4|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_4|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_7, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_2|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_4} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 221104#L310 [3678] L310-->L310-2: Formula: (< v_~m_pc~0_5 1) InVars {~m_pc~0=v_~m_pc~0_5} OutVars{~m_pc~0=v_~m_pc~0_5} AuxVars[] AssignedVars[] 221259#L310-2 [2805] L310-2-->L321: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_11 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 221257#L321 [4267] L321-->L815: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 221258#L815 [2976] L815-->L815-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_12) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} AuxVars[] AssignedVars[] 221537#L815-2 [2961] L815-2-->L329: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 221465#L329 [3683] L329-->L329-2: Formula: (< v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 221466#L329-2 [2861] L329-2-->L340: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 221463#L340 [4268] L340-->L823: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 221464#L823 [3234] L823-->L823-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} AuxVars[] AssignedVars[] 221674#L823-2 [3235] L823-2-->L348: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_4|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 221633#L348 [3690] L348-->L348-2: Formula: (< v_~t2_pc~0_5 1) InVars {~t2_pc~0=v_~t2_pc~0_5} OutVars{~t2_pc~0=v_~t2_pc~0_5} AuxVars[] AssignedVars[] 221635#L348-2 [3153] L348-2-->L359: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 221632#L359 [4269] L359-->L831: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 221228#L831 [2537] L831-->L831-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} AuxVars[] AssignedVars[] 221216#L831-2 [2520] L831-2-->L367: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_4|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 221155#L367 [3695] L367-->L367-2: Formula: (> 1 v_~t3_pc~0_5) InVars {~t3_pc~0=v_~t3_pc~0_5} OutVars{~t3_pc~0=v_~t3_pc~0_5} AuxVars[] AssignedVars[] 221133#L367-2 [2438] L367-2-->L378: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 221134#L378 [4270] L378-->L839: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 221154#L839 [2791] L839-->L839-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} AuxVars[] AssignedVars[] 221426#L839-2 [2794] L839-2-->L386: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_7, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 221337#L386 [3702] L386-->L386-2: Formula: (< v_~t4_pc~0_5 1) InVars {~t4_pc~0=v_~t4_pc~0_5} OutVars{~t4_pc~0=v_~t4_pc~0_5} AuxVars[] AssignedVars[] 221338#L386-2 [2680] L386-2-->L397: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 221335#L397 [4271] L397-->L847: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 221336#L847 [3084] L847-->L847-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} AuxVars[] AssignedVars[] 221588#L847-2 [3064] L847-2-->L405: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_4|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 221589#L405 [3708] L405-->L405-2: Formula: (> 1 v_~t5_pc~0_5) InVars {~t5_pc~0=v_~t5_pc~0_5} OutVars{~t5_pc~0=v_~t5_pc~0_5} AuxVars[] AssignedVars[] 221492#L405-2 [2940] L405-2-->L416: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 221527#L416 [4272] L416-->L855: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 221599#L855 [3091] L855-->L855-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_12} AuxVars[] AssignedVars[] 221600#L855-2 [3093] L855-2-->L424: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_4|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 221198#L424 [3713] L424-->L424-2: Formula: (< v_~t6_pc~0_5 1) InVars {~t6_pc~0=v_~t6_pc~0_5} OutVars{~t6_pc~0=v_~t6_pc~0_5} AuxVars[] AssignedVars[] 221199#L424-2 [2503] L424-2-->L435: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 221197#L435 [4273] L435-->L863: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___5~0_49 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_28|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_28|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 221119#L863 [2425] L863-->L863-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___5~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} AuxVars[] AssignedVars[] 221092#L863-2 [3719] L863-2-->L733-1: Formula: (> v_~M_E~0_15 1) InVars {~M_E~0=v_~M_E~0_15} OutVars{~M_E~0=v_~M_E~0_15} AuxVars[] AssignedVars[] 221093#L733-1 [3722] L733-1-->L738-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 221539#L738-1 [3723] L738-1-->L743-1: Formula: (< 1 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 221219#L743-1 [3726] L743-1-->L748-1: Formula: (< 1 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 221220#L748-1 [3728] L748-1-->L753-1: Formula: (> v_~T4_E~0_10 1) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 221097#L753-1 [3729] L753-1-->L758-1: Formula: (< 1 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 221098#L758-1 [3731] L758-1-->L763-1: Formula: (> v_~T6_E~0_10 1) InVars {~T6_E~0=v_~T6_E~0_10} OutVars{~T6_E~0=v_~T6_E~0_10} AuxVars[] AssignedVars[] 221171#L763-1 [3733] L763-1-->L768-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 221172#L768-1 [3736] L768-1-->L773-1: Formula: (< 1 v_~E_2~0_14) InVars {~E_2~0=v_~E_2~0_14} OutVars{~E_2~0=v_~E_2~0_14} AuxVars[] AssignedVars[] 221407#L773-1 [3737] L773-1-->L778-1: Formula: (< 1 v_~E_3~0_14) InVars {~E_3~0=v_~E_3~0_14} OutVars{~E_3~0=v_~E_3~0_14} AuxVars[] AssignedVars[] 221408#L778-1 [3740] L778-1-->L783-1: Formula: (< 1 v_~E_4~0_14) InVars {~E_4~0=v_~E_4~0_14} OutVars{~E_4~0=v_~E_4~0_14} AuxVars[] AssignedVars[] 221280#L783-1 [3741] L783-1-->L788-1: Formula: (< 1 v_~E_5~0_14) InVars {~E_5~0=v_~E_5~0_14} OutVars{~E_5~0=v_~E_5~0_14} AuxVars[] AssignedVars[] 221281#L788-1 [3744] L788-1-->L1014-1: Formula: (< 1 v_~E_6~0_14) InVars {~E_6~0=v_~E_6~0_14} OutVars{~E_6~0=v_~E_6~0_14} AuxVars[] AssignedVars[] 221645#L1014-1 [2020-06-22 00:13:37,999 INFO L796 eck$LassoCheckResult]: Loop: 221645#L1014-1 [4274] L1014-1-->L635: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp_ndt_7~0=v_ULTIMATE.start_eval_~tmp_ndt_7~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp_ndt_7~0] 222242#L635 [4275] L635-->L494: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_37} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 222239#L494 [3745] L494-->L498: Formula: (< v_~m_st~0_9 0) InVars {~m_st~0=v_~m_st~0_9} OutVars{~m_st~0=v_~m_st~0_9} AuxVars[] AssignedVars[] 222232#L498 [3749] L498-->L502: Formula: (< v_~t1_st~0_9 0) InVars {~t1_st~0=v_~t1_st~0_9} OutVars{~t1_st~0=v_~t1_st~0_9} AuxVars[] AssignedVars[] 222233#L502 [3753] L502-->L506: Formula: (> v_~t2_st~0_9 0) InVars {~t2_st~0=v_~t2_st~0_9} OutVars{~t2_st~0=v_~t2_st~0_9} AuxVars[] AssignedVars[] 222234#L506 [3760] L506-->L510: Formula: (< 0 v_~t3_st~0_10) InVars {~t3_st~0=v_~t3_st~0_10} OutVars{~t3_st~0=v_~t3_st~0_10} AuxVars[] AssignedVars[] 222235#L510 [3765] L510-->L514: Formula: (> 0 v_~t4_st~0_11) InVars {~t4_st~0=v_~t4_st~0_11} OutVars{~t4_st~0=v_~t4_st~0_11} AuxVars[] AssignedVars[] 222238#L514 [3773] L514-->L518: Formula: (> v_~t5_st~0_11 0) InVars {~t5_st~0=v_~t5_st~0_11} OutVars{~t5_st~0=v_~t5_st~0_11} AuxVars[] AssignedVars[] 222236#L518 [3783] L518-->L531: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_28 0) (< 0 v_~t6_st~0_11)) InVars {~t6_st~0=v_~t6_st~0_11} OutVars{~t6_st~0=v_~t6_st~0_11, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_28} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 222237#L531 [4276] L531-->L546: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 226845#L546 [4278] L546-->L660-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 226842#L660-2 [3747] L660-2-->L660-4: Formula: (> v_~M_E~0_30 0) InVars {~M_E~0=v_~M_E~0_30} OutVars{~M_E~0=v_~M_E~0_30} AuxVars[] AssignedVars[] 226839#L660-4 [3058] L660-4-->L665-3: Formula: (and (= v_~T1_E~0_11 1) (= v_~T1_E~0_12 0)) InVars {~T1_E~0=v_~T1_E~0_12} OutVars{~T1_E~0=v_~T1_E~0_11} AuxVars[] AssignedVars[~T1_E~0] 226836#L665-3 [3756] L665-3-->L670-3: Formula: (< 0 v_~T2_E~0_13) InVars {~T2_E~0=v_~T2_E~0_13} OutVars{~T2_E~0=v_~T2_E~0_13} AuxVars[] AssignedVars[] 226833#L670-3 [3762] L670-3-->L675-3: Formula: (< 0 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 226830#L675-3 [3768] L675-3-->L680-3: Formula: (> v_~T4_E~0_13 0) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 226827#L680-3 [3776] L680-3-->L685-3: Formula: (< 0 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 226824#L685-3 [3785] L685-3-->L690-3: Formula: (> v_~T6_E~0_13 0) InVars {~T6_E~0=v_~T6_E~0_13} OutVars{~T6_E~0=v_~T6_E~0_13} AuxVars[] AssignedVars[] 226821#L690-3 [3795] L690-3-->L695-3: Formula: (< 0 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 226818#L695-3 [3805] L695-3-->L700-3: Formula: (< 0 v_~E_2~0_31) InVars {~E_2~0=v_~E_2~0_31} OutVars{~E_2~0=v_~E_2~0_31} AuxVars[] AssignedVars[] 226815#L700-3 [3818] L700-3-->L705-3: Formula: (< 0 v_~E_3~0_31) InVars {~E_3~0=v_~E_3~0_31} OutVars{~E_3~0=v_~E_3~0_31} AuxVars[] AssignedVars[] 226812#L705-3 [2688] L705-3-->L710-3: Formula: (and (= v_~E_4~0_29 1) (= 0 v_~E_4~0_30)) InVars {~E_4~0=v_~E_4~0_30} OutVars{~E_4~0=v_~E_4~0_29} AuxVars[] AssignedVars[~E_4~0] 226809#L710-3 [3844] L710-3-->L715-3: Formula: (< 0 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 226806#L715-3 [3854] L715-3-->L720-3: Formula: (< 0 v_~E_6~0_31) InVars {~E_6~0=v_~E_6~0_31} OutVars{~E_6~0=v_~E_6~0_31} AuxVars[] AssignedVars[] 226803#L720-3 [2388] L720-3-->L310-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_43, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_43, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_25|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_25|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_25|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_43, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_43, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_43, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_25|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_25|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_25|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_25|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_43, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_25|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_43, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_43} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 226798#L310-21 [3870] L310-21-->L310-23: Formula: (< v_~m_pc~0_24 1) InVars {~m_pc~0=v_~m_pc~0_24} OutVars{~m_pc~0=v_~m_pc~0_24} AuxVars[] AssignedVars[] 226797#L310-23 [2785] L310-23-->L321-7: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_47 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_47} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 226795#L321-7 [4303] L321-7-->L815-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 226793#L815-21 [2667] L815-21-->L815-23: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_48) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_48} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_48} AuxVars[] AssignedVars[] 226791#L815-23 [2638] L815-23-->L329-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 226789#L329-21 [3911] L329-21-->L329-23: Formula: (< v_~t1_pc~0_24 1) InVars {~t1_pc~0=v_~t1_pc~0_24} OutVars{~t1_pc~0=v_~t1_pc~0_24} AuxVars[] AssignedVars[] 225907#L329-23 [3052] L329-23-->L340-7: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 226787#L340-7 [4310] L340-7-->L823-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 226785#L823-21 [2931] L823-21-->L823-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} AuxVars[] AssignedVars[] 226783#L823-23 [2934] L823-23-->L348-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_25|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 226779#L348-21 [3953] L348-21-->L348-23: Formula: (> 1 v_~t2_pc~0_24) InVars {~t2_pc~0=v_~t2_pc~0_24} OutVars{~t2_pc~0=v_~t2_pc~0_24} AuxVars[] AssignedVars[] 226777#L348-23 [3319] L348-23-->L359-7: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 226775#L359-7 [4317] L359-7-->L831-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 226773#L831-21 [2490] L831-21-->L831-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} AuxVars[] AssignedVars[] 226771#L831-23 [3197] L831-23-->L367-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_25|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 226768#L367-21 [3995] L367-21-->L367-23: Formula: (> v_~t3_pc~0_24 1) InVars {~t3_pc~0=v_~t3_pc~0_24} OutVars{~t3_pc~0=v_~t3_pc~0_24} AuxVars[] AssignedVars[] 226765#L367-23 [2385] L367-23-->L378-7: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 226763#L378-7 [4324] L378-7-->L839-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 226761#L839-21 [2715] L839-21-->L839-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_48} AuxVars[] AssignedVars[] 226759#L839-23 [2722] L839-23-->L386-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_49, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 226755#L386-21 [4038] L386-21-->L386-23: Formula: (> 1 v_~t4_pc~0_24) InVars {~t4_pc~0=v_~t4_pc~0_24} OutVars{~t4_pc~0=v_~t4_pc~0_24} AuxVars[] AssignedVars[] 226754#L386-23 [2623] L386-23-->L397-7: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 226753#L397-7 [4331] L397-7-->L847-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 226752#L847-21 [3021] L847-21-->L847-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_48} AuxVars[] AssignedVars[] 226751#L847-23 [2983] L847-23-->L405-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_25|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 226749#L405-21 [4080] L405-21-->L405-23: Formula: (> v_~t5_pc~0_24 1) InVars {~t5_pc~0=v_~t5_pc~0_24} OutVars{~t5_pc~0=v_~t5_pc~0_24} AuxVars[] AssignedVars[] 226748#L405-23 [2891] L405-23-->L416-7: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 226747#L416-7 [4338] L416-7-->L855-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 226746#L855-21 [3251] L855-21-->L855-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} AuxVars[] AssignedVars[] 226745#L855-23 [3257] L855-23-->L424-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_25|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 221643#L424-21 [4122] L424-21-->L424-23: Formula: (> 1 v_~t6_pc~0_24) InVars {~t6_pc~0=v_~t6_pc~0_24} OutVars{~t6_pc~0=v_~t6_pc~0_24} AuxVars[] AssignedVars[] 221644#L424-23 [3177] L424-23-->L435-7: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 223805#L435-7 [4340] L435-7-->L863-21: Formula: (and (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___5~0_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_35|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_41|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 223804#L863-21 [2570] L863-21-->L863-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___5~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_48} AuxVars[] AssignedVars[] 223803#L863-23 [4138] L863-23-->L733-3: Formula: (> v_~M_E~0_35 1) InVars {~M_E~0=v_~M_E~0_35} OutVars{~M_E~0=v_~M_E~0_35} AuxVars[] AssignedVars[] 223802#L733-3 [3184] L733-3-->L738-3: Formula: (and (= v_~T1_E~0_15 1) (= v_~T1_E~0_14 2)) InVars {~T1_E~0=v_~T1_E~0_15} OutVars{~T1_E~0=v_~T1_E~0_14} AuxVars[] AssignedVars[~T1_E~0] 223801#L738-3 [4142] L738-3-->L743-3: Formula: (< 1 v_~T2_E~0_16) InVars {~T2_E~0=v_~T2_E~0_16} OutVars{~T2_E~0=v_~T2_E~0_16} AuxVars[] AssignedVars[] 223800#L743-3 [4143] L743-3-->L748-3: Formula: (< 1 v_~T3_E~0_16) InVars {~T3_E~0=v_~T3_E~0_16} OutVars{~T3_E~0=v_~T3_E~0_16} AuxVars[] AssignedVars[] 223799#L748-3 [4145] L748-3-->L753-3: Formula: (> v_~T4_E~0_16 1) InVars {~T4_E~0=v_~T4_E~0_16} OutVars{~T4_E~0=v_~T4_E~0_16} AuxVars[] AssignedVars[] 223798#L753-3 [4148] L753-3-->L758-3: Formula: (< 1 v_~T5_E~0_16) InVars {~T5_E~0=v_~T5_E~0_16} OutVars{~T5_E~0=v_~T5_E~0_16} AuxVars[] AssignedVars[] 223797#L758-3 [4149] L758-3-->L763-3: Formula: (> v_~T6_E~0_16 1) InVars {~T6_E~0=v_~T6_E~0_16} OutVars{~T6_E~0=v_~T6_E~0_16} AuxVars[] AssignedVars[] 223796#L763-3 [4151] L763-3-->L768-3: Formula: (< 1 v_~E_1~0_36) InVars {~E_1~0=v_~E_1~0_36} OutVars{~E_1~0=v_~E_1~0_36} AuxVars[] AssignedVars[] 223795#L768-3 [4154] L768-3-->L773-3: Formula: (< 1 v_~E_2~0_36) InVars {~E_2~0=v_~E_2~0_36} OutVars{~E_2~0=v_~E_2~0_36} AuxVars[] AssignedVars[] 223794#L773-3 [4156] L773-3-->L778-3: Formula: (< 1 v_~E_3~0_36) InVars {~E_3~0=v_~E_3~0_36} OutVars{~E_3~0=v_~E_3~0_36} AuxVars[] AssignedVars[] 223793#L778-3 [3308] L778-3-->L783-3: Formula: (and (= 1 v_~E_4~0_35) (= v_~E_4~0_34 2)) InVars {~E_4~0=v_~E_4~0_35} OutVars{~E_4~0=v_~E_4~0_34} AuxVars[] AssignedVars[~E_4~0] 223792#L783-3 [4160] L783-3-->L788-3: Formula: (< 1 v_~E_5~0_36) InVars {~E_5~0=v_~E_5~0_36} OutVars{~E_5~0=v_~E_5~0_36} AuxVars[] AssignedVars[] 223791#L788-3 [4162] L788-3-->L793-3: Formula: (< 1 v_~E_6~0_36) InVars {~E_6~0=v_~E_6~0_36} OutVars{~E_6~0=v_~E_6~0_36} AuxVars[] AssignedVars[] 223790#L793-3 [2966] L793-3-->L494-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_30} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 223789#L494-1 [2878] L494-1-->L531-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33 1) (= 0 v_~m_st~0_21)) InVars {~m_st~0=v_~m_st~0_21} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33, ~m_st~0=v_~m_st~0_21} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 223781#L531-1 [4341] L531-1-->L1033: Formula: (and (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp~3] 223778#L1033 [4169] L1033-->L1033-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_6) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} AuxVars[] AssignedVars[] 223776#L1033-1 [2919] L1033-1-->L494-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_3|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_6, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_exists_runnable_thread_~__retres1~7, ULTIMATE.start_stop_simulation_#res] 223769#L494-2 [2882] L494-2-->L531-2: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9 1) (= v_~m_st~0_6 0)) InVars {~m_st~0=v_~m_st~0_6} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9, ~m_st~0=v_~m_st~0_6} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 223768#L531-2 [4343] L531-2-->L988: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 223767#L988 [3240] L988-->L995: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 223766#L995 [4354] L995-->L1014-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_6|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_#t~ret17, ULTIMATE.start_stop_simulation_#res] 221645#L1014-1 [2020-06-22 00:13:37,999 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:37,999 INFO L82 PathProgramCache]: Analyzing trace with hash -1932600016, now seen corresponding path program 8 times [2020-06-22 00:13:37,999 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:37,999 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:38,000 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:38,000 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:38,000 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:38,004 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:13:38,008 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:13:38,017 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:38,017 INFO L82 PathProgramCache]: Analyzing trace with hash -135562686, now seen corresponding path program 1 times [2020-06-22 00:13:38,017 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:38,017 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:38,018 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:38,018 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2020-06-22 00:13:38,018 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:38,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:38,045 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:38,045 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:38,045 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-06-22 00:13:38,046 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-06-22 00:13:38,046 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-06-22 00:13:38,046 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-06-22 00:13:38,046 INFO L87 Difference]: Start difference. First operand 6480 states and 9820 transitions. cyclomatic complexity: 3341 Second operand 3 states. [2020-06-22 00:13:38,741 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-06-22 00:13:38,741 INFO L93 Difference]: Finished difference Result 12468 states and 18808 transitions. [2020-06-22 00:13:38,742 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-06-22 00:13:38,742 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12468 states and 18808 transitions. [2020-06-22 00:13:38,789 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12396 [2020-06-22 00:13:38,819 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12468 states to 12468 states and 18808 transitions. [2020-06-22 00:13:38,819 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12468 [2020-06-22 00:13:38,826 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12468 [2020-06-22 00:13:38,826 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12468 states and 18808 transitions. [2020-06-22 00:13:38,834 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-06-22 00:13:38,834 INFO L706 BuchiCegarLoop]: Abstraction has 12468 states and 18808 transitions. [2020-06-22 00:13:38,839 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12468 states and 18808 transitions. [2020-06-22 00:13:38,926 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12468 to 12468. [2020-06-22 00:13:38,926 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12468 states. [2020-06-22 00:13:38,949 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12468 states to 12468 states and 18808 transitions. [2020-06-22 00:13:38,949 INFO L729 BuchiCegarLoop]: Abstraction has 12468 states and 18808 transitions. [2020-06-22 00:13:38,949 INFO L609 BuchiCegarLoop]: Abstraction has 12468 states and 18808 transitions. [2020-06-22 00:13:38,949 INFO L442 BuchiCegarLoop]: ======== Iteration 40============ [2020-06-22 00:13:38,949 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12468 states and 18808 transitions. [2020-06-22 00:13:38,985 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12396 [2020-06-22 00:13:38,986 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-06-22 00:13:38,986 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-06-22 00:13:38,988 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:38,988 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:38,989 INFO L794 eck$LassoCheckResult]: Stem: 240503#ULTIMATE.startENTRY [4266] ULTIMATE.startENTRY-->L444: Formula: (and (= 1 v_~t6_i~0_7) (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~M_E~0_37 2) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 0 v_~t6_pc~0_26) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_6~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= v_~T6_E~0_18 2) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~t6_st~0_24) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t6_pc~0=v_~t6_pc~0_26, ~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~T6_E~0=v_~T6_E~0_18, ~M_E~0=v_~M_E~0_37, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ~T4_E~0=v_~T4_E~0_18, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_4|, ~t6_i~0=v_~t6_i~0_7, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ULTIMATE.start_main_~__retres1~8=v_ULTIMATE.start_main_~__retres1~8_6, ~T2_E~0=v_~T2_E~0_18, ~t6_st~0=v_~t6_st~0_24, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_6~0=v_~E_6~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t6_pc~0, ~t5_i~0, ~t1_pc~0, ~t5_st~0, ~T6_E~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ~T4_E~0, ULTIMATE.start_start_simulation_#t~ret17, ~t6_i~0, ~t2_st~0, ~t2_pc~0, ULTIMATE.start_main_~__retres1~8, ~T2_E~0, ~t6_st~0, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_6~0, ULTIMATE.start_main_#res, ~E_2~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 240104#L444 [2453] L444-->L451-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 240105#L451-1 [3030] L451-1-->L456-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 240190#L456-1 [2574] L456-1-->L461-1: Formula: (and (= v_~t2_st~0_2 0) (= 1 v_~t2_i~0_3)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_2} AuxVars[] AssignedVars[~t2_st~0] 240191#L461-1 [2880] L461-1-->L466-1: Formula: (and (= v_~t3_st~0_3 0) (= v_~t3_i~0_3 1)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_3, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 240106#L466-1 [2457] L466-1-->L471-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 240107#L471-1 [3209] L471-1-->L476-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 240346#L476-1 [2761] L476-1-->L481-1: Formula: (and (= 1 v_~t6_i~0_3) (= v_~t6_st~0_4 0)) InVars {~t6_i~0=v_~t6_i~0_3} OutVars{~t6_st~0=v_~t6_st~0_4, ~t6_i~0=v_~t6_i~0_3} AuxVars[] AssignedVars[~t6_st~0] 240347#L481-1 [3652] L481-1-->L660-1: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 240521#L660-1 [3654] L660-1-->L665-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 240021#L665-1 [3655] L665-1-->L670-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 240022#L670-1 [3658] L670-1-->L675-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 240113#L675-1 [3659] L675-1-->L680-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 240114#L680-1 [3661] L680-1-->L685-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 240357#L685-1 [3663] L685-1-->L690-1: Formula: (< 0 v_~T6_E~0_4) InVars {~T6_E~0=v_~T6_E~0_4} OutVars{~T6_E~0=v_~T6_E~0_4} AuxVars[] AssignedVars[] 240358#L690-1 [3665] L690-1-->L695-1: Formula: (> v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 240232#L695-1 [3668] L695-1-->L700-1: Formula: (> v_~E_2~0_6 0) InVars {~E_2~0=v_~E_2~0_6} OutVars{~E_2~0=v_~E_2~0_6} AuxVars[] AssignedVars[] 240233#L700-1 [3670] L700-1-->L705-1: Formula: (> v_~E_3~0_6 0) InVars {~E_3~0=v_~E_3~0_6} OutVars{~E_3~0=v_~E_3~0_6} AuxVars[] AssignedVars[] 240487#L705-1 [3672] L705-1-->L710-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 240172#L710-1 [3674] L710-1-->L715-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 240173#L715-1 [3675] L715-1-->L720-1: Formula: (> v_~E_6~0_4 0) InVars {~E_6~0=v_~E_6~0_4} OutVars{~E_6~0=v_~E_6~0_4} AuxVars[] AssignedVars[] 240056#L720-1 [2412] L720-1-->L310: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_7, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_4|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_4|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_7, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_4, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_4, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_2|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_2|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_4|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_4|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_7, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_2|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_4} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 240057#L310 [3678] L310-->L310-2: Formula: (< v_~m_pc~0_5 1) InVars {~m_pc~0=v_~m_pc~0_5} OutVars{~m_pc~0=v_~m_pc~0_5} AuxVars[] AssignedVars[] 240205#L310-2 [2805] L310-2-->L321: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_11 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 240203#L321 [4267] L321-->L815: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 240204#L815 [2976] L815-->L815-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_12) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} AuxVars[] AssignedVars[] 240483#L815-2 [2961] L815-2-->L329: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 240409#L329 [3683] L329-->L329-2: Formula: (< v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 240410#L329-2 [2861] L329-2-->L340: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 240407#L340 [4268] L340-->L823: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 240408#L823 [3234] L823-->L823-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} AuxVars[] AssignedVars[] 240606#L823-2 [3235] L823-2-->L348: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_4|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 240577#L348 [3690] L348-->L348-2: Formula: (< v_~t2_pc~0_5 1) InVars {~t2_pc~0=v_~t2_pc~0_5} OutVars{~t2_pc~0=v_~t2_pc~0_5} AuxVars[] AssignedVars[] 240579#L348-2 [3153] L348-2-->L359: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 240576#L359 [4269] L359-->L831: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 240179#L831 [2537] L831-->L831-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} AuxVars[] AssignedVars[] 240167#L831-2 [2520] L831-2-->L367: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_4|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 240109#L367 [3695] L367-->L367-2: Formula: (> 1 v_~t3_pc~0_5) InVars {~t3_pc~0=v_~t3_pc~0_5} OutVars{~t3_pc~0=v_~t3_pc~0_5} AuxVars[] AssignedVars[] 240085#L367-2 [2438] L367-2-->L378: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 240086#L378 [4270] L378-->L839: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 240108#L839 [2791] L839-->L839-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} AuxVars[] AssignedVars[] 240371#L839-2 [2794] L839-2-->L386: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_7, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 240286#L386 [3702] L386-->L386-2: Formula: (< v_~t4_pc~0_5 1) InVars {~t4_pc~0=v_~t4_pc~0_5} OutVars{~t4_pc~0=v_~t4_pc~0_5} AuxVars[] AssignedVars[] 240287#L386-2 [2680] L386-2-->L397: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 240284#L397 [4271] L397-->L847: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 240285#L847 [3084] L847-->L847-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} AuxVars[] AssignedVars[] 240529#L847-2 [3064] L847-2-->L405: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_4|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 240530#L405 [3708] L405-->L405-2: Formula: (> 1 v_~t5_pc~0_5) InVars {~t5_pc~0=v_~t5_pc~0_5} OutVars{~t5_pc~0=v_~t5_pc~0_5} AuxVars[] AssignedVars[] 240439#L405-2 [2940] L405-2-->L416: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 240472#L416 [4272] L416-->L855: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 240540#L855 [3091] L855-->L855-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_12} AuxVars[] AssignedVars[] 240541#L855-2 [3093] L855-2-->L424: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_4|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 240152#L424 [3713] L424-->L424-2: Formula: (< v_~t6_pc~0_5 1) InVars {~t6_pc~0=v_~t6_pc~0_5} OutVars{~t6_pc~0=v_~t6_pc~0_5} AuxVars[] AssignedVars[] 240153#L424-2 [2503] L424-2-->L435: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 240151#L435 [4273] L435-->L863: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___5~0_49 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_28|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_28|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 240072#L863 [2425] L863-->L863-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___5~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} AuxVars[] AssignedVars[] 240045#L863-2 [3719] L863-2-->L733-1: Formula: (> v_~M_E~0_15 1) InVars {~M_E~0=v_~M_E~0_15} OutVars{~M_E~0=v_~M_E~0_15} AuxVars[] AssignedVars[] 240046#L733-1 [3722] L733-1-->L738-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 240485#L738-1 [3723] L738-1-->L743-1: Formula: (< 1 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 240170#L743-1 [3726] L743-1-->L748-1: Formula: (< 1 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 240171#L748-1 [3728] L748-1-->L753-1: Formula: (> v_~T4_E~0_10 1) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 240051#L753-1 [3729] L753-1-->L758-1: Formula: (< 1 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 240052#L758-1 [3731] L758-1-->L763-1: Formula: (> v_~T6_E~0_10 1) InVars {~T6_E~0=v_~T6_E~0_10} OutVars{~T6_E~0=v_~T6_E~0_10} AuxVars[] AssignedVars[] 240125#L763-1 [3733] L763-1-->L768-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 240126#L768-1 [3736] L768-1-->L773-1: Formula: (< 1 v_~E_2~0_14) InVars {~E_2~0=v_~E_2~0_14} OutVars{~E_2~0=v_~E_2~0_14} AuxVars[] AssignedVars[] 240352#L773-1 [3737] L773-1-->L778-1: Formula: (< 1 v_~E_3~0_14) InVars {~E_3~0=v_~E_3~0_14} OutVars{~E_3~0=v_~E_3~0_14} AuxVars[] AssignedVars[] 240353#L778-1 [3740] L778-1-->L783-1: Formula: (< 1 v_~E_4~0_14) InVars {~E_4~0=v_~E_4~0_14} OutVars{~E_4~0=v_~E_4~0_14} AuxVars[] AssignedVars[] 240226#L783-1 [3741] L783-1-->L788-1: Formula: (< 1 v_~E_5~0_14) InVars {~E_5~0=v_~E_5~0_14} OutVars{~E_5~0=v_~E_5~0_14} AuxVars[] AssignedVars[] 240227#L788-1 [3744] L788-1-->L1014-1: Formula: (< 1 v_~E_6~0_14) InVars {~E_6~0=v_~E_6~0_14} OutVars{~E_6~0=v_~E_6~0_14} AuxVars[] AssignedVars[] 240589#L1014-1 [2020-06-22 00:13:38,990 INFO L796 eck$LassoCheckResult]: Loop: 240589#L1014-1 [4274] L1014-1-->L635: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp_ndt_7~0=v_ULTIMATE.start_eval_~tmp_ndt_7~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp_ndt_7~0] 242683#L635 [4275] L635-->L494: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_37} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 242681#L494 [3746] L494-->L498: Formula: (> v_~m_st~0_9 0) InVars {~m_st~0=v_~m_st~0_9} OutVars{~m_st~0=v_~m_st~0_9} AuxVars[] AssignedVars[] 242674#L498 [3749] L498-->L502: Formula: (< v_~t1_st~0_9 0) InVars {~t1_st~0=v_~t1_st~0_9} OutVars{~t1_st~0=v_~t1_st~0_9} AuxVars[] AssignedVars[] 242675#L502 [3753] L502-->L506: Formula: (> v_~t2_st~0_9 0) InVars {~t2_st~0=v_~t2_st~0_9} OutVars{~t2_st~0=v_~t2_st~0_9} AuxVars[] AssignedVars[] 242676#L506 [3760] L506-->L510: Formula: (< 0 v_~t3_st~0_10) InVars {~t3_st~0=v_~t3_st~0_10} OutVars{~t3_st~0=v_~t3_st~0_10} AuxVars[] AssignedVars[] 242677#L510 [3765] L510-->L514: Formula: (> 0 v_~t4_st~0_11) InVars {~t4_st~0=v_~t4_st~0_11} OutVars{~t4_st~0=v_~t4_st~0_11} AuxVars[] AssignedVars[] 242680#L514 [3773] L514-->L518: Formula: (> v_~t5_st~0_11 0) InVars {~t5_st~0=v_~t5_st~0_11} OutVars{~t5_st~0=v_~t5_st~0_11} AuxVars[] AssignedVars[] 242678#L518 [3783] L518-->L531: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_28 0) (< 0 v_~t6_st~0_11)) InVars {~t6_st~0=v_~t6_st~0_11} OutVars{~t6_st~0=v_~t6_st~0_11, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_28} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 242679#L531 [4276] L531-->L546: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 252145#L546 [4278] L546-->L660-2: Formula: (and (= v_ULTIMATE.start_start_simulation_~kernel_st~0_13 3) (= v_ULTIMATE.start_eval_~tmp~0_9 0)) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} OutVars{ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_13, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_9} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~kernel_st~0] 251928#L660-2 [3747] L660-2-->L660-4: Formula: (> v_~M_E~0_30 0) InVars {~M_E~0=v_~M_E~0_30} OutVars{~M_E~0=v_~M_E~0_30} AuxVars[] AssignedVars[] 251772#L660-4 [3058] L660-4-->L665-3: Formula: (and (= v_~T1_E~0_11 1) (= v_~T1_E~0_12 0)) InVars {~T1_E~0=v_~T1_E~0_12} OutVars{~T1_E~0=v_~T1_E~0_11} AuxVars[] AssignedVars[~T1_E~0] 251771#L665-3 [3756] L665-3-->L670-3: Formula: (< 0 v_~T2_E~0_13) InVars {~T2_E~0=v_~T2_E~0_13} OutVars{~T2_E~0=v_~T2_E~0_13} AuxVars[] AssignedVars[] 251770#L670-3 [3762] L670-3-->L675-3: Formula: (< 0 v_~T3_E~0_13) InVars {~T3_E~0=v_~T3_E~0_13} OutVars{~T3_E~0=v_~T3_E~0_13} AuxVars[] AssignedVars[] 250492#L675-3 [3768] L675-3-->L680-3: Formula: (> v_~T4_E~0_13 0) InVars {~T4_E~0=v_~T4_E~0_13} OutVars{~T4_E~0=v_~T4_E~0_13} AuxVars[] AssignedVars[] 250491#L680-3 [3776] L680-3-->L685-3: Formula: (< 0 v_~T5_E~0_13) InVars {~T5_E~0=v_~T5_E~0_13} OutVars{~T5_E~0=v_~T5_E~0_13} AuxVars[] AssignedVars[] 250489#L685-3 [3785] L685-3-->L690-3: Formula: (> v_~T6_E~0_13 0) InVars {~T6_E~0=v_~T6_E~0_13} OutVars{~T6_E~0=v_~T6_E~0_13} AuxVars[] AssignedVars[] 250487#L690-3 [3795] L690-3-->L695-3: Formula: (< 0 v_~E_1~0_31) InVars {~E_1~0=v_~E_1~0_31} OutVars{~E_1~0=v_~E_1~0_31} AuxVars[] AssignedVars[] 250486#L695-3 [3805] L695-3-->L700-3: Formula: (< 0 v_~E_2~0_31) InVars {~E_2~0=v_~E_2~0_31} OutVars{~E_2~0=v_~E_2~0_31} AuxVars[] AssignedVars[] 250483#L700-3 [3818] L700-3-->L705-3: Formula: (< 0 v_~E_3~0_31) InVars {~E_3~0=v_~E_3~0_31} OutVars{~E_3~0=v_~E_3~0_31} AuxVars[] AssignedVars[] 250243#L705-3 [2688] L705-3-->L710-3: Formula: (and (= v_~E_4~0_29 1) (= 0 v_~E_4~0_30)) InVars {~E_4~0=v_~E_4~0_30} OutVars{~E_4~0=v_~E_4~0_29} AuxVars[] AssignedVars[~E_4~0] 250166#L710-3 [3844] L710-3-->L715-3: Formula: (< 0 v_~E_5~0_31) InVars {~E_5~0=v_~E_5~0_31} OutVars{~E_5~0=v_~E_5~0_31} AuxVars[] AssignedVars[] 250165#L715-3 [3854] L715-3-->L720-3: Formula: (< 0 v_~E_6~0_31) InVars {~E_6~0=v_~E_6~0_31} OutVars{~E_6~0=v_~E_6~0_31} AuxVars[] AssignedVars[] 250108#L720-3 [2388] L720-3-->L310-21: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_43, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_43, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_25|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_25|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_25|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_43, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_43, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_43, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_25|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_25|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_25|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_25|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_43, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_25|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_43, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_43} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 249887#L310-21 [3870] L310-21-->L310-23: Formula: (< v_~m_pc~0_24 1) InVars {~m_pc~0=v_~m_pc~0_24} OutVars{~m_pc~0=v_~m_pc~0_24} AuxVars[] AssignedVars[] 249885#L310-23 [2785] L310-23-->L321-7: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_47 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_47} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 249874#L321-7 [4303] L321-7-->L815-21: Formula: (and (= |v_ULTIMATE.start_is_master_triggered_#res_41| v_ULTIMATE.start_activate_threads_~tmp~1_62) (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_62 |v_ULTIMATE.start_is_master_triggered_#res_41|)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_62, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_41|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_62, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_41|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 249869#L815-21 [2667] L815-21-->L815-23: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_48) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_48} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_48} AuxVars[] AssignedVars[] 249868#L815-23 [2638] L815-23-->L329-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 249866#L329-21 [3911] L329-21-->L329-23: Formula: (< v_~t1_pc~0_24 1) InVars {~t1_pc~0=v_~t1_pc~0_24} OutVars{~t1_pc~0=v_~t1_pc~0_24} AuxVars[] AssignedVars[] 249413#L329-23 [3052] L329-23-->L340-7: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 249717#L340-7 [4310] L340-7-->L823-21: Formula: (and (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___0~0_62 |v_ULTIMATE.start_is_transmit1_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_62, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_41|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_62, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 249716#L823-21 [2931] L823-21-->L823-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_48} AuxVars[] AssignedVars[] 249714#L823-23 [2934] L823-23-->L348-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_25|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 249710#L348-21 [3953] L348-21-->L348-23: Formula: (> 1 v_~t2_pc~0_24) InVars {~t2_pc~0=v_~t2_pc~0_24} OutVars{~t2_pc~0=v_~t2_pc~0_24} AuxVars[] AssignedVars[] 249708#L348-23 [3319] L348-23-->L359-7: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 249707#L359-7 [4317] L359-7-->L831-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62 |v_ULTIMATE.start_is_transmit2_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_41|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_62, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_35|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 249706#L831-21 [2490] L831-21-->L831-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_48} AuxVars[] AssignedVars[] 249705#L831-23 [3197] L831-23-->L367-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_25|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 249704#L367-21 [3995] L367-21-->L367-23: Formula: (> v_~t3_pc~0_24 1) InVars {~t3_pc~0=v_~t3_pc~0_24} OutVars{~t3_pc~0=v_~t3_pc~0_24} AuxVars[] AssignedVars[] 249701#L367-23 [2385] L367-23-->L378-7: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 249699#L378-7 [4324] L378-7-->L839-21: Formula: (and (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___2~0_62 |v_ULTIMATE.start_is_transmit3_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_41|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_35|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_62, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_62} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 249697#L839-21 [2715] L839-21-->L839-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_48} AuxVars[] AssignedVars[] 249695#L839-23 [2722] L839-23-->L386-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_49, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_25|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 243914#L386-21 [4038] L386-21-->L386-23: Formula: (> 1 v_~t4_pc~0_24) InVars {~t4_pc~0=v_~t4_pc~0_24} OutVars{~t4_pc~0=v_~t4_pc~0_24} AuxVars[] AssignedVars[] 243912#L386-23 [2623] L386-23-->L397-7: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 243910#L397-7 [4331] L397-7-->L847-21: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___3~0_62 |v_ULTIMATE.start_is_transmit4_triggered_#res_35|) (= |v_ULTIMATE.start_is_transmit4_triggered_#res_35| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_62, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_62, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_41|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_35|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 243908#L847-21 [3021] L847-21-->L847-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_48} AuxVars[] AssignedVars[] 243906#L847-23 [2983] L847-23-->L405-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_25|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 243903#L405-21 [4080] L405-21-->L405-23: Formula: (> v_~t5_pc~0_24 1) InVars {~t5_pc~0=v_~t5_pc~0_24} OutVars{~t5_pc~0=v_~t5_pc~0_24} AuxVars[] AssignedVars[] 243901#L405-23 [2891] L405-23-->L416-7: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 243899#L416-7 [4338] L416-7-->L855-21: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_activate_threads_~tmp___4~0_62) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_35| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_35|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_41|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_62, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 243897#L855-21 [3251] L855-21-->L855-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_48} AuxVars[] AssignedVars[] 243896#L855-23 [3257] L855-23-->L424-21: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_25|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 243198#L424-21 [4122] L424-21-->L424-23: Formula: (> 1 v_~t6_pc~0_24) InVars {~t6_pc~0=v_~t6_pc~0_24} OutVars{~t6_pc~0=v_~t6_pc~0_24} AuxVars[] AssignedVars[] 243196#L424-23 [3177] L424-23-->L435-7: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_53 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_53} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 243194#L435-7 [4340] L435-7-->L863-21: Formula: (and (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|) (= v_ULTIMATE.start_activate_threads_~tmp___5~0_62 |v_ULTIMATE.start_is_transmit6_triggered_#res_35|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_35|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_62, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_41|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_62} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 243192#L863-21 [2570] L863-21-->L863-23: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___5~0_48 0) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_48} OutVars{ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_48} AuxVars[] AssignedVars[] 243190#L863-23 [4138] L863-23-->L733-3: Formula: (> v_~M_E~0_35 1) InVars {~M_E~0=v_~M_E~0_35} OutVars{~M_E~0=v_~M_E~0_35} AuxVars[] AssignedVars[] 243188#L733-3 [3184] L733-3-->L738-3: Formula: (and (= v_~T1_E~0_15 1) (= v_~T1_E~0_14 2)) InVars {~T1_E~0=v_~T1_E~0_15} OutVars{~T1_E~0=v_~T1_E~0_14} AuxVars[] AssignedVars[~T1_E~0] 243186#L738-3 [4142] L738-3-->L743-3: Formula: (< 1 v_~T2_E~0_16) InVars {~T2_E~0=v_~T2_E~0_16} OutVars{~T2_E~0=v_~T2_E~0_16} AuxVars[] AssignedVars[] 243184#L743-3 [4143] L743-3-->L748-3: Formula: (< 1 v_~T3_E~0_16) InVars {~T3_E~0=v_~T3_E~0_16} OutVars{~T3_E~0=v_~T3_E~0_16} AuxVars[] AssignedVars[] 243182#L748-3 [4145] L748-3-->L753-3: Formula: (> v_~T4_E~0_16 1) InVars {~T4_E~0=v_~T4_E~0_16} OutVars{~T4_E~0=v_~T4_E~0_16} AuxVars[] AssignedVars[] 243180#L753-3 [4148] L753-3-->L758-3: Formula: (< 1 v_~T5_E~0_16) InVars {~T5_E~0=v_~T5_E~0_16} OutVars{~T5_E~0=v_~T5_E~0_16} AuxVars[] AssignedVars[] 243178#L758-3 [4149] L758-3-->L763-3: Formula: (> v_~T6_E~0_16 1) InVars {~T6_E~0=v_~T6_E~0_16} OutVars{~T6_E~0=v_~T6_E~0_16} AuxVars[] AssignedVars[] 243177#L763-3 [4151] L763-3-->L768-3: Formula: (< 1 v_~E_1~0_36) InVars {~E_1~0=v_~E_1~0_36} OutVars{~E_1~0=v_~E_1~0_36} AuxVars[] AssignedVars[] 243176#L768-3 [4154] L768-3-->L773-3: Formula: (< 1 v_~E_2~0_36) InVars {~E_2~0=v_~E_2~0_36} OutVars{~E_2~0=v_~E_2~0_36} AuxVars[] AssignedVars[] 243175#L773-3 [4156] L773-3-->L778-3: Formula: (< 1 v_~E_3~0_36) InVars {~E_3~0=v_~E_3~0_36} OutVars{~E_3~0=v_~E_3~0_36} AuxVars[] AssignedVars[] 243174#L778-3 [3308] L778-3-->L783-3: Formula: (and (= 1 v_~E_4~0_35) (= v_~E_4~0_34 2)) InVars {~E_4~0=v_~E_4~0_35} OutVars{~E_4~0=v_~E_4~0_34} AuxVars[] AssignedVars[~E_4~0] 243173#L783-3 [4160] L783-3-->L788-3: Formula: (< 1 v_~E_5~0_36) InVars {~E_5~0=v_~E_5~0_36} OutVars{~E_5~0=v_~E_5~0_36} AuxVars[] AssignedVars[] 243172#L788-3 [4162] L788-3-->L793-3: Formula: (< 1 v_~E_6~0_36) InVars {~E_6~0=v_~E_6~0_36} OutVars{~E_6~0=v_~E_6~0_36} AuxVars[] AssignedVars[] 243171#L793-3 [2966] L793-3-->L494-1: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_9|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_30} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 243168#L494-1 [2878] L494-1-->L531-1: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33 1) (= 0 v_~m_st~0_21)) InVars {~m_st~0=v_~m_st~0_21} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_33, ~m_st~0=v_~m_st~0_21} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 243160#L531-1 [4341] L531-1-->L1033: Formula: (and (= v_ULTIMATE.start_start_simulation_~tmp~3_8 |v_ULTIMATE.start_exists_runnable_thread_#res_12|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39 |v_ULTIMATE.start_exists_runnable_thread_#res_12|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_12|, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_39, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_start_simulation_#t~ret16, ULTIMATE.start_start_simulation_~tmp~3] 243157#L1033 [4169] L1033-->L1033-1: Formula: (> 0 v_ULTIMATE.start_start_simulation_~tmp~3_6) InVars {ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} OutVars{ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_6} AuxVars[] AssignedVars[] 243154#L1033-1 [2919] L1033-1-->L494-2: Formula: true InVars {} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_1|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_3|, ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_1, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_1, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_6, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_1|} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~__retres2~0, ULTIMATE.start_stop_simulation_~tmp~2, ULTIMATE.start_exists_runnable_thread_~__retres1~7, ULTIMATE.start_stop_simulation_#res] 242695#L494-2 [2882] L494-2-->L531-2: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9 1) (= v_~m_st~0_6 0)) InVars {~m_st~0=v_~m_st~0_6} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_9, ~m_st~0=v_~m_st~0_6} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 242691#L531-2 [4343] L531-2-->L988: Formula: (and (= v_ULTIMATE.start_stop_simulation_~tmp~2_7 |v_ULTIMATE.start_exists_runnable_thread_#res_13|) (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40 |v_ULTIMATE.start_exists_runnable_thread_#res_13|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} OutVars{ULTIMATE.start_stop_simulation_#t~ret15=|v_ULTIMATE.start_stop_simulation_#t~ret15_4|, ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_13|, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_7, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_40} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_#t~ret15, ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_stop_simulation_~tmp~2] 242690#L988 [3240] L988-->L995: Formula: (and (= 0 v_ULTIMATE.start_stop_simulation_~tmp~2_6) (= v_ULTIMATE.start_stop_simulation_~__retres2~0_5 1)) InVars {ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_5, ULTIMATE.start_stop_simulation_~tmp~2=v_ULTIMATE.start_stop_simulation_~tmp~2_6} AuxVars[] AssignedVars[ULTIMATE.start_stop_simulation_~__retres2~0] 242689#L995 [4354] L995-->L1014-1: Formula: (and (= v_ULTIMATE.start_stop_simulation_~__retres2~0_8 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 |v_ULTIMATE.start_stop_simulation_#res_5|) (= v_ULTIMATE.start_start_simulation_~tmp___0~1_9 0)) InVars {ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8} OutVars{ULTIMATE.start_stop_simulation_~__retres2~0=v_ULTIMATE.start_stop_simulation_~__retres2~0_8, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_9, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_6|, ULTIMATE.start_stop_simulation_#res=|v_ULTIMATE.start_stop_simulation_#res_5|} AuxVars[] AssignedVars[ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_#t~ret17, ULTIMATE.start_stop_simulation_#res] 240589#L1014-1 [2020-06-22 00:13:38,990 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:38,990 INFO L82 PathProgramCache]: Analyzing trace with hash -1932600016, now seen corresponding path program 9 times [2020-06-22 00:13:38,990 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:38,990 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:38,991 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:38,991 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:38,991 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:38,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:13:38,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:13:39,007 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:39,008 INFO L82 PathProgramCache]: Analyzing trace with hash -15442813, now seen corresponding path program 1 times [2020-06-22 00:13:39,008 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:39,008 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:39,008 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:39,009 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2020-06-22 00:13:39,009 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:39,013 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:39,032 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:39,033 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:39,033 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-06-22 00:13:39,033 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-06-22 00:13:39,034 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-06-22 00:13:39,034 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-06-22 00:13:39,034 INFO L87 Difference]: Start difference. First operand 12468 states and 18808 transitions. cyclomatic complexity: 6342 Second operand 3 states. [2020-06-22 00:13:39,685 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-06-22 00:13:39,685 INFO L93 Difference]: Finished difference Result 16161 states and 24245 transitions. [2020-06-22 00:13:39,686 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-06-22 00:13:39,686 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 16161 states and 24245 transitions. [2020-06-22 00:13:39,747 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 16088 [2020-06-22 00:13:39,785 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 16161 states to 16161 states and 24245 transitions. [2020-06-22 00:13:39,785 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16161 [2020-06-22 00:13:39,795 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16161 [2020-06-22 00:13:39,795 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16161 states and 24245 transitions. [2020-06-22 00:13:39,806 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-06-22 00:13:39,806 INFO L706 BuchiCegarLoop]: Abstraction has 16161 states and 24245 transitions. [2020-06-22 00:13:39,812 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16161 states and 24245 transitions. [2020-06-22 00:13:39,923 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16161 to 16161. [2020-06-22 00:13:39,923 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16161 states. [2020-06-22 00:13:39,952 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16161 states to 16161 states and 24245 transitions. [2020-06-22 00:13:39,952 INFO L729 BuchiCegarLoop]: Abstraction has 16161 states and 24245 transitions. [2020-06-22 00:13:39,952 INFO L609 BuchiCegarLoop]: Abstraction has 16161 states and 24245 transitions. [2020-06-22 00:13:39,952 INFO L442 BuchiCegarLoop]: ======== Iteration 41============ [2020-06-22 00:13:39,953 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16161 states and 24245 transitions. [2020-06-22 00:13:40,000 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 16088 [2020-06-22 00:13:40,001 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-06-22 00:13:40,001 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-06-22 00:13:40,002 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:40,002 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:40,003 INFO L794 eck$LassoCheckResult]: Stem: 269140#ULTIMATE.startENTRY [4266] ULTIMATE.startENTRY-->L444: Formula: (and (= 1 v_~t6_i~0_7) (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~M_E~0_37 2) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 0 v_~t6_pc~0_26) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_6~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= v_~T6_E~0_18 2) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~t6_st~0_24) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t6_pc~0=v_~t6_pc~0_26, ~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~T6_E~0=v_~T6_E~0_18, ~M_E~0=v_~M_E~0_37, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ~T4_E~0=v_~T4_E~0_18, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_4|, ~t6_i~0=v_~t6_i~0_7, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ULTIMATE.start_main_~__retres1~8=v_ULTIMATE.start_main_~__retres1~8_6, ~T2_E~0=v_~T2_E~0_18, ~t6_st~0=v_~t6_st~0_24, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_6~0=v_~E_6~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t6_pc~0, ~t5_i~0, ~t1_pc~0, ~t5_st~0, ~T6_E~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ~T4_E~0, ULTIMATE.start_start_simulation_#t~ret17, ~t6_i~0, ~t2_st~0, ~t2_pc~0, ULTIMATE.start_main_~__retres1~8, ~T2_E~0, ~t6_st~0, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_6~0, ULTIMATE.start_main_#res, ~E_2~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 268738#L444 [2453] L444-->L451-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 268739#L451-1 [3030] L451-1-->L456-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 268822#L456-1 [2574] L456-1-->L461-1: Formula: (and (= v_~t2_st~0_2 0) (= 1 v_~t2_i~0_3)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_2} AuxVars[] AssignedVars[~t2_st~0] 268823#L461-1 [2880] L461-1-->L466-1: Formula: (and (= v_~t3_st~0_3 0) (= v_~t3_i~0_3 1)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_3, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 268740#L466-1 [2457] L466-1-->L471-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 268741#L471-1 [3209] L471-1-->L476-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 268977#L476-1 [2761] L476-1-->L481-1: Formula: (and (= 1 v_~t6_i~0_3) (= v_~t6_st~0_4 0)) InVars {~t6_i~0=v_~t6_i~0_3} OutVars{~t6_st~0=v_~t6_st~0_4, ~t6_i~0=v_~t6_i~0_3} AuxVars[] AssignedVars[~t6_st~0] 268978#L481-1 [3652] L481-1-->L660-1: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 269156#L660-1 [3654] L660-1-->L665-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 268656#L665-1 [3655] L665-1-->L670-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 268657#L670-1 [3658] L670-1-->L675-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 268747#L675-1 [3659] L675-1-->L680-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 268748#L680-1 [3661] L680-1-->L685-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 268990#L685-1 [3663] L685-1-->L690-1: Formula: (< 0 v_~T6_E~0_4) InVars {~T6_E~0=v_~T6_E~0_4} OutVars{~T6_E~0=v_~T6_E~0_4} AuxVars[] AssignedVars[] 268991#L690-1 [3665] L690-1-->L695-1: Formula: (> v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 268863#L695-1 [3668] L695-1-->L700-1: Formula: (> v_~E_2~0_6 0) InVars {~E_2~0=v_~E_2~0_6} OutVars{~E_2~0=v_~E_2~0_6} AuxVars[] AssignedVars[] 268864#L700-1 [3670] L700-1-->L705-1: Formula: (> v_~E_3~0_6 0) InVars {~E_3~0=v_~E_3~0_6} OutVars{~E_3~0=v_~E_3~0_6} AuxVars[] AssignedVars[] 269124#L705-1 [3672] L705-1-->L710-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 268805#L710-1 [3674] L710-1-->L715-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 268806#L715-1 [3675] L715-1-->L720-1: Formula: (> v_~E_6~0_4 0) InVars {~E_6~0=v_~E_6~0_4} OutVars{~E_6~0=v_~E_6~0_4} AuxVars[] AssignedVars[] 268690#L720-1 [2412] L720-1-->L310: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_7, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_4|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_4|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_7, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_4, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_4, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_2|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_2|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_4|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_4|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_7, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_2|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_4} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 268691#L310 [3678] L310-->L310-2: Formula: (< v_~m_pc~0_5 1) InVars {~m_pc~0=v_~m_pc~0_5} OutVars{~m_pc~0=v_~m_pc~0_5} AuxVars[] AssignedVars[] 268836#L310-2 [2805] L310-2-->L321: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_11 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 268834#L321 [4267] L321-->L815: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 268835#L815 [2976] L815-->L815-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_12) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} AuxVars[] AssignedVars[] 269119#L815-2 [2961] L815-2-->L329: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 269043#L329 [3683] L329-->L329-2: Formula: (< v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 269044#L329-2 [2861] L329-2-->L340: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 269041#L340 [4268] L340-->L823: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 269042#L823 [3234] L823-->L823-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} AuxVars[] AssignedVars[] 269242#L823-2 [3235] L823-2-->L348: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_4|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 269213#L348 [3690] L348-->L348-2: Formula: (< v_~t2_pc~0_5 1) InVars {~t2_pc~0=v_~t2_pc~0_5} OutVars{~t2_pc~0=v_~t2_pc~0_5} AuxVars[] AssignedVars[] 269215#L348-2 [3153] L348-2-->L359: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 269212#L359 [4269] L359-->L831: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 268812#L831 [2537] L831-->L831-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} AuxVars[] AssignedVars[] 268800#L831-2 [2520] L831-2-->L367: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_4|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 268743#L367 [3695] L367-->L367-2: Formula: (> 1 v_~t3_pc~0_5) InVars {~t3_pc~0=v_~t3_pc~0_5} OutVars{~t3_pc~0=v_~t3_pc~0_5} AuxVars[] AssignedVars[] 268719#L367-2 [2438] L367-2-->L378: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 268720#L378 [4270] L378-->L839: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 268742#L839 [2791] L839-->L839-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} AuxVars[] AssignedVars[] 269003#L839-2 [2794] L839-2-->L386: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_7, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 268914#L386 [3702] L386-->L386-2: Formula: (< v_~t4_pc~0_5 1) InVars {~t4_pc~0=v_~t4_pc~0_5} OutVars{~t4_pc~0=v_~t4_pc~0_5} AuxVars[] AssignedVars[] 268915#L386-2 [2680] L386-2-->L397: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 268912#L397 [4271] L397-->L847: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 268913#L847 [3084] L847-->L847-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} AuxVars[] AssignedVars[] 269164#L847-2 [3064] L847-2-->L405: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_4|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 269165#L405 [3708] L405-->L405-2: Formula: (> 1 v_~t5_pc~0_5) InVars {~t5_pc~0=v_~t5_pc~0_5} OutVars{~t5_pc~0=v_~t5_pc~0_5} AuxVars[] AssignedVars[] 269073#L405-2 [2940] L405-2-->L416: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 269106#L416 [4272] L416-->L855: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 269175#L855 [3091] L855-->L855-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_12} AuxVars[] AssignedVars[] 269176#L855-2 [3093] L855-2-->L424: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_4|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 268786#L424 [3713] L424-->L424-2: Formula: (< v_~t6_pc~0_5 1) InVars {~t6_pc~0=v_~t6_pc~0_5} OutVars{~t6_pc~0=v_~t6_pc~0_5} AuxVars[] AssignedVars[] 268787#L424-2 [2503] L424-2-->L435: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 268785#L435 [4273] L435-->L863: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___5~0_49 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_28|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_28|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 268706#L863 [2425] L863-->L863-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___5~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} AuxVars[] AssignedVars[] 268680#L863-2 [3719] L863-2-->L733-1: Formula: (> v_~M_E~0_15 1) InVars {~M_E~0=v_~M_E~0_15} OutVars{~M_E~0=v_~M_E~0_15} AuxVars[] AssignedVars[] 268681#L733-1 [3722] L733-1-->L738-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 269122#L738-1 [3723] L738-1-->L743-1: Formula: (< 1 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 268803#L743-1 [3726] L743-1-->L748-1: Formula: (< 1 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 268804#L748-1 [3728] L748-1-->L753-1: Formula: (> v_~T4_E~0_10 1) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 268685#L753-1 [3729] L753-1-->L758-1: Formula: (< 1 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 268686#L758-1 [3731] L758-1-->L763-1: Formula: (> v_~T6_E~0_10 1) InVars {~T6_E~0=v_~T6_E~0_10} OutVars{~T6_E~0=v_~T6_E~0_10} AuxVars[] AssignedVars[] 268759#L763-1 [3733] L763-1-->L768-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 268760#L768-1 [3736] L768-1-->L773-1: Formula: (< 1 v_~E_2~0_14) InVars {~E_2~0=v_~E_2~0_14} OutVars{~E_2~0=v_~E_2~0_14} AuxVars[] AssignedVars[] 268983#L773-1 [3737] L773-1-->L778-1: Formula: (< 1 v_~E_3~0_14) InVars {~E_3~0=v_~E_3~0_14} OutVars{~E_3~0=v_~E_3~0_14} AuxVars[] AssignedVars[] 268984#L778-1 [3740] L778-1-->L783-1: Formula: (< 1 v_~E_4~0_14) InVars {~E_4~0=v_~E_4~0_14} OutVars{~E_4~0=v_~E_4~0_14} AuxVars[] AssignedVars[] 268857#L783-1 [3741] L783-1-->L788-1: Formula: (< 1 v_~E_5~0_14) InVars {~E_5~0=v_~E_5~0_14} OutVars{~E_5~0=v_~E_5~0_14} AuxVars[] AssignedVars[] 268858#L788-1 [3744] L788-1-->L1014-1: Formula: (< 1 v_~E_6~0_14) InVars {~E_6~0=v_~E_6~0_14} OutVars{~E_6~0=v_~E_6~0_14} AuxVars[] AssignedVars[] 269227#L1014-1 [4274] L1014-1-->L635: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp_ndt_7~0=v_ULTIMATE.start_eval_~tmp_ndt_7~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp_ndt_7~0] 269953#L635 [2020-06-22 00:13:40,003 INFO L796 eck$LassoCheckResult]: Loop: 269953#L635 [4275] L635-->L494: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_37} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 269949#L494 [2876] L494-->L531: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21 1) (= v_~m_st~0_8 0)) InVars {~m_st~0=v_~m_st~0_8} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21, ~m_st~0=v_~m_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 269947#L531 [4276] L531-->L546: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 269945#L546 [3757] L546-->L546-1: Formula: (> v_ULTIMATE.start_eval_~tmp~0_4 0) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} OutVars{ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} AuxVars[] AssignedVars[] 269943#L546-1 [3164] L546-1-->L554: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_2 |v_ULTIMATE.start_eval_#t~nondet1_3|) (= 0 v_~m_st~0_10)) InVars {~m_st~0=v_~m_st~0_10, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_3|} OutVars{ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_2|, ~m_st~0=v_~m_st~0_10, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_1~0] 269942#L554 [2472] L554-->L551: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} AuxVars[] AssignedVars[] 269941#L551 [3771] L551-->L565: Formula: (> 0 v_~t1_st~0_15) InVars {~t1_st~0=v_~t1_st~0_15} OutVars{~t1_st~0=v_~t1_st~0_15} AuxVars[] AssignedVars[] 269936#L565 [3781] L565-->L579: Formula: (> v_~t2_st~0_16 0) InVars {~t2_st~0=v_~t2_st~0_16} OutVars{~t2_st~0=v_~t2_st~0_16} AuxVars[] AssignedVars[] 270006#L579 [3793] L579-->L593: Formula: (> 0 v_~t3_st~0_18) InVars {~t3_st~0=v_~t3_st~0_18} OutVars{~t3_st~0=v_~t3_st~0_18} AuxVars[] AssignedVars[] 269997#L593 [3803] L593-->L607: Formula: (> 0 v_~t4_st~0_20) InVars {~t4_st~0=v_~t4_st~0_20} OutVars{~t4_st~0=v_~t4_st~0_20} AuxVars[] AssignedVars[] 269982#L607 [3815] L607-->L621: Formula: (< v_~t5_st~0_21 0) InVars {~t5_st~0=v_~t5_st~0_21} OutVars{~t5_st~0=v_~t5_st~0_21} AuxVars[] AssignedVars[] 269955#L621 [3829] L621-->L635: Formula: (< 0 v_~t6_st~0_21) InVars {~t6_st~0=v_~t6_st~0_21} OutVars{~t6_st~0=v_~t6_st~0_21} AuxVars[] AssignedVars[] 269953#L635 [2020-06-22 00:13:40,003 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:40,003 INFO L82 PathProgramCache]: Analyzing trace with hash 218945922, now seen corresponding path program 1 times [2020-06-22 00:13:40,003 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:40,004 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:40,004 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:40,004 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:40,004 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:40,008 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:13:40,013 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:13:40,021 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:40,021 INFO L82 PathProgramCache]: Analyzing trace with hash 446364273, now seen corresponding path program 1 times [2020-06-22 00:13:40,021 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:40,022 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:40,022 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:40,022 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:40,022 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:40,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:13:40,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:13:40,028 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:40,028 INFO L82 PathProgramCache]: Analyzing trace with hash 909154930, now seen corresponding path program 1 times [2020-06-22 00:13:40,028 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:40,028 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:40,029 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:40,029 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:40,029 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:40,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:40,052 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:40,053 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:40,053 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-06-22 00:13:40,123 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-06-22 00:13:40,123 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-06-22 00:13:40,123 INFO L87 Difference]: Start difference. First operand 16161 states and 24245 transitions. cyclomatic complexity: 8087 Second operand 3 states. [2020-06-22 00:13:40,585 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-06-22 00:13:40,585 INFO L93 Difference]: Finished difference Result 16161 states and 24101 transitions. [2020-06-22 00:13:40,586 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-06-22 00:13:40,586 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 16161 states and 24101 transitions. [2020-06-22 00:13:40,765 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 16088 [2020-06-22 00:13:40,799 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 16161 states to 16161 states and 24101 transitions. [2020-06-22 00:13:40,799 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16161 [2020-06-22 00:13:40,809 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16161 [2020-06-22 00:13:40,810 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16161 states and 24101 transitions. [2020-06-22 00:13:40,820 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-06-22 00:13:40,820 INFO L706 BuchiCegarLoop]: Abstraction has 16161 states and 24101 transitions. [2020-06-22 00:13:40,827 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16161 states and 24101 transitions. [2020-06-22 00:13:40,944 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16161 to 16161. [2020-06-22 00:13:40,944 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16161 states. [2020-06-22 00:13:40,973 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16161 states to 16161 states and 24101 transitions. [2020-06-22 00:13:40,974 INFO L729 BuchiCegarLoop]: Abstraction has 16161 states and 24101 transitions. [2020-06-22 00:13:40,974 INFO L609 BuchiCegarLoop]: Abstraction has 16161 states and 24101 transitions. [2020-06-22 00:13:40,974 INFO L442 BuchiCegarLoop]: ======== Iteration 42============ [2020-06-22 00:13:40,974 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16161 states and 24101 transitions. [2020-06-22 00:13:41,022 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 16088 [2020-06-22 00:13:41,022 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-06-22 00:13:41,022 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-06-22 00:13:41,023 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:41,023 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:41,024 INFO L794 eck$LassoCheckResult]: Stem: 301484#ULTIMATE.startENTRY [4266] ULTIMATE.startENTRY-->L444: Formula: (and (= 1 v_~t6_i~0_7) (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~M_E~0_37 2) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 0 v_~t6_pc~0_26) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_6~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= v_~T6_E~0_18 2) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~t6_st~0_24) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t6_pc~0=v_~t6_pc~0_26, ~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~T6_E~0=v_~T6_E~0_18, ~M_E~0=v_~M_E~0_37, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ~T4_E~0=v_~T4_E~0_18, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_4|, ~t6_i~0=v_~t6_i~0_7, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ULTIMATE.start_main_~__retres1~8=v_ULTIMATE.start_main_~__retres1~8_6, ~T2_E~0=v_~T2_E~0_18, ~t6_st~0=v_~t6_st~0_24, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_6~0=v_~E_6~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t6_pc~0, ~t5_i~0, ~t1_pc~0, ~t5_st~0, ~T6_E~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ~T4_E~0, ULTIMATE.start_start_simulation_#t~ret17, ~t6_i~0, ~t2_st~0, ~t2_pc~0, ULTIMATE.start_main_~__retres1~8, ~T2_E~0, ~t6_st~0, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_6~0, ULTIMATE.start_main_#res, ~E_2~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 301069#L444 [2453] L444-->L451-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 301070#L451-1 [3030] L451-1-->L456-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 301160#L456-1 [2574] L456-1-->L461-1: Formula: (and (= v_~t2_st~0_2 0) (= 1 v_~t2_i~0_3)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_2} AuxVars[] AssignedVars[~t2_st~0] 301161#L461-1 [2880] L461-1-->L466-1: Formula: (and (= v_~t3_st~0_3 0) (= v_~t3_i~0_3 1)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_3, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 301071#L466-1 [2457] L466-1-->L471-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 301072#L471-1 [3209] L471-1-->L476-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 301317#L476-1 [2761] L476-1-->L481-1: Formula: (and (= 1 v_~t6_i~0_3) (= v_~t6_st~0_4 0)) InVars {~t6_i~0=v_~t6_i~0_3} OutVars{~t6_st~0=v_~t6_st~0_4, ~t6_i~0=v_~t6_i~0_3} AuxVars[] AssignedVars[~t6_st~0] 301318#L481-1 [3652] L481-1-->L660-1: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 301500#L660-1 [3654] L660-1-->L665-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 300986#L665-1 [3655] L665-1-->L670-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 300987#L670-1 [3658] L670-1-->L675-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 301078#L675-1 [3659] L675-1-->L680-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 301079#L680-1 [3661] L680-1-->L685-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 301330#L685-1 [3663] L685-1-->L690-1: Formula: (< 0 v_~T6_E~0_4) InVars {~T6_E~0=v_~T6_E~0_4} OutVars{~T6_E~0=v_~T6_E~0_4} AuxVars[] AssignedVars[] 301331#L690-1 [3665] L690-1-->L695-1: Formula: (> v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 301201#L695-1 [3668] L695-1-->L700-1: Formula: (> v_~E_2~0_6 0) InVars {~E_2~0=v_~E_2~0_6} OutVars{~E_2~0=v_~E_2~0_6} AuxVars[] AssignedVars[] 301202#L700-1 [3670] L700-1-->L705-1: Formula: (> v_~E_3~0_6 0) InVars {~E_3~0=v_~E_3~0_6} OutVars{~E_3~0=v_~E_3~0_6} AuxVars[] AssignedVars[] 301467#L705-1 [3672] L705-1-->L710-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 301140#L710-1 [3674] L710-1-->L715-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 301141#L715-1 [3675] L715-1-->L720-1: Formula: (> v_~E_6~0_4 0) InVars {~E_6~0=v_~E_6~0_4} OutVars{~E_6~0=v_~E_6~0_4} AuxVars[] AssignedVars[] 301020#L720-1 [2412] L720-1-->L310: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_7, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_4|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_4|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_7, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_4, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_4, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_2|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_2|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_4|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_4|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_7, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_2|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_4} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 301021#L310 [3678] L310-->L310-2: Formula: (< v_~m_pc~0_5 1) InVars {~m_pc~0=v_~m_pc~0_5} OutVars{~m_pc~0=v_~m_pc~0_5} AuxVars[] AssignedVars[] 301174#L310-2 [2805] L310-2-->L321: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_11 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 301172#L321 [4267] L321-->L815: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 301173#L815 [2976] L815-->L815-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_12) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} AuxVars[] AssignedVars[] 301462#L815-2 [2961] L815-2-->L329: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 301385#L329 [3683] L329-->L329-2: Formula: (< v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 301386#L329-2 [2861] L329-2-->L340: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 301383#L340 [4268] L340-->L823: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 301384#L823 [3234] L823-->L823-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} AuxVars[] AssignedVars[] 301589#L823-2 [3235] L823-2-->L348: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_4|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 301558#L348 [3690] L348-->L348-2: Formula: (< v_~t2_pc~0_5 1) InVars {~t2_pc~0=v_~t2_pc~0_5} OutVars{~t2_pc~0=v_~t2_pc~0_5} AuxVars[] AssignedVars[] 301560#L348-2 [3153] L348-2-->L359: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 301557#L359 [4269] L359-->L831: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 301149#L831 [2537] L831-->L831-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} AuxVars[] AssignedVars[] 301135#L831-2 [2520] L831-2-->L367: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_4|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 301074#L367 [3695] L367-->L367-2: Formula: (> 1 v_~t3_pc~0_5) InVars {~t3_pc~0=v_~t3_pc~0_5} OutVars{~t3_pc~0=v_~t3_pc~0_5} AuxVars[] AssignedVars[] 301050#L367-2 [2438] L367-2-->L378: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 301051#L378 [4270] L378-->L839: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 301073#L839 [2791] L839-->L839-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} AuxVars[] AssignedVars[] 301344#L839-2 [2794] L839-2-->L386: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_7, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 301253#L386 [3702] L386-->L386-2: Formula: (< v_~t4_pc~0_5 1) InVars {~t4_pc~0=v_~t4_pc~0_5} OutVars{~t4_pc~0=v_~t4_pc~0_5} AuxVars[] AssignedVars[] 301254#L386-2 [2680] L386-2-->L397: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 301251#L397 [4271] L397-->L847: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 301252#L847 [3084] L847-->L847-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} AuxVars[] AssignedVars[] 301509#L847-2 [3064] L847-2-->L405: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_4|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 301510#L405 [3708] L405-->L405-2: Formula: (> 1 v_~t5_pc~0_5) InVars {~t5_pc~0=v_~t5_pc~0_5} OutVars{~t5_pc~0=v_~t5_pc~0_5} AuxVars[] AssignedVars[] 301413#L405-2 [2940] L405-2-->L416: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 301449#L416 [4272] L416-->L855: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 301521#L855 [3091] L855-->L855-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_12} AuxVars[] AssignedVars[] 301522#L855-2 [3093] L855-2-->L424: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_4|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 301118#L424 [3713] L424-->L424-2: Formula: (< v_~t6_pc~0_5 1) InVars {~t6_pc~0=v_~t6_pc~0_5} OutVars{~t6_pc~0=v_~t6_pc~0_5} AuxVars[] AssignedVars[] 301119#L424-2 [2503] L424-2-->L435: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 301117#L435 [4273] L435-->L863: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___5~0_49 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_28|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_28|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 301036#L863 [2425] L863-->L863-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___5~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} AuxVars[] AssignedVars[] 301010#L863-2 [3719] L863-2-->L733-1: Formula: (> v_~M_E~0_15 1) InVars {~M_E~0=v_~M_E~0_15} OutVars{~M_E~0=v_~M_E~0_15} AuxVars[] AssignedVars[] 301011#L733-1 [3722] L733-1-->L738-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 301465#L738-1 [3723] L738-1-->L743-1: Formula: (< 1 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 301138#L743-1 [3726] L743-1-->L748-1: Formula: (< 1 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 301139#L748-1 [3728] L748-1-->L753-1: Formula: (> v_~T4_E~0_10 1) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 301015#L753-1 [3729] L753-1-->L758-1: Formula: (< 1 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 301016#L758-1 [3731] L758-1-->L763-1: Formula: (> v_~T6_E~0_10 1) InVars {~T6_E~0=v_~T6_E~0_10} OutVars{~T6_E~0=v_~T6_E~0_10} AuxVars[] AssignedVars[] 301090#L763-1 [3733] L763-1-->L768-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 301091#L768-1 [3736] L768-1-->L773-1: Formula: (< 1 v_~E_2~0_14) InVars {~E_2~0=v_~E_2~0_14} OutVars{~E_2~0=v_~E_2~0_14} AuxVars[] AssignedVars[] 301323#L773-1 [3737] L773-1-->L778-1: Formula: (< 1 v_~E_3~0_14) InVars {~E_3~0=v_~E_3~0_14} OutVars{~E_3~0=v_~E_3~0_14} AuxVars[] AssignedVars[] 301324#L778-1 [3740] L778-1-->L783-1: Formula: (< 1 v_~E_4~0_14) InVars {~E_4~0=v_~E_4~0_14} OutVars{~E_4~0=v_~E_4~0_14} AuxVars[] AssignedVars[] 301195#L783-1 [3741] L783-1-->L788-1: Formula: (< 1 v_~E_5~0_14) InVars {~E_5~0=v_~E_5~0_14} OutVars{~E_5~0=v_~E_5~0_14} AuxVars[] AssignedVars[] 301196#L788-1 [3744] L788-1-->L1014-1: Formula: (< 1 v_~E_6~0_14) InVars {~E_6~0=v_~E_6~0_14} OutVars{~E_6~0=v_~E_6~0_14} AuxVars[] AssignedVars[] 301572#L1014-1 [4274] L1014-1-->L635: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp_ndt_7~0=v_ULTIMATE.start_eval_~tmp_ndt_7~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp_ndt_7~0] 302135#L635 [2020-06-22 00:13:41,024 INFO L796 eck$LassoCheckResult]: Loop: 302135#L635 [4275] L635-->L494: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_37} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 302132#L494 [2876] L494-->L531: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21 1) (= v_~m_st~0_8 0)) InVars {~m_st~0=v_~m_st~0_8} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21, ~m_st~0=v_~m_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 302128#L531 [4276] L531-->L546: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 302126#L546 [3757] L546-->L546-1: Formula: (> v_ULTIMATE.start_eval_~tmp~0_4 0) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} OutVars{ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} AuxVars[] AssignedVars[] 302122#L546-1 [3164] L546-1-->L554: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_2 |v_ULTIMATE.start_eval_#t~nondet1_3|) (= 0 v_~m_st~0_10)) InVars {~m_st~0=v_~m_st~0_10, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_3|} OutVars{ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_2|, ~m_st~0=v_~m_st~0_10, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_1~0] 302118#L554 [2472] L554-->L551: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} AuxVars[] AssignedVars[] 302116#L551 [3772] L551-->L565: Formula: (< 0 v_~t1_st~0_15) InVars {~t1_st~0=v_~t1_st~0_15} OutVars{~t1_st~0=v_~t1_st~0_15} AuxVars[] AssignedVars[] 302098#L565 [3781] L565-->L579: Formula: (> v_~t2_st~0_16 0) InVars {~t2_st~0=v_~t2_st~0_16} OutVars{~t2_st~0=v_~t2_st~0_16} AuxVars[] AssignedVars[] 302154#L579 [3793] L579-->L593: Formula: (> 0 v_~t3_st~0_18) InVars {~t3_st~0=v_~t3_st~0_18} OutVars{~t3_st~0=v_~t3_st~0_18} AuxVars[] AssignedVars[] 302149#L593 [3803] L593-->L607: Formula: (> 0 v_~t4_st~0_20) InVars {~t4_st~0=v_~t4_st~0_20} OutVars{~t4_st~0=v_~t4_st~0_20} AuxVars[] AssignedVars[] 302145#L607 [3815] L607-->L621: Formula: (< v_~t5_st~0_21 0) InVars {~t5_st~0=v_~t5_st~0_21} OutVars{~t5_st~0=v_~t5_st~0_21} AuxVars[] AssignedVars[] 302137#L621 [3829] L621-->L635: Formula: (< 0 v_~t6_st~0_21) InVars {~t6_st~0=v_~t6_st~0_21} OutVars{~t6_st~0=v_~t6_st~0_21} AuxVars[] AssignedVars[] 302135#L635 [2020-06-22 00:13:41,025 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:41,025 INFO L82 PathProgramCache]: Analyzing trace with hash 218945922, now seen corresponding path program 2 times [2020-06-22 00:13:41,025 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:41,025 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:41,026 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:41,026 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:41,026 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:41,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:13:41,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:13:41,047 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:41,047 INFO L82 PathProgramCache]: Analyzing trace with hash 474993424, now seen corresponding path program 1 times [2020-06-22 00:13:41,047 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:41,047 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:41,048 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:41,048 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2020-06-22 00:13:41,048 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:41,050 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:13:41,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:13:41,053 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:41,053 INFO L82 PathProgramCache]: Analyzing trace with hash 937784081, now seen corresponding path program 1 times [2020-06-22 00:13:41,053 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:41,053 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:41,054 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:41,054 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:41,054 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:41,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:41,078 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:41,078 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:41,078 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-06-22 00:13:41,155 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-06-22 00:13:41,155 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-06-22 00:13:41,155 INFO L87 Difference]: Start difference. First operand 16161 states and 24101 transitions. cyclomatic complexity: 7943 Second operand 3 states. [2020-06-22 00:13:41,794 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-06-22 00:13:41,794 INFO L93 Difference]: Finished difference Result 28253 states and 41741 transitions. [2020-06-22 00:13:41,795 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-06-22 00:13:41,795 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 28253 states and 41741 transitions. [2020-06-22 00:13:41,913 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 28180 [2020-06-22 00:13:41,990 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 28253 states to 28253 states and 41741 transitions. [2020-06-22 00:13:41,990 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 28253 [2020-06-22 00:13:42,010 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28253 [2020-06-22 00:13:42,010 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28253 states and 41741 transitions. [2020-06-22 00:13:42,029 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-06-22 00:13:42,030 INFO L706 BuchiCegarLoop]: Abstraction has 28253 states and 41741 transitions. [2020-06-22 00:13:42,041 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28253 states and 41741 transitions. [2020-06-22 00:13:42,247 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28253 to 28253. [2020-06-22 00:13:42,248 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 28253 states. [2020-06-22 00:13:42,301 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28253 states to 28253 states and 41741 transitions. [2020-06-22 00:13:42,301 INFO L729 BuchiCegarLoop]: Abstraction has 28253 states and 41741 transitions. [2020-06-22 00:13:42,301 INFO L609 BuchiCegarLoop]: Abstraction has 28253 states and 41741 transitions. [2020-06-22 00:13:42,301 INFO L442 BuchiCegarLoop]: ======== Iteration 43============ [2020-06-22 00:13:42,301 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28253 states and 41741 transitions. [2020-06-22 00:13:42,396 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 28180 [2020-06-22 00:13:42,396 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-06-22 00:13:42,396 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-06-22 00:13:42,397 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:42,397 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:42,398 INFO L794 eck$LassoCheckResult]: Stem: 345905#ULTIMATE.startENTRY [4266] ULTIMATE.startENTRY-->L444: Formula: (and (= 1 v_~t6_i~0_7) (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~M_E~0_37 2) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 0 v_~t6_pc~0_26) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_6~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= v_~T6_E~0_18 2) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~t6_st~0_24) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t6_pc~0=v_~t6_pc~0_26, ~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~T6_E~0=v_~T6_E~0_18, ~M_E~0=v_~M_E~0_37, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ~T4_E~0=v_~T4_E~0_18, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_4|, ~t6_i~0=v_~t6_i~0_7, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ULTIMATE.start_main_~__retres1~8=v_ULTIMATE.start_main_~__retres1~8_6, ~T2_E~0=v_~T2_E~0_18, ~t6_st~0=v_~t6_st~0_24, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_6~0=v_~E_6~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t6_pc~0, ~t5_i~0, ~t1_pc~0, ~t5_st~0, ~T6_E~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ~T4_E~0, ULTIMATE.start_start_simulation_#t~ret17, ~t6_i~0, ~t2_st~0, ~t2_pc~0, ULTIMATE.start_main_~__retres1~8, ~T2_E~0, ~t6_st~0, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_6~0, ULTIMATE.start_main_#res, ~E_2~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 345493#L444 [2453] L444-->L451-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 345494#L451-1 [3030] L451-1-->L456-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 345579#L456-1 [2574] L456-1-->L461-1: Formula: (and (= v_~t2_st~0_2 0) (= 1 v_~t2_i~0_3)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_2} AuxVars[] AssignedVars[~t2_st~0] 345580#L461-1 [2880] L461-1-->L466-1: Formula: (and (= v_~t3_st~0_3 0) (= v_~t3_i~0_3 1)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_3, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 345495#L466-1 [2457] L466-1-->L471-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 345496#L471-1 [3209] L471-1-->L476-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 345738#L476-1 [2761] L476-1-->L481-1: Formula: (and (= 1 v_~t6_i~0_3) (= v_~t6_st~0_4 0)) InVars {~t6_i~0=v_~t6_i~0_3} OutVars{~t6_st~0=v_~t6_st~0_4, ~t6_i~0=v_~t6_i~0_3} AuxVars[] AssignedVars[~t6_st~0] 345739#L481-1 [3652] L481-1-->L660-1: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 345922#L660-1 [3654] L660-1-->L665-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 345408#L665-1 [3655] L665-1-->L670-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 345409#L670-1 [3658] L670-1-->L675-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 345502#L675-1 [3659] L675-1-->L680-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 345503#L680-1 [3661] L680-1-->L685-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 345751#L685-1 [3663] L685-1-->L690-1: Formula: (< 0 v_~T6_E~0_4) InVars {~T6_E~0=v_~T6_E~0_4} OutVars{~T6_E~0=v_~T6_E~0_4} AuxVars[] AssignedVars[] 345752#L690-1 [3665] L690-1-->L695-1: Formula: (> v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 345619#L695-1 [3668] L695-1-->L700-1: Formula: (> v_~E_2~0_6 0) InVars {~E_2~0=v_~E_2~0_6} OutVars{~E_2~0=v_~E_2~0_6} AuxVars[] AssignedVars[] 345620#L700-1 [3670] L700-1-->L705-1: Formula: (> v_~E_3~0_6 0) InVars {~E_3~0=v_~E_3~0_6} OutVars{~E_3~0=v_~E_3~0_6} AuxVars[] AssignedVars[] 345887#L705-1 [3672] L705-1-->L710-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 345563#L710-1 [3674] L710-1-->L715-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 345564#L715-1 [3675] L715-1-->L720-1: Formula: (> v_~E_6~0_4 0) InVars {~E_6~0=v_~E_6~0_4} OutVars{~E_6~0=v_~E_6~0_4} AuxVars[] AssignedVars[] 345443#L720-1 [2412] L720-1-->L310: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_7, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_4|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_4|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_7, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_4, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_4, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_2|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_2|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_4|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_4|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_7, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_2|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_4} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 345444#L310 [3678] L310-->L310-2: Formula: (< v_~m_pc~0_5 1) InVars {~m_pc~0=v_~m_pc~0_5} OutVars{~m_pc~0=v_~m_pc~0_5} AuxVars[] AssignedVars[] 345592#L310-2 [2805] L310-2-->L321: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_11 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 345590#L321 [4267] L321-->L815: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 345591#L815 [2976] L815-->L815-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_12) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} AuxVars[] AssignedVars[] 345882#L815-2 [2961] L815-2-->L329: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 345807#L329 [3683] L329-->L329-2: Formula: (< v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 345808#L329-2 [2861] L329-2-->L340: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 345805#L340 [4268] L340-->L823: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 345806#L823 [3234] L823-->L823-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} AuxVars[] AssignedVars[] 346016#L823-2 [3235] L823-2-->L348: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_4|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 345980#L348 [3690] L348-->L348-2: Formula: (< v_~t2_pc~0_5 1) InVars {~t2_pc~0=v_~t2_pc~0_5} OutVars{~t2_pc~0=v_~t2_pc~0_5} AuxVars[] AssignedVars[] 345982#L348-2 [3153] L348-2-->L359: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 345979#L359 [4269] L359-->L831: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 345570#L831 [2537] L831-->L831-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} AuxVars[] AssignedVars[] 345558#L831-2 [2520] L831-2-->L367: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_4|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 345498#L367 [3695] L367-->L367-2: Formula: (> 1 v_~t3_pc~0_5) InVars {~t3_pc~0=v_~t3_pc~0_5} OutVars{~t3_pc~0=v_~t3_pc~0_5} AuxVars[] AssignedVars[] 345474#L367-2 [2438] L367-2-->L378: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 345475#L378 [4270] L378-->L839: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 345497#L839 [2791] L839-->L839-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} AuxVars[] AssignedVars[] 345766#L839-2 [2794] L839-2-->L386: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_7, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 345671#L386 [3702] L386-->L386-2: Formula: (< v_~t4_pc~0_5 1) InVars {~t4_pc~0=v_~t4_pc~0_5} OutVars{~t4_pc~0=v_~t4_pc~0_5} AuxVars[] AssignedVars[] 345672#L386-2 [2680] L386-2-->L397: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 345669#L397 [4271] L397-->L847: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 345670#L847 [3084] L847-->L847-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} AuxVars[] AssignedVars[] 345930#L847-2 [3064] L847-2-->L405: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_4|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 345931#L405 [3708] L405-->L405-2: Formula: (> 1 v_~t5_pc~0_5) InVars {~t5_pc~0=v_~t5_pc~0_5} OutVars{~t5_pc~0=v_~t5_pc~0_5} AuxVars[] AssignedVars[] 345836#L405-2 [2940] L405-2-->L416: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 345871#L416 [4272] L416-->L855: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 345941#L855 [3091] L855-->L855-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_12} AuxVars[] AssignedVars[] 345942#L855-2 [3093] L855-2-->L424: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_4|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 345541#L424 [3713] L424-->L424-2: Formula: (< v_~t6_pc~0_5 1) InVars {~t6_pc~0=v_~t6_pc~0_5} OutVars{~t6_pc~0=v_~t6_pc~0_5} AuxVars[] AssignedVars[] 345542#L424-2 [2503] L424-2-->L435: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 345540#L435 [4273] L435-->L863: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___5~0_49 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_28|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_28|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 345459#L863 [2425] L863-->L863-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___5~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} AuxVars[] AssignedVars[] 345433#L863-2 [3719] L863-2-->L733-1: Formula: (> v_~M_E~0_15 1) InVars {~M_E~0=v_~M_E~0_15} OutVars{~M_E~0=v_~M_E~0_15} AuxVars[] AssignedVars[] 345434#L733-1 [3722] L733-1-->L738-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 345885#L738-1 [3723] L738-1-->L743-1: Formula: (< 1 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 345561#L743-1 [3726] L743-1-->L748-1: Formula: (< 1 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 345562#L748-1 [3728] L748-1-->L753-1: Formula: (> v_~T4_E~0_10 1) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 345438#L753-1 [3729] L753-1-->L758-1: Formula: (< 1 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 345439#L758-1 [3731] L758-1-->L763-1: Formula: (> v_~T6_E~0_10 1) InVars {~T6_E~0=v_~T6_E~0_10} OutVars{~T6_E~0=v_~T6_E~0_10} AuxVars[] AssignedVars[] 345514#L763-1 [3733] L763-1-->L768-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 345515#L768-1 [3736] L768-1-->L773-1: Formula: (< 1 v_~E_2~0_14) InVars {~E_2~0=v_~E_2~0_14} OutVars{~E_2~0=v_~E_2~0_14} AuxVars[] AssignedVars[] 345743#L773-1 [3737] L773-1-->L778-1: Formula: (< 1 v_~E_3~0_14) InVars {~E_3~0=v_~E_3~0_14} OutVars{~E_3~0=v_~E_3~0_14} AuxVars[] AssignedVars[] 345744#L778-1 [3740] L778-1-->L783-1: Formula: (< 1 v_~E_4~0_14) InVars {~E_4~0=v_~E_4~0_14} OutVars{~E_4~0=v_~E_4~0_14} AuxVars[] AssignedVars[] 345613#L783-1 [3741] L783-1-->L788-1: Formula: (< 1 v_~E_5~0_14) InVars {~E_5~0=v_~E_5~0_14} OutVars{~E_5~0=v_~E_5~0_14} AuxVars[] AssignedVars[] 345614#L788-1 [3744] L788-1-->L1014-1: Formula: (< 1 v_~E_6~0_14) InVars {~E_6~0=v_~E_6~0_14} OutVars{~E_6~0=v_~E_6~0_14} AuxVars[] AssignedVars[] 345995#L1014-1 [4274] L1014-1-->L635: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp_ndt_7~0=v_ULTIMATE.start_eval_~tmp_ndt_7~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp_ndt_7~0] 347577#L635 [2020-06-22 00:13:42,398 INFO L796 eck$LassoCheckResult]: Loop: 347577#L635 [4275] L635-->L494: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_37} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 348480#L494 [2876] L494-->L531: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21 1) (= v_~m_st~0_8 0)) InVars {~m_st~0=v_~m_st~0_8} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21, ~m_st~0=v_~m_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 347464#L531 [4276] L531-->L546: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 347465#L546 [3757] L546-->L546-1: Formula: (> v_ULTIMATE.start_eval_~tmp~0_4 0) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} OutVars{ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} AuxVars[] AssignedVars[] 347436#L546-1 [3164] L546-1-->L554: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_2 |v_ULTIMATE.start_eval_#t~nondet1_3|) (= 0 v_~m_st~0_10)) InVars {~m_st~0=v_~m_st~0_10, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_3|} OutVars{ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_2|, ~m_st~0=v_~m_st~0_10, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_1~0] 347439#L554 [2472] L554-->L551: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} AuxVars[] AssignedVars[] 347143#L551 [2690] L551-->L568: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_2~0_2 |v_ULTIMATE.start_eval_#t~nondet2_3|) (= 0 v_~t1_st~0_11)) InVars {~t1_st~0=v_~t1_st~0_11, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_3|} OutVars{ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_2|, ~t1_st~0=v_~t1_st~0_11, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_2~0] 347139#L568 [3161] L568-->L565: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_2~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_5} AuxVars[] AssignedVars[] 347140#L565 [3781] L565-->L579: Formula: (> v_~t2_st~0_16 0) InVars {~t2_st~0=v_~t2_st~0_16} OutVars{~t2_st~0=v_~t2_st~0_16} AuxVars[] AssignedVars[] 347831#L579 [3793] L579-->L593: Formula: (> 0 v_~t3_st~0_18) InVars {~t3_st~0=v_~t3_st~0_18} OutVars{~t3_st~0=v_~t3_st~0_18} AuxVars[] AssignedVars[] 347590#L593 [3803] L593-->L607: Formula: (> 0 v_~t4_st~0_20) InVars {~t4_st~0=v_~t4_st~0_20} OutVars{~t4_st~0=v_~t4_st~0_20} AuxVars[] AssignedVars[] 347589#L607 [3815] L607-->L621: Formula: (< v_~t5_st~0_21 0) InVars {~t5_st~0=v_~t5_st~0_21} OutVars{~t5_st~0=v_~t5_st~0_21} AuxVars[] AssignedVars[] 348485#L621 [3829] L621-->L635: Formula: (< 0 v_~t6_st~0_21) InVars {~t6_st~0=v_~t6_st~0_21} OutVars{~t6_st~0=v_~t6_st~0_21} AuxVars[] AssignedVars[] 347577#L635 [2020-06-22 00:13:42,399 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:42,399 INFO L82 PathProgramCache]: Analyzing trace with hash 218945922, now seen corresponding path program 3 times [2020-06-22 00:13:42,399 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:42,399 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:42,400 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:42,400 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:42,400 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:42,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:13:42,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:13:42,417 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:42,417 INFO L82 PathProgramCache]: Analyzing trace with hash -1242974313, now seen corresponding path program 1 times [2020-06-22 00:13:42,417 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:42,417 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:42,418 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:42,418 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2020-06-22 00:13:42,418 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:42,420 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:13:42,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:13:42,423 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:42,423 INFO L82 PathProgramCache]: Analyzing trace with hash 218634166, now seen corresponding path program 1 times [2020-06-22 00:13:42,423 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:42,423 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:42,424 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:42,424 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:42,424 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:42,429 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:42,450 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:42,450 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:42,451 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-06-22 00:13:42,532 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-06-22 00:13:42,532 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-06-22 00:13:42,532 INFO L87 Difference]: Start difference. First operand 28253 states and 41741 transitions. cyclomatic complexity: 13491 Second operand 3 states. [2020-06-22 00:13:43,361 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-06-22 00:13:43,361 INFO L93 Difference]: Finished difference Result 51990 states and 76708 transitions. [2020-06-22 00:13:43,362 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-06-22 00:13:43,362 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 51990 states and 76708 transitions. [2020-06-22 00:13:43,790 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 51848 [2020-06-22 00:13:43,916 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 51990 states to 51990 states and 76708 transitions. [2020-06-22 00:13:43,916 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 51990 [2020-06-22 00:13:43,953 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 51990 [2020-06-22 00:13:43,953 INFO L73 IsDeterministic]: Start isDeterministic. Operand 51990 states and 76708 transitions. [2020-06-22 00:13:43,985 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-06-22 00:13:43,985 INFO L706 BuchiCegarLoop]: Abstraction has 51990 states and 76708 transitions. [2020-06-22 00:13:44,009 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51990 states and 76708 transitions. [2020-06-22 00:13:44,406 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51990 to 51990. [2020-06-22 00:13:44,407 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 51990 states. [2020-06-22 00:13:44,508 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51990 states to 51990 states and 76708 transitions. [2020-06-22 00:13:44,508 INFO L729 BuchiCegarLoop]: Abstraction has 51990 states and 76708 transitions. [2020-06-22 00:13:44,509 INFO L609 BuchiCegarLoop]: Abstraction has 51990 states and 76708 transitions. [2020-06-22 00:13:44,509 INFO L442 BuchiCegarLoop]: ======== Iteration 44============ [2020-06-22 00:13:44,509 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51990 states and 76708 transitions. [2020-06-22 00:13:44,701 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 51848 [2020-06-22 00:13:44,702 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-06-22 00:13:44,702 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-06-22 00:13:44,702 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:44,703 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:44,704 INFO L794 eck$LassoCheckResult]: Stem: 426163#ULTIMATE.startENTRY [4266] ULTIMATE.startENTRY-->L444: Formula: (and (= 1 v_~t6_i~0_7) (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~M_E~0_37 2) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 0 v_~t6_pc~0_26) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_6~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= v_~T6_E~0_18 2) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~t6_st~0_24) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t6_pc~0=v_~t6_pc~0_26, ~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~T6_E~0=v_~T6_E~0_18, ~M_E~0=v_~M_E~0_37, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ~T4_E~0=v_~T4_E~0_18, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_4|, ~t6_i~0=v_~t6_i~0_7, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ULTIMATE.start_main_~__retres1~8=v_ULTIMATE.start_main_~__retres1~8_6, ~T2_E~0=v_~T2_E~0_18, ~t6_st~0=v_~t6_st~0_24, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_6~0=v_~E_6~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t6_pc~0, ~t5_i~0, ~t1_pc~0, ~t5_st~0, ~T6_E~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ~T4_E~0, ULTIMATE.start_start_simulation_#t~ret17, ~t6_i~0, ~t2_st~0, ~t2_pc~0, ULTIMATE.start_main_~__retres1~8, ~T2_E~0, ~t6_st~0, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_6~0, ULTIMATE.start_main_#res, ~E_2~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 425742#L444 [2453] L444-->L451-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 425743#L451-1 [3030] L451-1-->L456-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 425831#L456-1 [3642] L456-1-->L461-1: Formula: (and (> 1 v_~t2_i~0_4) (= v_~t2_st~0_3 2)) InVars {~t2_i~0=v_~t2_i~0_4} OutVars{~t2_i~0=v_~t2_i~0_4, ~t2_st~0=v_~t2_st~0_3} AuxVars[] AssignedVars[~t2_st~0] 425832#L461-1 [2880] L461-1-->L466-1: Formula: (and (= v_~t3_st~0_3 0) (= v_~t3_i~0_3 1)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_3, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 449767#L466-1 [2457] L466-1-->L471-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 449766#L471-1 [3209] L471-1-->L476-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 449765#L476-1 [2761] L476-1-->L481-1: Formula: (and (= 1 v_~t6_i~0_3) (= v_~t6_st~0_4 0)) InVars {~t6_i~0=v_~t6_i~0_3} OutVars{~t6_st~0=v_~t6_st~0_4, ~t6_i~0=v_~t6_i~0_3} AuxVars[] AssignedVars[~t6_st~0] 449764#L481-1 [3652] L481-1-->L660-1: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 449763#L660-1 [3654] L660-1-->L665-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 449762#L665-1 [3655] L665-1-->L670-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 449761#L670-1 [3658] L670-1-->L675-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 449760#L675-1 [3659] L675-1-->L680-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 449759#L680-1 [3661] L680-1-->L685-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 449758#L685-1 [3663] L685-1-->L690-1: Formula: (< 0 v_~T6_E~0_4) InVars {~T6_E~0=v_~T6_E~0_4} OutVars{~T6_E~0=v_~T6_E~0_4} AuxVars[] AssignedVars[] 449757#L690-1 [3665] L690-1-->L695-1: Formula: (> v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 449756#L695-1 [3668] L695-1-->L700-1: Formula: (> v_~E_2~0_6 0) InVars {~E_2~0=v_~E_2~0_6} OutVars{~E_2~0=v_~E_2~0_6} AuxVars[] AssignedVars[] 449755#L700-1 [3670] L700-1-->L705-1: Formula: (> v_~E_3~0_6 0) InVars {~E_3~0=v_~E_3~0_6} OutVars{~E_3~0=v_~E_3~0_6} AuxVars[] AssignedVars[] 449754#L705-1 [3672] L705-1-->L710-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 449753#L710-1 [3674] L710-1-->L715-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 449752#L715-1 [3675] L715-1-->L720-1: Formula: (> v_~E_6~0_4 0) InVars {~E_6~0=v_~E_6~0_4} OutVars{~E_6~0=v_~E_6~0_4} AuxVars[] AssignedVars[] 449751#L720-1 [2412] L720-1-->L310: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_7, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_4|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_4|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_7, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_4, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_4, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_2|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_2|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_4|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_4|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_7, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_2|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_4} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 449750#L310 [3678] L310-->L310-2: Formula: (< v_~m_pc~0_5 1) InVars {~m_pc~0=v_~m_pc~0_5} OutVars{~m_pc~0=v_~m_pc~0_5} AuxVars[] AssignedVars[] 449749#L310-2 [2805] L310-2-->L321: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_11 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 449748#L321 [4267] L321-->L815: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 449747#L815 [2976] L815-->L815-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_12) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} AuxVars[] AssignedVars[] 449746#L815-2 [2961] L815-2-->L329: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 449745#L329 [3683] L329-->L329-2: Formula: (< v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 449744#L329-2 [2861] L329-2-->L340: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 449743#L340 [4268] L340-->L823: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 449742#L823 [3234] L823-->L823-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} AuxVars[] AssignedVars[] 449741#L823-2 [3235] L823-2-->L348: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_4|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 449739#L348 [3690] L348-->L348-2: Formula: (< v_~t2_pc~0_5 1) InVars {~t2_pc~0=v_~t2_pc~0_5} OutVars{~t2_pc~0=v_~t2_pc~0_5} AuxVars[] AssignedVars[] 449738#L348-2 [3153] L348-2-->L359: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 449737#L359 [4269] L359-->L831: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 449736#L831 [2537] L831-->L831-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} AuxVars[] AssignedVars[] 449735#L831-2 [2520] L831-2-->L367: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_4|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 449733#L367 [3695] L367-->L367-2: Formula: (> 1 v_~t3_pc~0_5) InVars {~t3_pc~0=v_~t3_pc~0_5} OutVars{~t3_pc~0=v_~t3_pc~0_5} AuxVars[] AssignedVars[] 449730#L367-2 [2438] L367-2-->L378: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 449728#L378 [4270] L378-->L839: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 426020#L839 [2791] L839-->L839-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} AuxVars[] AssignedVars[] 426021#L839-2 [2794] L839-2-->L386: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_7, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 449687#L386 [3702] L386-->L386-2: Formula: (< v_~t4_pc~0_5 1) InVars {~t4_pc~0=v_~t4_pc~0_5} OutVars{~t4_pc~0=v_~t4_pc~0_5} AuxVars[] AssignedVars[] 449685#L386-2 [2680] L386-2-->L397: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 449684#L397 [4271] L397-->L847: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 449682#L847 [3084] L847-->L847-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} AuxVars[] AssignedVars[] 449680#L847-2 [3064] L847-2-->L405: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_4|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 449674#L405 [3708] L405-->L405-2: Formula: (> 1 v_~t5_pc~0_5) InVars {~t5_pc~0=v_~t5_pc~0_5} OutVars{~t5_pc~0=v_~t5_pc~0_5} AuxVars[] AssignedVars[] 449672#L405-2 [2940] L405-2-->L416: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 449670#L416 [4272] L416-->L855: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 449668#L855 [3091] L855-->L855-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_12} AuxVars[] AssignedVars[] 449666#L855-2 [3093] L855-2-->L424: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_4|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 449664#L424 [3713] L424-->L424-2: Formula: (< v_~t6_pc~0_5 1) InVars {~t6_pc~0=v_~t6_pc~0_5} OutVars{~t6_pc~0=v_~t6_pc~0_5} AuxVars[] AssignedVars[] 449662#L424-2 [2503] L424-2-->L435: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 449660#L435 [4273] L435-->L863: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___5~0_49 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_28|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_28|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 449658#L863 [2425] L863-->L863-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___5~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} AuxVars[] AssignedVars[] 449656#L863-2 [3719] L863-2-->L733-1: Formula: (> v_~M_E~0_15 1) InVars {~M_E~0=v_~M_E~0_15} OutVars{~M_E~0=v_~M_E~0_15} AuxVars[] AssignedVars[] 449654#L733-1 [3722] L733-1-->L738-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 449653#L738-1 [3723] L738-1-->L743-1: Formula: (< 1 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 449651#L743-1 [3726] L743-1-->L748-1: Formula: (< 1 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 449650#L748-1 [3728] L748-1-->L753-1: Formula: (> v_~T4_E~0_10 1) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 449649#L753-1 [3729] L753-1-->L758-1: Formula: (< 1 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 449647#L758-1 [3731] L758-1-->L763-1: Formula: (> v_~T6_E~0_10 1) InVars {~T6_E~0=v_~T6_E~0_10} OutVars{~T6_E~0=v_~T6_E~0_10} AuxVars[] AssignedVars[] 449645#L763-1 [3733] L763-1-->L768-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 449643#L768-1 [3736] L768-1-->L773-1: Formula: (< 1 v_~E_2~0_14) InVars {~E_2~0=v_~E_2~0_14} OutVars{~E_2~0=v_~E_2~0_14} AuxVars[] AssignedVars[] 449642#L773-1 [3737] L773-1-->L778-1: Formula: (< 1 v_~E_3~0_14) InVars {~E_3~0=v_~E_3~0_14} OutVars{~E_3~0=v_~E_3~0_14} AuxVars[] AssignedVars[] 449640#L778-1 [3740] L778-1-->L783-1: Formula: (< 1 v_~E_4~0_14) InVars {~E_4~0=v_~E_4~0_14} OutVars{~E_4~0=v_~E_4~0_14} AuxVars[] AssignedVars[] 449638#L783-1 [3741] L783-1-->L788-1: Formula: (< 1 v_~E_5~0_14) InVars {~E_5~0=v_~E_5~0_14} OutVars{~E_5~0=v_~E_5~0_14} AuxVars[] AssignedVars[] 449636#L788-1 [3744] L788-1-->L1014-1: Formula: (< 1 v_~E_6~0_14) InVars {~E_6~0=v_~E_6~0_14} OutVars{~E_6~0=v_~E_6~0_14} AuxVars[] AssignedVars[] 449634#L1014-1 [4274] L1014-1-->L635: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp_ndt_7~0=v_ULTIMATE.start_eval_~tmp_ndt_7~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp_ndt_7~0] 449567#L635 [2020-06-22 00:13:44,704 INFO L796 eck$LassoCheckResult]: Loop: 449567#L635 [4275] L635-->L494: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_37} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 449626#L494 [2876] L494-->L531: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21 1) (= v_~m_st~0_8 0)) InVars {~m_st~0=v_~m_st~0_8} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21, ~m_st~0=v_~m_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 449622#L531 [4276] L531-->L546: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 449621#L546 [3757] L546-->L546-1: Formula: (> v_ULTIMATE.start_eval_~tmp~0_4 0) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} OutVars{ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} AuxVars[] AssignedVars[] 449618#L546-1 [3164] L546-1-->L554: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_2 |v_ULTIMATE.start_eval_#t~nondet1_3|) (= 0 v_~m_st~0_10)) InVars {~m_st~0=v_~m_st~0_10, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_3|} OutVars{ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_2|, ~m_st~0=v_~m_st~0_10, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_1~0] 449617#L554 [2472] L554-->L551: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} AuxVars[] AssignedVars[] 438783#L551 [2690] L551-->L568: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_2~0_2 |v_ULTIMATE.start_eval_#t~nondet2_3|) (= 0 v_~t1_st~0_11)) InVars {~t1_st~0=v_~t1_st~0_11, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_3|} OutVars{ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_2|, ~t1_st~0=v_~t1_st~0_11, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_2~0] 438780#L568 [3161] L568-->L565: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_2~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_5} AuxVars[] AssignedVars[] 438781#L565 [3781] L565-->L579: Formula: (> v_~t2_st~0_16 0) InVars {~t2_st~0=v_~t2_st~0_16} OutVars{~t2_st~0=v_~t2_st~0_16} AuxVars[] AssignedVars[] 449581#L579 [3793] L579-->L593: Formula: (> 0 v_~t3_st~0_18) InVars {~t3_st~0=v_~t3_st~0_18} OutVars{~t3_st~0=v_~t3_st~0_18} AuxVars[] AssignedVars[] 449577#L593 [3803] L593-->L607: Formula: (> 0 v_~t4_st~0_20) InVars {~t4_st~0=v_~t4_st~0_20} OutVars{~t4_st~0=v_~t4_st~0_20} AuxVars[] AssignedVars[] 449573#L607 [3815] L607-->L621: Formula: (< v_~t5_st~0_21 0) InVars {~t5_st~0=v_~t5_st~0_21} OutVars{~t5_st~0=v_~t5_st~0_21} AuxVars[] AssignedVars[] 449569#L621 [3829] L621-->L635: Formula: (< 0 v_~t6_st~0_21) InVars {~t6_st~0=v_~t6_st~0_21} OutVars{~t6_st~0=v_~t6_st~0_21} AuxVars[] AssignedVars[] 449567#L635 [2020-06-22 00:13:44,704 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:44,704 INFO L82 PathProgramCache]: Analyzing trace with hash -667082066, now seen corresponding path program 1 times [2020-06-22 00:13:44,704 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:44,705 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:44,705 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:44,705 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:44,705 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:44,708 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:44,719 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:44,719 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:44,719 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-06-22 00:13:44,720 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-06-22 00:13:44,720 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:44,720 INFO L82 PathProgramCache]: Analyzing trace with hash -1242974313, now seen corresponding path program 2 times [2020-06-22 00:13:44,720 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:44,720 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:44,721 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:44,721 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:44,721 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:44,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:13:44,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:13:44,811 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-06-22 00:13:44,811 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-06-22 00:13:44,811 INFO L87 Difference]: Start difference. First operand 51990 states and 76708 transitions. cyclomatic complexity: 24721 Second operand 3 states. [2020-06-22 00:13:45,289 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-06-22 00:13:45,289 INFO L93 Difference]: Finished difference Result 51990 states and 76707 transitions. [2020-06-22 00:13:45,290 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-06-22 00:13:45,290 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 51990 states and 76707 transitions. [2020-06-22 00:13:45,527 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 51848 [2020-06-22 00:13:45,678 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 51990 states to 51990 states and 76707 transitions. [2020-06-22 00:13:45,678 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 51990 [2020-06-22 00:13:45,716 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 51990 [2020-06-22 00:13:45,716 INFO L73 IsDeterministic]: Start isDeterministic. Operand 51990 states and 76707 transitions. [2020-06-22 00:13:45,749 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-06-22 00:13:45,749 INFO L706 BuchiCegarLoop]: Abstraction has 51990 states and 76707 transitions. [2020-06-22 00:13:45,773 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51990 states and 76707 transitions. [2020-06-22 00:13:47,570 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51990 to 51990. [2020-06-22 00:13:47,570 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 51990 states. [2020-06-22 00:13:47,672 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51990 states to 51990 states and 76707 transitions. [2020-06-22 00:13:47,672 INFO L729 BuchiCegarLoop]: Abstraction has 51990 states and 76707 transitions. [2020-06-22 00:13:47,672 INFO L609 BuchiCegarLoop]: Abstraction has 51990 states and 76707 transitions. [2020-06-22 00:13:47,672 INFO L442 BuchiCegarLoop]: ======== Iteration 45============ [2020-06-22 00:13:47,672 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51990 states and 76707 transitions. [2020-06-22 00:13:47,855 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 51848 [2020-06-22 00:13:47,855 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-06-22 00:13:47,855 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-06-22 00:13:47,856 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:47,856 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:47,857 INFO L794 eck$LassoCheckResult]: Stem: 530152#ULTIMATE.startENTRY [4266] ULTIMATE.startENTRY-->L444: Formula: (and (= 1 v_~t6_i~0_7) (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~M_E~0_37 2) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 0 v_~t6_pc~0_26) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_6~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= v_~T6_E~0_18 2) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~t6_st~0_24) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t6_pc~0=v_~t6_pc~0_26, ~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~T6_E~0=v_~T6_E~0_18, ~M_E~0=v_~M_E~0_37, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ~T4_E~0=v_~T4_E~0_18, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_4|, ~t6_i~0=v_~t6_i~0_7, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ULTIMATE.start_main_~__retres1~8=v_ULTIMATE.start_main_~__retres1~8_6, ~T2_E~0=v_~T2_E~0_18, ~t6_st~0=v_~t6_st~0_24, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_6~0=v_~E_6~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t6_pc~0, ~t5_i~0, ~t1_pc~0, ~t5_st~0, ~T6_E~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ~T4_E~0, ULTIMATE.start_start_simulation_#t~ret17, ~t6_i~0, ~t2_st~0, ~t2_pc~0, ULTIMATE.start_main_~__retres1~8, ~T2_E~0, ~t6_st~0, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_6~0, ULTIMATE.start_main_#res, ~E_2~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 529727#L444 [2453] L444-->L451-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 529728#L451-1 [3030] L451-1-->L456-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 529821#L456-1 [3641] L456-1-->L461-1: Formula: (and (= v_~t2_st~0_3 2) (< 1 v_~t2_i~0_4)) InVars {~t2_i~0=v_~t2_i~0_4} OutVars{~t2_i~0=v_~t2_i~0_4, ~t2_st~0=v_~t2_st~0_3} AuxVars[] AssignedVars[~t2_st~0] 529822#L461-1 [2880] L461-1-->L466-1: Formula: (and (= v_~t3_st~0_3 0) (= v_~t3_i~0_3 1)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_3, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 529732#L466-1 [2457] L466-1-->L471-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 529733#L471-1 [3209] L471-1-->L476-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 529977#L476-1 [2761] L476-1-->L481-1: Formula: (and (= 1 v_~t6_i~0_3) (= v_~t6_st~0_4 0)) InVars {~t6_i~0=v_~t6_i~0_3} OutVars{~t6_st~0=v_~t6_st~0_4, ~t6_i~0=v_~t6_i~0_3} AuxVars[] AssignedVars[~t6_st~0] 529978#L481-1 [3652] L481-1-->L660-1: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 530171#L660-1 [3654] L660-1-->L665-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 529645#L665-1 [3655] L665-1-->L670-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 529646#L670-1 [3658] L670-1-->L675-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 529739#L675-1 [3659] L675-1-->L680-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 529740#L680-1 [3661] L680-1-->L685-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 529991#L685-1 [3663] L685-1-->L690-1: Formula: (< 0 v_~T6_E~0_4) InVars {~T6_E~0=v_~T6_E~0_4} OutVars{~T6_E~0=v_~T6_E~0_4} AuxVars[] AssignedVars[] 529992#L690-1 [3665] L690-1-->L695-1: Formula: (> v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 529862#L695-1 [3668] L695-1-->L700-1: Formula: (> v_~E_2~0_6 0) InVars {~E_2~0=v_~E_2~0_6} OutVars{~E_2~0=v_~E_2~0_6} AuxVars[] AssignedVars[] 529863#L700-1 [3670] L700-1-->L705-1: Formula: (> v_~E_3~0_6 0) InVars {~E_3~0=v_~E_3~0_6} OutVars{~E_3~0=v_~E_3~0_6} AuxVars[] AssignedVars[] 530135#L705-1 [3672] L705-1-->L710-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 529802#L710-1 [3674] L710-1-->L715-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 529803#L715-1 [3675] L715-1-->L720-1: Formula: (> v_~E_6~0_4 0) InVars {~E_6~0=v_~E_6~0_4} OutVars{~E_6~0=v_~E_6~0_4} AuxVars[] AssignedVars[] 529679#L720-1 [2412] L720-1-->L310: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_7, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_4|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_4|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_7, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_4, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_4, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_2|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_2|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_4|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_4|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_7, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_2|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_4} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 529680#L310 [3678] L310-->L310-2: Formula: (< v_~m_pc~0_5 1) InVars {~m_pc~0=v_~m_pc~0_5} OutVars{~m_pc~0=v_~m_pc~0_5} AuxVars[] AssignedVars[] 529835#L310-2 [2805] L310-2-->L321: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_11 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 529830#L321 [4267] L321-->L815: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 529831#L815 [2976] L815-->L815-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_12) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} AuxVars[] AssignedVars[] 530130#L815-2 [2961] L815-2-->L329: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 530048#L329 [3683] L329-->L329-2: Formula: (< v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 530049#L329-2 [2861] L329-2-->L340: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 530044#L340 [4268] L340-->L823: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 530045#L823 [3234] L823-->L823-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} AuxVars[] AssignedVars[] 530274#L823-2 [3235] L823-2-->L348: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_4|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 530235#L348 [3690] L348-->L348-2: Formula: (< v_~t2_pc~0_5 1) InVars {~t2_pc~0=v_~t2_pc~0_5} OutVars{~t2_pc~0=v_~t2_pc~0_5} AuxVars[] AssignedVars[] 530237#L348-2 [3153] L348-2-->L359: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 530234#L359 [4269] L359-->L831: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 529810#L831 [2537] L831-->L831-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} AuxVars[] AssignedVars[] 529797#L831-2 [2520] L831-2-->L367: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_4|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 529735#L367 [3695] L367-->L367-2: Formula: (> 1 v_~t3_pc~0_5) InVars {~t3_pc~0=v_~t3_pc~0_5} OutVars{~t3_pc~0=v_~t3_pc~0_5} AuxVars[] AssignedVars[] 529712#L367-2 [2438] L367-2-->L378: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 529713#L378 [4270] L378-->L839: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 529734#L839 [2791] L839-->L839-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} AuxVars[] AssignedVars[] 530003#L839-2 [2794] L839-2-->L386: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_7, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 529913#L386 [3702] L386-->L386-2: Formula: (< v_~t4_pc~0_5 1) InVars {~t4_pc~0=v_~t4_pc~0_5} OutVars{~t4_pc~0=v_~t4_pc~0_5} AuxVars[] AssignedVars[] 529914#L386-2 [2680] L386-2-->L397: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 529911#L397 [4271] L397-->L847: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 529912#L847 [3084] L847-->L847-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} AuxVars[] AssignedVars[] 530181#L847-2 [3064] L847-2-->L405: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_4|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 530182#L405 [3708] L405-->L405-2: Formula: (> 1 v_~t5_pc~0_5) InVars {~t5_pc~0=v_~t5_pc~0_5} OutVars{~t5_pc~0=v_~t5_pc~0_5} AuxVars[] AssignedVars[] 553683#L405-2 [2940] L405-2-->L416: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 530267#L416 [4272] L416-->L855: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 530195#L855 [3091] L855-->L855-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_12} AuxVars[] AssignedVars[] 530196#L855-2 [3093] L855-2-->L424: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_4|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 530198#L424 [3713] L424-->L424-2: Formula: (< v_~t6_pc~0_5 1) InVars {~t6_pc~0=v_~t6_pc~0_5} OutVars{~t6_pc~0=v_~t6_pc~0_5} AuxVars[] AssignedVars[] 553669#L424-2 [2503] L424-2-->L435: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 553643#L435 [4273] L435-->L863: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___5~0_49 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_28|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_28|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 553641#L863 [2425] L863-->L863-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___5~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} AuxVars[] AssignedVars[] 529666#L863-2 [3719] L863-2-->L733-1: Formula: (> v_~M_E~0_15 1) InVars {~M_E~0=v_~M_E~0_15} OutVars{~M_E~0=v_~M_E~0_15} AuxVars[] AssignedVars[] 529667#L733-1 [3722] L733-1-->L738-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 530133#L738-1 [3723] L738-1-->L743-1: Formula: (< 1 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 529800#L743-1 [3726] L743-1-->L748-1: Formula: (< 1 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 529801#L748-1 [3728] L748-1-->L753-1: Formula: (> v_~T4_E~0_10 1) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 529674#L753-1 [3729] L753-1-->L758-1: Formula: (< 1 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 529675#L758-1 [3731] L758-1-->L763-1: Formula: (> v_~T6_E~0_10 1) InVars {~T6_E~0=v_~T6_E~0_10} OutVars{~T6_E~0=v_~T6_E~0_10} AuxVars[] AssignedVars[] 529751#L763-1 [3733] L763-1-->L768-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 529752#L768-1 [3736] L768-1-->L773-1: Formula: (< 1 v_~E_2~0_14) InVars {~E_2~0=v_~E_2~0_14} OutVars{~E_2~0=v_~E_2~0_14} AuxVars[] AssignedVars[] 529981#L773-1 [3737] L773-1-->L778-1: Formula: (< 1 v_~E_3~0_14) InVars {~E_3~0=v_~E_3~0_14} OutVars{~E_3~0=v_~E_3~0_14} AuxVars[] AssignedVars[] 529982#L778-1 [3740] L778-1-->L783-1: Formula: (< 1 v_~E_4~0_14) InVars {~E_4~0=v_~E_4~0_14} OutVars{~E_4~0=v_~E_4~0_14} AuxVars[] AssignedVars[] 553500#L783-1 [3741] L783-1-->L788-1: Formula: (< 1 v_~E_5~0_14) InVars {~E_5~0=v_~E_5~0_14} OutVars{~E_5~0=v_~E_5~0_14} AuxVars[] AssignedVars[] 553497#L788-1 [3744] L788-1-->L1014-1: Formula: (< 1 v_~E_6~0_14) InVars {~E_6~0=v_~E_6~0_14} OutVars{~E_6~0=v_~E_6~0_14} AuxVars[] AssignedVars[] 553481#L1014-1 [4274] L1014-1-->L635: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp_ndt_7~0=v_ULTIMATE.start_eval_~tmp_ndt_7~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp_ndt_7~0] 546243#L635 [2020-06-22 00:13:47,857 INFO L796 eck$LassoCheckResult]: Loop: 546243#L635 [4275] L635-->L494: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_37} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 553457#L494 [2876] L494-->L531: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21 1) (= v_~m_st~0_8 0)) InVars {~m_st~0=v_~m_st~0_8} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21, ~m_st~0=v_~m_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 553447#L531 [4276] L531-->L546: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 553439#L546 [3757] L546-->L546-1: Formula: (> v_ULTIMATE.start_eval_~tmp~0_4 0) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} OutVars{ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} AuxVars[] AssignedVars[] 553429#L546-1 [3164] L546-1-->L554: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_2 |v_ULTIMATE.start_eval_#t~nondet1_3|) (= 0 v_~m_st~0_10)) InVars {~m_st~0=v_~m_st~0_10, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_3|} OutVars{ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_2|, ~m_st~0=v_~m_st~0_10, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_1~0] 553421#L554 [2472] L554-->L551: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} AuxVars[] AssignedVars[] 550448#L551 [2690] L551-->L568: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_2~0_2 |v_ULTIMATE.start_eval_#t~nondet2_3|) (= 0 v_~t1_st~0_11)) InVars {~t1_st~0=v_~t1_st~0_11, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_3|} OutVars{ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_2|, ~t1_st~0=v_~t1_st~0_11, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_2~0] 550204#L568 [3161] L568-->L565: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_2~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_5} AuxVars[] AssignedVars[] 550205#L565 [3781] L565-->L579: Formula: (> v_~t2_st~0_16 0) InVars {~t2_st~0=v_~t2_st~0_16} OutVars{~t2_st~0=v_~t2_st~0_16} AuxVars[] AssignedVars[] 546257#L579 [3793] L579-->L593: Formula: (> 0 v_~t3_st~0_18) InVars {~t3_st~0=v_~t3_st~0_18} OutVars{~t3_st~0=v_~t3_st~0_18} AuxVars[] AssignedVars[] 546253#L593 [3803] L593-->L607: Formula: (> 0 v_~t4_st~0_20) InVars {~t4_st~0=v_~t4_st~0_20} OutVars{~t4_st~0=v_~t4_st~0_20} AuxVars[] AssignedVars[] 546249#L607 [3815] L607-->L621: Formula: (< v_~t5_st~0_21 0) InVars {~t5_st~0=v_~t5_st~0_21} OutVars{~t5_st~0=v_~t5_st~0_21} AuxVars[] AssignedVars[] 546244#L621 [3829] L621-->L635: Formula: (< 0 v_~t6_st~0_21) InVars {~t6_st~0=v_~t6_st~0_21} OutVars{~t6_st~0=v_~t6_st~0_21} AuxVars[] AssignedVars[] 546243#L635 [2020-06-22 00:13:47,858 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:47,858 INFO L82 PathProgramCache]: Analyzing trace with hash -59005203, now seen corresponding path program 1 times [2020-06-22 00:13:47,858 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:47,858 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:47,859 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:47,859 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2020-06-22 00:13:47,859 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:47,861 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:47,871 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:47,871 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:47,871 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-06-22 00:13:47,872 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-06-22 00:13:47,872 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:47,872 INFO L82 PathProgramCache]: Analyzing trace with hash -1242974313, now seen corresponding path program 3 times [2020-06-22 00:13:47,872 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:47,872 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:47,873 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:47,873 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:47,873 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:47,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:13:47,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:13:47,954 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-06-22 00:13:47,954 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-06-22 00:13:47,954 INFO L87 Difference]: Start difference. First operand 51990 states and 76707 transitions. cyclomatic complexity: 24720 Second operand 3 states. [2020-06-22 00:13:48,414 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-06-22 00:13:48,414 INFO L93 Difference]: Finished difference Result 51921 states and 76619 transitions. [2020-06-22 00:13:48,415 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-06-22 00:13:48,416 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 51921 states and 76619 transitions. [2020-06-22 00:13:48,656 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 51848 [2020-06-22 00:13:48,811 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 51921 states to 51921 states and 76619 transitions. [2020-06-22 00:13:48,811 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 51921 [2020-06-22 00:13:48,850 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 51921 [2020-06-22 00:13:48,850 INFO L73 IsDeterministic]: Start isDeterministic. Operand 51921 states and 76619 transitions. [2020-06-22 00:13:48,886 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-06-22 00:13:48,886 INFO L706 BuchiCegarLoop]: Abstraction has 51921 states and 76619 transitions. [2020-06-22 00:13:48,910 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51921 states and 76619 transitions. [2020-06-22 00:13:49,315 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51921 to 51921. [2020-06-22 00:13:49,315 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 51921 states. [2020-06-22 00:13:49,417 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51921 states to 51921 states and 76619 transitions. [2020-06-22 00:13:49,417 INFO L729 BuchiCegarLoop]: Abstraction has 51921 states and 76619 transitions. [2020-06-22 00:13:49,417 INFO L609 BuchiCegarLoop]: Abstraction has 51921 states and 76619 transitions. [2020-06-22 00:13:49,417 INFO L442 BuchiCegarLoop]: ======== Iteration 46============ [2020-06-22 00:13:49,417 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51921 states and 76619 transitions. [2020-06-22 00:13:49,610 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 51848 [2020-06-22 00:13:49,611 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-06-22 00:13:49,611 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-06-22 00:13:49,611 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:49,612 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:49,613 INFO L794 eck$LassoCheckResult]: Stem: 634055#ULTIMATE.startENTRY [4266] ULTIMATE.startENTRY-->L444: Formula: (and (= 1 v_~t6_i~0_7) (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~M_E~0_37 2) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 0 v_~t6_pc~0_26) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_6~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= v_~T6_E~0_18 2) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~t6_st~0_24) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t6_pc~0=v_~t6_pc~0_26, ~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~T6_E~0=v_~T6_E~0_18, ~M_E~0=v_~M_E~0_37, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ~T4_E~0=v_~T4_E~0_18, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_4|, ~t6_i~0=v_~t6_i~0_7, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ULTIMATE.start_main_~__retres1~8=v_ULTIMATE.start_main_~__retres1~8_6, ~T2_E~0=v_~T2_E~0_18, ~t6_st~0=v_~t6_st~0_24, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_6~0=v_~E_6~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t6_pc~0, ~t5_i~0, ~t1_pc~0, ~t5_st~0, ~T6_E~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ~T4_E~0, ULTIMATE.start_start_simulation_#t~ret17, ~t6_i~0, ~t2_st~0, ~t2_pc~0, ULTIMATE.start_main_~__retres1~8, ~T2_E~0, ~t6_st~0, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_6~0, ULTIMATE.start_main_#res, ~E_2~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 633641#L444 [2453] L444-->L451-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 633642#L451-1 [3030] L451-1-->L456-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 633733#L456-1 [2574] L456-1-->L461-1: Formula: (and (= v_~t2_st~0_2 0) (= 1 v_~t2_i~0_3)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_2} AuxVars[] AssignedVars[~t2_st~0] 633734#L461-1 [2880] L461-1-->L466-1: Formula: (and (= v_~t3_st~0_3 0) (= v_~t3_i~0_3 1)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_3, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 633646#L466-1 [2457] L466-1-->L471-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 633647#L471-1 [3209] L471-1-->L476-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 633893#L476-1 [2761] L476-1-->L481-1: Formula: (and (= 1 v_~t6_i~0_3) (= v_~t6_st~0_4 0)) InVars {~t6_i~0=v_~t6_i~0_3} OutVars{~t6_st~0=v_~t6_st~0_4, ~t6_i~0=v_~t6_i~0_3} AuxVars[] AssignedVars[~t6_st~0] 633894#L481-1 [3652] L481-1-->L660-1: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 634070#L660-1 [3654] L660-1-->L665-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 633560#L665-1 [3655] L665-1-->L670-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 633561#L670-1 [3658] L670-1-->L675-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 633653#L675-1 [3659] L675-1-->L680-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 633654#L680-1 [3661] L680-1-->L685-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 633905#L685-1 [3663] L685-1-->L690-1: Formula: (< 0 v_~T6_E~0_4) InVars {~T6_E~0=v_~T6_E~0_4} OutVars{~T6_E~0=v_~T6_E~0_4} AuxVars[] AssignedVars[] 633906#L690-1 [3665] L690-1-->L695-1: Formula: (> v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 633774#L695-1 [3668] L695-1-->L700-1: Formula: (> v_~E_2~0_6 0) InVars {~E_2~0=v_~E_2~0_6} OutVars{~E_2~0=v_~E_2~0_6} AuxVars[] AssignedVars[] 633775#L700-1 [3670] L700-1-->L705-1: Formula: (> v_~E_3~0_6 0) InVars {~E_3~0=v_~E_3~0_6} OutVars{~E_3~0=v_~E_3~0_6} AuxVars[] AssignedVars[] 634039#L705-1 [3672] L705-1-->L710-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 633714#L710-1 [3674] L710-1-->L715-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 633715#L715-1 [3675] L715-1-->L720-1: Formula: (> v_~E_6~0_4 0) InVars {~E_6~0=v_~E_6~0_4} OutVars{~E_6~0=v_~E_6~0_4} AuxVars[] AssignedVars[] 633596#L720-1 [2412] L720-1-->L310: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_7, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_4|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_4|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_7, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_4, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_4, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_2|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_2|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_4|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_4|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_7, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_2|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_4} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 633597#L310 [3678] L310-->L310-2: Formula: (< v_~m_pc~0_5 1) InVars {~m_pc~0=v_~m_pc~0_5} OutVars{~m_pc~0=v_~m_pc~0_5} AuxVars[] AssignedVars[] 633747#L310-2 [2805] L310-2-->L321: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_11 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 633742#L321 [4267] L321-->L815: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 633743#L815 [2976] L815-->L815-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_12) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} AuxVars[] AssignedVars[] 634035#L815-2 [2961] L815-2-->L329: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 633961#L329 [3683] L329-->L329-2: Formula: (< v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 633962#L329-2 [2861] L329-2-->L340: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 633957#L340 [4268] L340-->L823: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 633958#L823 [3234] L823-->L823-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} AuxVars[] AssignedVars[] 634154#L823-2 [3235] L823-2-->L348: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_4|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 634124#L348 [3690] L348-->L348-2: Formula: (< v_~t2_pc~0_5 1) InVars {~t2_pc~0=v_~t2_pc~0_5} OutVars{~t2_pc~0=v_~t2_pc~0_5} AuxVars[] AssignedVars[] 634126#L348-2 [3153] L348-2-->L359: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 634122#L359 [4269] L359-->L831: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 633723#L831 [2537] L831-->L831-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} AuxVars[] AssignedVars[] 633709#L831-2 [2520] L831-2-->L367: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_4|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 633649#L367 [3695] L367-->L367-2: Formula: (> 1 v_~t3_pc~0_5) InVars {~t3_pc~0=v_~t3_pc~0_5} OutVars{~t3_pc~0=v_~t3_pc~0_5} AuxVars[] AssignedVars[] 633627#L367-2 [2438] L367-2-->L378: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 633628#L378 [4270] L378-->L839: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 633648#L839 [2791] L839-->L839-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} AuxVars[] AssignedVars[] 633919#L839-2 [2794] L839-2-->L386: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_7, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 633827#L386 [3702] L386-->L386-2: Formula: (< v_~t4_pc~0_5 1) InVars {~t4_pc~0=v_~t4_pc~0_5} OutVars{~t4_pc~0=v_~t4_pc~0_5} AuxVars[] AssignedVars[] 633828#L386-2 [2680] L386-2-->L397: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 633825#L397 [4271] L397-->L847: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 633826#L847 [3084] L847-->L847-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} AuxVars[] AssignedVars[] 634078#L847-2 [3064] L847-2-->L405: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_4|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 634079#L405 [3708] L405-->L405-2: Formula: (> 1 v_~t5_pc~0_5) InVars {~t5_pc~0=v_~t5_pc~0_5} OutVars{~t5_pc~0=v_~t5_pc~0_5} AuxVars[] AssignedVars[] 633992#L405-2 [2940] L405-2-->L416: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 634023#L416 [4272] L416-->L855: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 634089#L855 [3091] L855-->L855-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_12} AuxVars[] AssignedVars[] 634090#L855-2 [3093] L855-2-->L424: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_4|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 633692#L424 [3713] L424-->L424-2: Formula: (< v_~t6_pc~0_5 1) InVars {~t6_pc~0=v_~t6_pc~0_5} OutVars{~t6_pc~0=v_~t6_pc~0_5} AuxVars[] AssignedVars[] 633693#L424-2 [2503] L424-2-->L435: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 633689#L435 [4273] L435-->L863: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___5~0_49 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_28|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_28|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 633610#L863 [2425] L863-->L863-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___5~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} AuxVars[] AssignedVars[] 633583#L863-2 [3719] L863-2-->L733-1: Formula: (> v_~M_E~0_15 1) InVars {~M_E~0=v_~M_E~0_15} OutVars{~M_E~0=v_~M_E~0_15} AuxVars[] AssignedVars[] 633584#L733-1 [3722] L733-1-->L738-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 634037#L738-1 [3723] L738-1-->L743-1: Formula: (< 1 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 633712#L743-1 [3726] L743-1-->L748-1: Formula: (< 1 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 633713#L748-1 [3728] L748-1-->L753-1: Formula: (> v_~T4_E~0_10 1) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 633591#L753-1 [3729] L753-1-->L758-1: Formula: (< 1 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 633592#L758-1 [3731] L758-1-->L763-1: Formula: (> v_~T6_E~0_10 1) InVars {~T6_E~0=v_~T6_E~0_10} OutVars{~T6_E~0=v_~T6_E~0_10} AuxVars[] AssignedVars[] 633665#L763-1 [3733] L763-1-->L768-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 633666#L768-1 [3736] L768-1-->L773-1: Formula: (< 1 v_~E_2~0_14) InVars {~E_2~0=v_~E_2~0_14} OutVars{~E_2~0=v_~E_2~0_14} AuxVars[] AssignedVars[] 633896#L773-1 [3737] L773-1-->L778-1: Formula: (< 1 v_~E_3~0_14) InVars {~E_3~0=v_~E_3~0_14} OutVars{~E_3~0=v_~E_3~0_14} AuxVars[] AssignedVars[] 633897#L778-1 [3740] L778-1-->L783-1: Formula: (< 1 v_~E_4~0_14) InVars {~E_4~0=v_~E_4~0_14} OutVars{~E_4~0=v_~E_4~0_14} AuxVars[] AssignedVars[] 633766#L783-1 [3741] L783-1-->L788-1: Formula: (< 1 v_~E_5~0_14) InVars {~E_5~0=v_~E_5~0_14} OutVars{~E_5~0=v_~E_5~0_14} AuxVars[] AssignedVars[] 633767#L788-1 [3744] L788-1-->L1014-1: Formula: (< 1 v_~E_6~0_14) InVars {~E_6~0=v_~E_6~0_14} OutVars{~E_6~0=v_~E_6~0_14} AuxVars[] AssignedVars[] 634136#L1014-1 [4274] L1014-1-->L635: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp_ndt_7~0=v_ULTIMATE.start_eval_~tmp_ndt_7~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp_ndt_7~0] 652561#L635 [2020-06-22 00:13:49,613 INFO L796 eck$LassoCheckResult]: Loop: 652561#L635 [4275] L635-->L494: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_37} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 649328#L494 [2876] L494-->L531: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21 1) (= v_~m_st~0_8 0)) InVars {~m_st~0=v_~m_st~0_8} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21, ~m_st~0=v_~m_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 649327#L531 [4276] L531-->L546: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 649326#L546 [3757] L546-->L546-1: Formula: (> v_ULTIMATE.start_eval_~tmp~0_4 0) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} OutVars{ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} AuxVars[] AssignedVars[] 649323#L546-1 [3164] L546-1-->L554: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_2 |v_ULTIMATE.start_eval_#t~nondet1_3|) (= 0 v_~m_st~0_10)) InVars {~m_st~0=v_~m_st~0_10, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_3|} OutVars{ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_2|, ~m_st~0=v_~m_st~0_10, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_1~0] 649321#L554 [2472] L554-->L551: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} AuxVars[] AssignedVars[] 649319#L551 [2690] L551-->L568: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_2~0_2 |v_ULTIMATE.start_eval_#t~nondet2_3|) (= 0 v_~t1_st~0_11)) InVars {~t1_st~0=v_~t1_st~0_11, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_3|} OutVars{ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_2|, ~t1_st~0=v_~t1_st~0_11, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_2~0] 646688#L568 [3161] L568-->L565: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_2~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_5} AuxVars[] AssignedVars[] 646689#L565 [3782] L565-->L579: Formula: (< v_~t2_st~0_16 0) InVars {~t2_st~0=v_~t2_st~0_16} OutVars{~t2_st~0=v_~t2_st~0_16} AuxVars[] AssignedVars[] 648421#L579 [3793] L579-->L593: Formula: (> 0 v_~t3_st~0_18) InVars {~t3_st~0=v_~t3_st~0_18} OutVars{~t3_st~0=v_~t3_st~0_18} AuxVars[] AssignedVars[] 652577#L593 [3803] L593-->L607: Formula: (> 0 v_~t4_st~0_20) InVars {~t4_st~0=v_~t4_st~0_20} OutVars{~t4_st~0=v_~t4_st~0_20} AuxVars[] AssignedVars[] 652573#L607 [3815] L607-->L621: Formula: (< v_~t5_st~0_21 0) InVars {~t5_st~0=v_~t5_st~0_21} OutVars{~t5_st~0=v_~t5_st~0_21} AuxVars[] AssignedVars[] 652564#L621 [3829] L621-->L635: Formula: (< 0 v_~t6_st~0_21) InVars {~t6_st~0=v_~t6_st~0_21} OutVars{~t6_st~0=v_~t6_st~0_21} AuxVars[] AssignedVars[] 652561#L635 [2020-06-22 00:13:49,613 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:49,613 INFO L82 PathProgramCache]: Analyzing trace with hash 218945922, now seen corresponding path program 4 times [2020-06-22 00:13:49,613 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:49,614 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:49,614 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:49,614 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2020-06-22 00:13:49,614 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:49,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:13:49,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:13:49,631 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:49,631 INFO L82 PathProgramCache]: Analyzing trace with hash -1242050792, now seen corresponding path program 1 times [2020-06-22 00:13:49,631 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:49,631 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:49,632 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:49,632 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2020-06-22 00:13:49,632 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:49,634 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:13:49,635 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:13:49,636 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:49,637 INFO L82 PathProgramCache]: Analyzing trace with hash 219557687, now seen corresponding path program 1 times [2020-06-22 00:13:49,637 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:49,637 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:49,637 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:49,638 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:49,638 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:49,642 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:49,661 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:49,661 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:49,661 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-06-22 00:13:49,732 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-06-22 00:13:49,732 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-06-22 00:13:49,733 INFO L87 Difference]: Start difference. First operand 51921 states and 76619 transitions. cyclomatic complexity: 24701 Second operand 3 states. [2020-06-22 00:13:50,160 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-06-22 00:13:50,160 INFO L93 Difference]: Finished difference Result 46245 states and 68099 transitions. [2020-06-22 00:13:50,161 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-06-22 00:13:50,161 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 46245 states and 68099 transitions. [2020-06-22 00:13:50,589 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 46172 [2020-06-22 00:13:50,690 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 46245 states to 46245 states and 68099 transitions. [2020-06-22 00:13:50,690 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 46245 [2020-06-22 00:13:50,715 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 46245 [2020-06-22 00:13:50,716 INFO L73 IsDeterministic]: Start isDeterministic. Operand 46245 states and 68099 transitions. [2020-06-22 00:13:50,740 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-06-22 00:13:50,741 INFO L706 BuchiCegarLoop]: Abstraction has 46245 states and 68099 transitions. [2020-06-22 00:13:50,758 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46245 states and 68099 transitions. [2020-06-22 00:13:51,092 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46245 to 46245. [2020-06-22 00:13:51,092 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 46245 states. [2020-06-22 00:13:51,175 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46245 states to 46245 states and 68099 transitions. [2020-06-22 00:13:51,175 INFO L729 BuchiCegarLoop]: Abstraction has 46245 states and 68099 transitions. [2020-06-22 00:13:51,175 INFO L609 BuchiCegarLoop]: Abstraction has 46245 states and 68099 transitions. [2020-06-22 00:13:51,175 INFO L442 BuchiCegarLoop]: ======== Iteration 47============ [2020-06-22 00:13:51,176 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 46245 states and 68099 transitions. [2020-06-22 00:13:51,340 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 46172 [2020-06-22 00:13:51,341 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-06-22 00:13:51,341 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-06-22 00:13:51,341 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:51,342 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:51,343 INFO L794 eck$LassoCheckResult]: Stem: 732226#ULTIMATE.startENTRY [4266] ULTIMATE.startENTRY-->L444: Formula: (and (= 1 v_~t6_i~0_7) (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~M_E~0_37 2) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 0 v_~t6_pc~0_26) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_6~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= v_~T6_E~0_18 2) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~t6_st~0_24) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t6_pc~0=v_~t6_pc~0_26, ~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~T6_E~0=v_~T6_E~0_18, ~M_E~0=v_~M_E~0_37, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ~T4_E~0=v_~T4_E~0_18, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_4|, ~t6_i~0=v_~t6_i~0_7, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ULTIMATE.start_main_~__retres1~8=v_ULTIMATE.start_main_~__retres1~8_6, ~T2_E~0=v_~T2_E~0_18, ~t6_st~0=v_~t6_st~0_24, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_6~0=v_~E_6~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t6_pc~0, ~t5_i~0, ~t1_pc~0, ~t5_st~0, ~T6_E~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ~T4_E~0, ULTIMATE.start_start_simulation_#t~ret17, ~t6_i~0, ~t2_st~0, ~t2_pc~0, ULTIMATE.start_main_~__retres1~8, ~T2_E~0, ~t6_st~0, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_6~0, ULTIMATE.start_main_#res, ~E_2~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 731816#L444 [2453] L444-->L451-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 731817#L451-1 [3030] L451-1-->L456-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 731905#L456-1 [2574] L456-1-->L461-1: Formula: (and (= v_~t2_st~0_2 0) (= 1 v_~t2_i~0_3)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_2} AuxVars[] AssignedVars[~t2_st~0] 731906#L461-1 [2880] L461-1-->L466-1: Formula: (and (= v_~t3_st~0_3 0) (= v_~t3_i~0_3 1)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_3, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 731821#L466-1 [2457] L466-1-->L471-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 731822#L471-1 [3209] L471-1-->L476-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 732063#L476-1 [2761] L476-1-->L481-1: Formula: (and (= 1 v_~t6_i~0_3) (= v_~t6_st~0_4 0)) InVars {~t6_i~0=v_~t6_i~0_3} OutVars{~t6_st~0=v_~t6_st~0_4, ~t6_i~0=v_~t6_i~0_3} AuxVars[] AssignedVars[~t6_st~0] 732064#L481-1 [3652] L481-1-->L660-1: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 732244#L660-1 [3654] L660-1-->L665-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 731736#L665-1 [3655] L665-1-->L670-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 731737#L670-1 [3658] L670-1-->L675-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 731828#L675-1 [3659] L675-1-->L680-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 731829#L680-1 [3661] L680-1-->L685-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 732075#L685-1 [3663] L685-1-->L690-1: Formula: (< 0 v_~T6_E~0_4) InVars {~T6_E~0=v_~T6_E~0_4} OutVars{~T6_E~0=v_~T6_E~0_4} AuxVars[] AssignedVars[] 732076#L690-1 [3665] L690-1-->L695-1: Formula: (> v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 731945#L695-1 [3668] L695-1-->L700-1: Formula: (> v_~E_2~0_6 0) InVars {~E_2~0=v_~E_2~0_6} OutVars{~E_2~0=v_~E_2~0_6} AuxVars[] AssignedVars[] 731946#L700-1 [3670] L700-1-->L705-1: Formula: (> v_~E_3~0_6 0) InVars {~E_3~0=v_~E_3~0_6} OutVars{~E_3~0=v_~E_3~0_6} AuxVars[] AssignedVars[] 732210#L705-1 [3672] L705-1-->L710-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 731887#L710-1 [3674] L710-1-->L715-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 731888#L715-1 [3675] L715-1-->L720-1: Formula: (> v_~E_6~0_4 0) InVars {~E_6~0=v_~E_6~0_4} OutVars{~E_6~0=v_~E_6~0_4} AuxVars[] AssignedVars[] 731771#L720-1 [2412] L720-1-->L310: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_7, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_4|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_4|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_7, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_4, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_4, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_2|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_2|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_4|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_4|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_7, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_2|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_4} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 731772#L310 [3678] L310-->L310-2: Formula: (< v_~m_pc~0_5 1) InVars {~m_pc~0=v_~m_pc~0_5} OutVars{~m_pc~0=v_~m_pc~0_5} AuxVars[] AssignedVars[] 731918#L310-2 [2805] L310-2-->L321: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_11 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 731916#L321 [4267] L321-->L815: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 731917#L815 [2976] L815-->L815-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_12) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} AuxVars[] AssignedVars[] 732206#L815-2 [2961] L815-2-->L329: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 732130#L329 [3683] L329-->L329-2: Formula: (< v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 732131#L329-2 [2861] L329-2-->L340: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 732128#L340 [4268] L340-->L823: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 732129#L823 [3234] L823-->L823-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} AuxVars[] AssignedVars[] 732340#L823-2 [3235] L823-2-->L348: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_4|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 732303#L348 [3690] L348-->L348-2: Formula: (< v_~t2_pc~0_5 1) InVars {~t2_pc~0=v_~t2_pc~0_5} OutVars{~t2_pc~0=v_~t2_pc~0_5} AuxVars[] AssignedVars[] 732305#L348-2 [3153] L348-2-->L359: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 732302#L359 [4269] L359-->L831: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 731895#L831 [2537] L831-->L831-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} AuxVars[] AssignedVars[] 731882#L831-2 [2520] L831-2-->L367: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_4|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 731824#L367 [3695] L367-->L367-2: Formula: (> 1 v_~t3_pc~0_5) InVars {~t3_pc~0=v_~t3_pc~0_5} OutVars{~t3_pc~0=v_~t3_pc~0_5} AuxVars[] AssignedVars[] 731801#L367-2 [2438] L367-2-->L378: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 731802#L378 [4270] L378-->L839: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 731823#L839 [2791] L839-->L839-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} AuxVars[] AssignedVars[] 732090#L839-2 [2794] L839-2-->L386: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_7, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 731995#L386 [3702] L386-->L386-2: Formula: (< v_~t4_pc~0_5 1) InVars {~t4_pc~0=v_~t4_pc~0_5} OutVars{~t4_pc~0=v_~t4_pc~0_5} AuxVars[] AssignedVars[] 731996#L386-2 [2680] L386-2-->L397: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 731993#L397 [4271] L397-->L847: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 731994#L847 [3084] L847-->L847-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} AuxVars[] AssignedVars[] 732251#L847-2 [3064] L847-2-->L405: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_4|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 732252#L405 [3708] L405-->L405-2: Formula: (> 1 v_~t5_pc~0_5) InVars {~t5_pc~0=v_~t5_pc~0_5} OutVars{~t5_pc~0=v_~t5_pc~0_5} AuxVars[] AssignedVars[] 732157#L405-2 [2940] L405-2-->L416: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 732194#L416 [4272] L416-->L855: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 732265#L855 [3091] L855-->L855-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_12} AuxVars[] AssignedVars[] 732266#L855-2 [3093] L855-2-->L424: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_4|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 731867#L424 [3713] L424-->L424-2: Formula: (< v_~t6_pc~0_5 1) InVars {~t6_pc~0=v_~t6_pc~0_5} OutVars{~t6_pc~0=v_~t6_pc~0_5} AuxVars[] AssignedVars[] 731868#L424-2 [2503] L424-2-->L435: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 731866#L435 [4273] L435-->L863: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___5~0_49 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_28|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_28|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 731787#L863 [2425] L863-->L863-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___5~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} AuxVars[] AssignedVars[] 731760#L863-2 [3719] L863-2-->L733-1: Formula: (> v_~M_E~0_15 1) InVars {~M_E~0=v_~M_E~0_15} OutVars{~M_E~0=v_~M_E~0_15} AuxVars[] AssignedVars[] 731761#L733-1 [3722] L733-1-->L738-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 732208#L738-1 [3723] L738-1-->L743-1: Formula: (< 1 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 731885#L743-1 [3726] L743-1-->L748-1: Formula: (< 1 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 731886#L748-1 [3728] L748-1-->L753-1: Formula: (> v_~T4_E~0_10 1) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 731765#L753-1 [3729] L753-1-->L758-1: Formula: (< 1 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 731766#L758-1 [3731] L758-1-->L763-1: Formula: (> v_~T6_E~0_10 1) InVars {~T6_E~0=v_~T6_E~0_10} OutVars{~T6_E~0=v_~T6_E~0_10} AuxVars[] AssignedVars[] 731839#L763-1 [3733] L763-1-->L768-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 731840#L768-1 [3736] L768-1-->L773-1: Formula: (< 1 v_~E_2~0_14) InVars {~E_2~0=v_~E_2~0_14} OutVars{~E_2~0=v_~E_2~0_14} AuxVars[] AssignedVars[] 732068#L773-1 [3737] L773-1-->L778-1: Formula: (< 1 v_~E_3~0_14) InVars {~E_3~0=v_~E_3~0_14} OutVars{~E_3~0=v_~E_3~0_14} AuxVars[] AssignedVars[] 732069#L778-1 [3740] L778-1-->L783-1: Formula: (< 1 v_~E_4~0_14) InVars {~E_4~0=v_~E_4~0_14} OutVars{~E_4~0=v_~E_4~0_14} AuxVars[] AssignedVars[] 731939#L783-1 [3741] L783-1-->L788-1: Formula: (< 1 v_~E_5~0_14) InVars {~E_5~0=v_~E_5~0_14} OutVars{~E_5~0=v_~E_5~0_14} AuxVars[] AssignedVars[] 731940#L788-1 [3744] L788-1-->L1014-1: Formula: (< 1 v_~E_6~0_14) InVars {~E_6~0=v_~E_6~0_14} OutVars{~E_6~0=v_~E_6~0_14} AuxVars[] AssignedVars[] 732324#L1014-1 [4274] L1014-1-->L635: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp_ndt_7~0=v_ULTIMATE.start_eval_~tmp_ndt_7~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp_ndt_7~0] 748943#L635 [2020-06-22 00:13:51,343 INFO L796 eck$LassoCheckResult]: Loop: 748943#L635 [4275] L635-->L494: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_37} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 748937#L494 [2876] L494-->L531: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21 1) (= v_~m_st~0_8 0)) InVars {~m_st~0=v_~m_st~0_8} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21, ~m_st~0=v_~m_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 748935#L531 [4276] L531-->L546: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 748933#L546 [3757] L546-->L546-1: Formula: (> v_ULTIMATE.start_eval_~tmp~0_4 0) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} OutVars{ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} AuxVars[] AssignedVars[] 748927#L546-1 [3164] L546-1-->L554: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_2 |v_ULTIMATE.start_eval_#t~nondet1_3|) (= 0 v_~m_st~0_10)) InVars {~m_st~0=v_~m_st~0_10, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_3|} OutVars{ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_2|, ~m_st~0=v_~m_st~0_10, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_1~0] 748924#L554 [2472] L554-->L551: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} AuxVars[] AssignedVars[] 742210#L551 [2690] L551-->L568: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_2~0_2 |v_ULTIMATE.start_eval_#t~nondet2_3|) (= 0 v_~t1_st~0_11)) InVars {~t1_st~0=v_~t1_st~0_11, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_3|} OutVars{ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_2|, ~t1_st~0=v_~t1_st~0_11, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_2~0] 742207#L568 [3161] L568-->L565: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_2~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_5} AuxVars[] AssignedVars[] 742208#L565 [2469] L565-->L582: Formula: (and (= v_~t2_st~0_12 0) (= v_ULTIMATE.start_eval_~tmp_ndt_3~0_2 |v_ULTIMATE.start_eval_#t~nondet3_3|)) InVars {ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_3|, ~t2_st~0=v_~t2_st~0_12} OutVars{ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_2|, ~t2_st~0=v_~t2_st~0_12, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_~tmp_ndt_3~0] 745135#L582 [2901] L582-->L579: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_3~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_5} AuxVars[] AssignedVars[] 745129#L579 [3793] L579-->L593: Formula: (> 0 v_~t3_st~0_18) InVars {~t3_st~0=v_~t3_st~0_18} OutVars{~t3_st~0=v_~t3_st~0_18} AuxVars[] AssignedVars[] 745123#L593 [3803] L593-->L607: Formula: (> 0 v_~t4_st~0_20) InVars {~t4_st~0=v_~t4_st~0_20} OutVars{~t4_st~0=v_~t4_st~0_20} AuxVars[] AssignedVars[] 745117#L607 [3815] L607-->L621: Formula: (< v_~t5_st~0_21 0) InVars {~t5_st~0=v_~t5_st~0_21} OutVars{~t5_st~0=v_~t5_st~0_21} AuxVars[] AssignedVars[] 748945#L621 [3829] L621-->L635: Formula: (< 0 v_~t6_st~0_21) InVars {~t6_st~0=v_~t6_st~0_21} OutVars{~t6_st~0=v_~t6_st~0_21} AuxVars[] AssignedVars[] 748943#L635 [2020-06-22 00:13:51,343 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:51,343 INFO L82 PathProgramCache]: Analyzing trace with hash 218945922, now seen corresponding path program 5 times [2020-06-22 00:13:51,343 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:51,344 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:51,344 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:51,344 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:51,344 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:51,348 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:13:51,352 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:13:51,361 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:51,361 INFO L82 PathProgramCache]: Analyzing trace with hash 391674734, now seen corresponding path program 1 times [2020-06-22 00:13:51,361 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:51,361 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:51,362 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:51,362 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2020-06-22 00:13:51,362 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:51,364 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:13:51,365 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:13:51,366 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:51,367 INFO L82 PathProgramCache]: Analyzing trace with hash -1543102673, now seen corresponding path program 1 times [2020-06-22 00:13:51,367 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:51,367 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:51,367 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:51,368 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:51,368 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:51,372 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:51,391 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:51,391 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:51,391 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-06-22 00:13:51,471 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-06-22 00:13:51,471 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-06-22 00:13:51,471 INFO L87 Difference]: Start difference. First operand 46245 states and 68099 transitions. cyclomatic complexity: 21857 Second operand 3 states. [2020-06-22 00:13:51,898 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-06-22 00:13:51,899 INFO L93 Difference]: Finished difference Result 46245 states and 67811 transitions. [2020-06-22 00:13:51,899 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-06-22 00:13:51,899 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 46245 states and 67811 transitions. [2020-06-22 00:13:52,092 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 46172 [2020-06-22 00:13:52,216 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 46245 states to 46245 states and 67811 transitions. [2020-06-22 00:13:52,216 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 46245 [2020-06-22 00:13:52,250 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 46245 [2020-06-22 00:13:52,250 INFO L73 IsDeterministic]: Start isDeterministic. Operand 46245 states and 67811 transitions. [2020-06-22 00:13:52,281 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-06-22 00:13:52,282 INFO L706 BuchiCegarLoop]: Abstraction has 46245 states and 67811 transitions. [2020-06-22 00:13:52,303 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46245 states and 67811 transitions. [2020-06-22 00:13:52,636 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46245 to 46245. [2020-06-22 00:13:52,636 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 46245 states. [2020-06-22 00:13:52,718 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46245 states to 46245 states and 67811 transitions. [2020-06-22 00:13:52,718 INFO L729 BuchiCegarLoop]: Abstraction has 46245 states and 67811 transitions. [2020-06-22 00:13:52,718 INFO L609 BuchiCegarLoop]: Abstraction has 46245 states and 67811 transitions. [2020-06-22 00:13:52,718 INFO L442 BuchiCegarLoop]: ======== Iteration 48============ [2020-06-22 00:13:52,718 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 46245 states and 67811 transitions. [2020-06-22 00:13:52,880 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 46172 [2020-06-22 00:13:52,881 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-06-22 00:13:52,881 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-06-22 00:13:52,882 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:52,882 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:52,883 INFO L794 eck$LassoCheckResult]: Stem: 824717#ULTIMATE.startENTRY [4266] ULTIMATE.startENTRY-->L444: Formula: (and (= 1 v_~t6_i~0_7) (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~M_E~0_37 2) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 0 v_~t6_pc~0_26) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_6~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= v_~T6_E~0_18 2) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~t6_st~0_24) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t6_pc~0=v_~t6_pc~0_26, ~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~T6_E~0=v_~T6_E~0_18, ~M_E~0=v_~M_E~0_37, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ~T4_E~0=v_~T4_E~0_18, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_4|, ~t6_i~0=v_~t6_i~0_7, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ULTIMATE.start_main_~__retres1~8=v_ULTIMATE.start_main_~__retres1~8_6, ~T2_E~0=v_~T2_E~0_18, ~t6_st~0=v_~t6_st~0_24, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_6~0=v_~E_6~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t6_pc~0, ~t5_i~0, ~t1_pc~0, ~t5_st~0, ~T6_E~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ~T4_E~0, ULTIMATE.start_start_simulation_#t~ret17, ~t6_i~0, ~t2_st~0, ~t2_pc~0, ULTIMATE.start_main_~__retres1~8, ~T2_E~0, ~t6_st~0, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_6~0, ULTIMATE.start_main_#res, ~E_2~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 824316#L444 [2453] L444-->L451-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 824317#L451-1 [3030] L451-1-->L456-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 824407#L456-1 [2574] L456-1-->L461-1: Formula: (and (= v_~t2_st~0_2 0) (= 1 v_~t2_i~0_3)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_2} AuxVars[] AssignedVars[~t2_st~0] 824408#L461-1 [2880] L461-1-->L466-1: Formula: (and (= v_~t3_st~0_3 0) (= v_~t3_i~0_3 1)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_3, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 824318#L466-1 [2457] L466-1-->L471-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 824319#L471-1 [3209] L471-1-->L476-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 824557#L476-1 [2761] L476-1-->L481-1: Formula: (and (= 1 v_~t6_i~0_3) (= v_~t6_st~0_4 0)) InVars {~t6_i~0=v_~t6_i~0_3} OutVars{~t6_st~0=v_~t6_st~0_4, ~t6_i~0=v_~t6_i~0_3} AuxVars[] AssignedVars[~t6_st~0] 824558#L481-1 [3652] L481-1-->L660-1: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 824733#L660-1 [3654] L660-1-->L665-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 824234#L665-1 [3655] L665-1-->L670-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 824235#L670-1 [3658] L670-1-->L675-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 824325#L675-1 [3659] L675-1-->L680-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 824326#L680-1 [3661] L680-1-->L685-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 824569#L685-1 [3663] L685-1-->L690-1: Formula: (< 0 v_~T6_E~0_4) InVars {~T6_E~0=v_~T6_E~0_4} OutVars{~T6_E~0=v_~T6_E~0_4} AuxVars[] AssignedVars[] 824570#L690-1 [3665] L690-1-->L695-1: Formula: (> v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 824447#L695-1 [3668] L695-1-->L700-1: Formula: (> v_~E_2~0_6 0) InVars {~E_2~0=v_~E_2~0_6} OutVars{~E_2~0=v_~E_2~0_6} AuxVars[] AssignedVars[] 824448#L700-1 [3670] L700-1-->L705-1: Formula: (> v_~E_3~0_6 0) InVars {~E_3~0=v_~E_3~0_6} OutVars{~E_3~0=v_~E_3~0_6} AuxVars[] AssignedVars[] 824700#L705-1 [3672] L705-1-->L710-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 824387#L710-1 [3674] L710-1-->L715-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 824388#L715-1 [3675] L715-1-->L720-1: Formula: (> v_~E_6~0_4 0) InVars {~E_6~0=v_~E_6~0_4} OutVars{~E_6~0=v_~E_6~0_4} AuxVars[] AssignedVars[] 824269#L720-1 [2412] L720-1-->L310: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_7, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_4|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_4|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_7, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_4, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_4, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_2|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_2|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_4|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_4|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_7, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_2|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_4} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 824270#L310 [3678] L310-->L310-2: Formula: (< v_~m_pc~0_5 1) InVars {~m_pc~0=v_~m_pc~0_5} OutVars{~m_pc~0=v_~m_pc~0_5} AuxVars[] AssignedVars[] 824420#L310-2 [2805] L310-2-->L321: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_11 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 824418#L321 [4267] L321-->L815: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 824419#L815 [2976] L815-->L815-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_12) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} AuxVars[] AssignedVars[] 824696#L815-2 [2961] L815-2-->L329: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 824624#L329 [3683] L329-->L329-2: Formula: (< v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 824625#L329-2 [2861] L329-2-->L340: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 824622#L340 [4268] L340-->L823: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 824623#L823 [3234] L823-->L823-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} AuxVars[] AssignedVars[] 824830#L823-2 [3235] L823-2-->L348: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_4|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 824796#L348 [3690] L348-->L348-2: Formula: (< v_~t2_pc~0_5 1) InVars {~t2_pc~0=v_~t2_pc~0_5} OutVars{~t2_pc~0=v_~t2_pc~0_5} AuxVars[] AssignedVars[] 824798#L348-2 [3153] L348-2-->L359: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 824795#L359 [4269] L359-->L831: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 824397#L831 [2537] L831-->L831-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} AuxVars[] AssignedVars[] 824382#L831-2 [2520] L831-2-->L367: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_4|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 824321#L367 [3695] L367-->L367-2: Formula: (> 1 v_~t3_pc~0_5) InVars {~t3_pc~0=v_~t3_pc~0_5} OutVars{~t3_pc~0=v_~t3_pc~0_5} AuxVars[] AssignedVars[] 824298#L367-2 [2438] L367-2-->L378: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 824299#L378 [4270] L378-->L839: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 824320#L839 [2791] L839-->L839-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} AuxVars[] AssignedVars[] 824582#L839-2 [2794] L839-2-->L386: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_7, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 824494#L386 [3702] L386-->L386-2: Formula: (< v_~t4_pc~0_5 1) InVars {~t4_pc~0=v_~t4_pc~0_5} OutVars{~t4_pc~0=v_~t4_pc~0_5} AuxVars[] AssignedVars[] 824495#L386-2 [2680] L386-2-->L397: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 824492#L397 [4271] L397-->L847: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 824493#L847 [3084] L847-->L847-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} AuxVars[] AssignedVars[] 824741#L847-2 [3064] L847-2-->L405: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_4|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 824742#L405 [3708] L405-->L405-2: Formula: (> 1 v_~t5_pc~0_5) InVars {~t5_pc~0=v_~t5_pc~0_5} OutVars{~t5_pc~0=v_~t5_pc~0_5} AuxVars[] AssignedVars[] 824653#L405-2 [2940] L405-2-->L416: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 824685#L416 [4272] L416-->L855: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 824755#L855 [3091] L855-->L855-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_12} AuxVars[] AssignedVars[] 824756#L855-2 [3093] L855-2-->L424: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_4|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 824365#L424 [3713] L424-->L424-2: Formula: (< v_~t6_pc~0_5 1) InVars {~t6_pc~0=v_~t6_pc~0_5} OutVars{~t6_pc~0=v_~t6_pc~0_5} AuxVars[] AssignedVars[] 824366#L424-2 [2503] L424-2-->L435: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 824364#L435 [4273] L435-->L863: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___5~0_49 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_28|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_28|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 824285#L863 [2425] L863-->L863-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___5~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} AuxVars[] AssignedVars[] 824258#L863-2 [3719] L863-2-->L733-1: Formula: (> v_~M_E~0_15 1) InVars {~M_E~0=v_~M_E~0_15} OutVars{~M_E~0=v_~M_E~0_15} AuxVars[] AssignedVars[] 824259#L733-1 [3722] L733-1-->L738-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 824698#L738-1 [3723] L738-1-->L743-1: Formula: (< 1 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 824385#L743-1 [3726] L743-1-->L748-1: Formula: (< 1 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 824386#L748-1 [3728] L748-1-->L753-1: Formula: (> v_~T4_E~0_10 1) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 824264#L753-1 [3729] L753-1-->L758-1: Formula: (< 1 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 824265#L758-1 [3731] L758-1-->L763-1: Formula: (> v_~T6_E~0_10 1) InVars {~T6_E~0=v_~T6_E~0_10} OutVars{~T6_E~0=v_~T6_E~0_10} AuxVars[] AssignedVars[] 824336#L763-1 [3733] L763-1-->L768-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 824337#L768-1 [3736] L768-1-->L773-1: Formula: (< 1 v_~E_2~0_14) InVars {~E_2~0=v_~E_2~0_14} OutVars{~E_2~0=v_~E_2~0_14} AuxVars[] AssignedVars[] 824563#L773-1 [3737] L773-1-->L778-1: Formula: (< 1 v_~E_3~0_14) InVars {~E_3~0=v_~E_3~0_14} OutVars{~E_3~0=v_~E_3~0_14} AuxVars[] AssignedVars[] 824564#L778-1 [3740] L778-1-->L783-1: Formula: (< 1 v_~E_4~0_14) InVars {~E_4~0=v_~E_4~0_14} OutVars{~E_4~0=v_~E_4~0_14} AuxVars[] AssignedVars[] 824441#L783-1 [3741] L783-1-->L788-1: Formula: (< 1 v_~E_5~0_14) InVars {~E_5~0=v_~E_5~0_14} OutVars{~E_5~0=v_~E_5~0_14} AuxVars[] AssignedVars[] 824442#L788-1 [3744] L788-1-->L1014-1: Formula: (< 1 v_~E_6~0_14) InVars {~E_6~0=v_~E_6~0_14} OutVars{~E_6~0=v_~E_6~0_14} AuxVars[] AssignedVars[] 824816#L1014-1 [4274] L1014-1-->L635: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp_ndt_7~0=v_ULTIMATE.start_eval_~tmp_ndt_7~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp_ndt_7~0] 839136#L635 [2020-06-22 00:13:52,883 INFO L796 eck$LassoCheckResult]: Loop: 839136#L635 [4275] L635-->L494: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_37} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 839131#L494 [2876] L494-->L531: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21 1) (= v_~m_st~0_8 0)) InVars {~m_st~0=v_~m_st~0_8} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21, ~m_st~0=v_~m_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 839129#L531 [4276] L531-->L546: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 839127#L546 [3757] L546-->L546-1: Formula: (> v_ULTIMATE.start_eval_~tmp~0_4 0) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} OutVars{ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} AuxVars[] AssignedVars[] 839123#L546-1 [3164] L546-1-->L554: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_2 |v_ULTIMATE.start_eval_#t~nondet1_3|) (= 0 v_~m_st~0_10)) InVars {~m_st~0=v_~m_st~0_10, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_3|} OutVars{ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_2|, ~m_st~0=v_~m_st~0_10, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_1~0] 839120#L554 [2472] L554-->L551: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} AuxVars[] AssignedVars[] 835921#L551 [2690] L551-->L568: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_2~0_2 |v_ULTIMATE.start_eval_#t~nondet2_3|) (= 0 v_~t1_st~0_11)) InVars {~t1_st~0=v_~t1_st~0_11, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_3|} OutVars{ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_2|, ~t1_st~0=v_~t1_st~0_11, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_2~0] 835916#L568 [3161] L568-->L565: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_2~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_5} AuxVars[] AssignedVars[] 835917#L565 [2469] L565-->L582: Formula: (and (= v_~t2_st~0_12 0) (= v_ULTIMATE.start_eval_~tmp_ndt_3~0_2 |v_ULTIMATE.start_eval_#t~nondet3_3|)) InVars {ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_3|, ~t2_st~0=v_~t2_st~0_12} OutVars{ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_2|, ~t2_st~0=v_~t2_st~0_12, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_~tmp_ndt_3~0] 839832#L582 [2901] L582-->L579: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_3~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_5} AuxVars[] AssignedVars[] 839152#L579 [3794] L579-->L593: Formula: (< 0 v_~t3_st~0_18) InVars {~t3_st~0=v_~t3_st~0_18} OutVars{~t3_st~0=v_~t3_st~0_18} AuxVars[] AssignedVars[] 839149#L593 [3803] L593-->L607: Formula: (> 0 v_~t4_st~0_20) InVars {~t4_st~0=v_~t4_st~0_20} OutVars{~t4_st~0=v_~t4_st~0_20} AuxVars[] AssignedVars[] 839145#L607 [3815] L607-->L621: Formula: (< v_~t5_st~0_21 0) InVars {~t5_st~0=v_~t5_st~0_21} OutVars{~t5_st~0=v_~t5_st~0_21} AuxVars[] AssignedVars[] 839137#L621 [3829] L621-->L635: Formula: (< 0 v_~t6_st~0_21) InVars {~t6_st~0=v_~t6_st~0_21} OutVars{~t6_st~0=v_~t6_st~0_21} AuxVars[] AssignedVars[] 839136#L635 [2020-06-22 00:13:52,883 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:52,883 INFO L82 PathProgramCache]: Analyzing trace with hash 218945922, now seen corresponding path program 6 times [2020-06-22 00:13:52,883 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:52,884 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:52,884 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:52,884 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:52,884 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:52,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:13:52,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:13:52,900 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:52,900 INFO L82 PathProgramCache]: Analyzing trace with hash 391704525, now seen corresponding path program 1 times [2020-06-22 00:13:52,901 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:52,901 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:52,901 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:52,901 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2020-06-22 00:13:52,902 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:52,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:13:52,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:13:52,906 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:52,906 INFO L82 PathProgramCache]: Analyzing trace with hash -1543072882, now seen corresponding path program 1 times [2020-06-22 00:13:52,906 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:52,906 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:52,907 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:52,907 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:52,907 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:52,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:52,930 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:52,930 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:52,930 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-06-22 00:13:53,026 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-06-22 00:13:53,026 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-06-22 00:13:53,026 INFO L87 Difference]: Start difference. First operand 46245 states and 67811 transitions. cyclomatic complexity: 21569 Second operand 3 states. [2020-06-22 00:13:53,981 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-06-22 00:13:53,982 INFO L93 Difference]: Finished difference Result 75049 states and 110923 transitions. [2020-06-22 00:13:54,004 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-06-22 00:13:54,004 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 75049 states and 110923 transitions. [2020-06-22 00:13:54,328 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 74976 [2020-06-22 00:13:54,525 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 75049 states to 75049 states and 110923 transitions. [2020-06-22 00:13:54,526 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 75049 [2020-06-22 00:13:54,574 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 75049 [2020-06-22 00:13:54,575 INFO L73 IsDeterministic]: Start isDeterministic. Operand 75049 states and 110923 transitions. [2020-06-22 00:13:54,619 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-06-22 00:13:54,619 INFO L706 BuchiCegarLoop]: Abstraction has 75049 states and 110923 transitions. [2020-06-22 00:13:54,654 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 75049 states and 110923 transitions. [2020-06-22 00:13:55,210 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 75049 to 75049. [2020-06-22 00:13:55,211 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 75049 states. [2020-06-22 00:13:55,351 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 75049 states to 75049 states and 110923 transitions. [2020-06-22 00:13:55,352 INFO L729 BuchiCegarLoop]: Abstraction has 75049 states and 110923 transitions. [2020-06-22 00:13:55,352 INFO L609 BuchiCegarLoop]: Abstraction has 75049 states and 110923 transitions. [2020-06-22 00:13:55,352 INFO L442 BuchiCegarLoop]: ======== Iteration 49============ [2020-06-22 00:13:55,352 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 75049 states and 110923 transitions. [2020-06-22 00:13:55,635 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 74976 [2020-06-22 00:13:55,636 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-06-22 00:13:55,636 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-06-22 00:13:55,636 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:55,637 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:55,637 INFO L794 eck$LassoCheckResult]: Stem: 946028#ULTIMATE.startENTRY [4266] ULTIMATE.startENTRY-->L444: Formula: (and (= 1 v_~t6_i~0_7) (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~M_E~0_37 2) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 0 v_~t6_pc~0_26) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_6~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= v_~T6_E~0_18 2) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~t6_st~0_24) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t6_pc~0=v_~t6_pc~0_26, ~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~T6_E~0=v_~T6_E~0_18, ~M_E~0=v_~M_E~0_37, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ~T4_E~0=v_~T4_E~0_18, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_4|, ~t6_i~0=v_~t6_i~0_7, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ULTIMATE.start_main_~__retres1~8=v_ULTIMATE.start_main_~__retres1~8_6, ~T2_E~0=v_~T2_E~0_18, ~t6_st~0=v_~t6_st~0_24, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_6~0=v_~E_6~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t6_pc~0, ~t5_i~0, ~t1_pc~0, ~t5_st~0, ~T6_E~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ~T4_E~0, ULTIMATE.start_start_simulation_#t~ret17, ~t6_i~0, ~t2_st~0, ~t2_pc~0, ULTIMATE.start_main_~__retres1~8, ~T2_E~0, ~t6_st~0, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_6~0, ULTIMATE.start_main_#res, ~E_2~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 945621#L444 [2453] L444-->L451-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 945622#L451-1 [3030] L451-1-->L456-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 945705#L456-1 [2574] L456-1-->L461-1: Formula: (and (= v_~t2_st~0_2 0) (= 1 v_~t2_i~0_3)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_2} AuxVars[] AssignedVars[~t2_st~0] 945706#L461-1 [2880] L461-1-->L466-1: Formula: (and (= v_~t3_st~0_3 0) (= v_~t3_i~0_3 1)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_3, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 945623#L466-1 [2457] L466-1-->L471-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 945624#L471-1 [3209] L471-1-->L476-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 945860#L476-1 [2761] L476-1-->L481-1: Formula: (and (= 1 v_~t6_i~0_3) (= v_~t6_st~0_4 0)) InVars {~t6_i~0=v_~t6_i~0_3} OutVars{~t6_st~0=v_~t6_st~0_4, ~t6_i~0=v_~t6_i~0_3} AuxVars[] AssignedVars[~t6_st~0] 945861#L481-1 [3652] L481-1-->L660-1: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 946047#L660-1 [3654] L660-1-->L665-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 945536#L665-1 [3655] L665-1-->L670-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 945537#L670-1 [3658] L670-1-->L675-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 945630#L675-1 [3659] L675-1-->L680-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 945631#L680-1 [3661] L680-1-->L685-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 945873#L685-1 [3663] L685-1-->L690-1: Formula: (< 0 v_~T6_E~0_4) InVars {~T6_E~0=v_~T6_E~0_4} OutVars{~T6_E~0=v_~T6_E~0_4} AuxVars[] AssignedVars[] 945874#L690-1 [3665] L690-1-->L695-1: Formula: (> v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 945746#L695-1 [3668] L695-1-->L700-1: Formula: (> v_~E_2~0_6 0) InVars {~E_2~0=v_~E_2~0_6} OutVars{~E_2~0=v_~E_2~0_6} AuxVars[] AssignedVars[] 945747#L700-1 [3670] L700-1-->L705-1: Formula: (> v_~E_3~0_6 0) InVars {~E_3~0=v_~E_3~0_6} OutVars{~E_3~0=v_~E_3~0_6} AuxVars[] AssignedVars[] 946011#L705-1 [3672] L705-1-->L710-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 945687#L710-1 [3674] L710-1-->L715-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 945688#L715-1 [3675] L715-1-->L720-1: Formula: (> v_~E_6~0_4 0) InVars {~E_6~0=v_~E_6~0_4} OutVars{~E_6~0=v_~E_6~0_4} AuxVars[] AssignedVars[] 945572#L720-1 [2412] L720-1-->L310: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_7, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_4|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_4|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_7, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_4, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_4, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_2|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_2|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_4|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_4|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_7, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_2|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_4} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 945573#L310 [3678] L310-->L310-2: Formula: (< v_~m_pc~0_5 1) InVars {~m_pc~0=v_~m_pc~0_5} OutVars{~m_pc~0=v_~m_pc~0_5} AuxVars[] AssignedVars[] 945719#L310-2 [2805] L310-2-->L321: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_11 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 945717#L321 [4267] L321-->L815: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 945718#L815 [2976] L815-->L815-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_12) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} AuxVars[] AssignedVars[] 946007#L815-2 [2961] L815-2-->L329: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 945932#L329 [3683] L329-->L329-2: Formula: (< v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 945933#L329-2 [2861] L329-2-->L340: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 945930#L340 [4268] L340-->L823: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 945931#L823 [3234] L823-->L823-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} AuxVars[] AssignedVars[] 946140#L823-2 [3235] L823-2-->L348: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_4|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 946105#L348 [3690] L348-->L348-2: Formula: (< v_~t2_pc~0_5 1) InVars {~t2_pc~0=v_~t2_pc~0_5} OutVars{~t2_pc~0=v_~t2_pc~0_5} AuxVars[] AssignedVars[] 946107#L348-2 [3153] L348-2-->L359: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 946104#L359 [4269] L359-->L831: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 945695#L831 [2537] L831-->L831-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} AuxVars[] AssignedVars[] 945682#L831-2 [2520] L831-2-->L367: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_4|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 945626#L367 [3695] L367-->L367-2: Formula: (> 1 v_~t3_pc~0_5) InVars {~t3_pc~0=v_~t3_pc~0_5} OutVars{~t3_pc~0=v_~t3_pc~0_5} AuxVars[] AssignedVars[] 945603#L367-2 [2438] L367-2-->L378: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 945604#L378 [4270] L378-->L839: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 945625#L839 [2791] L839-->L839-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} AuxVars[] AssignedVars[] 945887#L839-2 [2794] L839-2-->L386: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_7, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 945795#L386 [3702] L386-->L386-2: Formula: (< v_~t4_pc~0_5 1) InVars {~t4_pc~0=v_~t4_pc~0_5} OutVars{~t4_pc~0=v_~t4_pc~0_5} AuxVars[] AssignedVars[] 945796#L386-2 [2680] L386-2-->L397: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 945793#L397 [4271] L397-->L847: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 945794#L847 [3084] L847-->L847-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} AuxVars[] AssignedVars[] 946054#L847-2 [3064] L847-2-->L405: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_4|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 946055#L405 [3708] L405-->L405-2: Formula: (> 1 v_~t5_pc~0_5) InVars {~t5_pc~0=v_~t5_pc~0_5} OutVars{~t5_pc~0=v_~t5_pc~0_5} AuxVars[] AssignedVars[] 945961#L405-2 [2940] L405-2-->L416: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 945996#L416 [4272] L416-->L855: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 946065#L855 [3091] L855-->L855-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_12} AuxVars[] AssignedVars[] 946066#L855-2 [3093] L855-2-->L424: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_4|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 945667#L424 [3713] L424-->L424-2: Formula: (< v_~t6_pc~0_5 1) InVars {~t6_pc~0=v_~t6_pc~0_5} OutVars{~t6_pc~0=v_~t6_pc~0_5} AuxVars[] AssignedVars[] 945668#L424-2 [2503] L424-2-->L435: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 945666#L435 [4273] L435-->L863: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___5~0_49 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_28|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_28|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 945588#L863 [2425] L863-->L863-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___5~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} AuxVars[] AssignedVars[] 945561#L863-2 [3719] L863-2-->L733-1: Formula: (> v_~M_E~0_15 1) InVars {~M_E~0=v_~M_E~0_15} OutVars{~M_E~0=v_~M_E~0_15} AuxVars[] AssignedVars[] 945562#L733-1 [3722] L733-1-->L738-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 946009#L738-1 [3723] L738-1-->L743-1: Formula: (< 1 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 945685#L743-1 [3726] L743-1-->L748-1: Formula: (< 1 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 945686#L748-1 [3728] L748-1-->L753-1: Formula: (> v_~T4_E~0_10 1) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 945567#L753-1 [3729] L753-1-->L758-1: Formula: (< 1 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 945568#L758-1 [3731] L758-1-->L763-1: Formula: (> v_~T6_E~0_10 1) InVars {~T6_E~0=v_~T6_E~0_10} OutVars{~T6_E~0=v_~T6_E~0_10} AuxVars[] AssignedVars[] 945641#L763-1 [3733] L763-1-->L768-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 945642#L768-1 [3736] L768-1-->L773-1: Formula: (< 1 v_~E_2~0_14) InVars {~E_2~0=v_~E_2~0_14} OutVars{~E_2~0=v_~E_2~0_14} AuxVars[] AssignedVars[] 945866#L773-1 [3737] L773-1-->L778-1: Formula: (< 1 v_~E_3~0_14) InVars {~E_3~0=v_~E_3~0_14} OutVars{~E_3~0=v_~E_3~0_14} AuxVars[] AssignedVars[] 945867#L778-1 [3740] L778-1-->L783-1: Formula: (< 1 v_~E_4~0_14) InVars {~E_4~0=v_~E_4~0_14} OutVars{~E_4~0=v_~E_4~0_14} AuxVars[] AssignedVars[] 945740#L783-1 [3741] L783-1-->L788-1: Formula: (< 1 v_~E_5~0_14) InVars {~E_5~0=v_~E_5~0_14} OutVars{~E_5~0=v_~E_5~0_14} AuxVars[] AssignedVars[] 945741#L788-1 [3744] L788-1-->L1014-1: Formula: (< 1 v_~E_6~0_14) InVars {~E_6~0=v_~E_6~0_14} OutVars{~E_6~0=v_~E_6~0_14} AuxVars[] AssignedVars[] 946122#L1014-1 [4274] L1014-1-->L635: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp_ndt_7~0=v_ULTIMATE.start_eval_~tmp_ndt_7~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp_ndt_7~0] 961369#L635 [2020-06-22 00:13:55,638 INFO L796 eck$LassoCheckResult]: Loop: 961369#L635 [4275] L635-->L494: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_37} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 961365#L494 [2876] L494-->L531: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21 1) (= v_~m_st~0_8 0)) InVars {~m_st~0=v_~m_st~0_8} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21, ~m_st~0=v_~m_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 961361#L531 [4276] L531-->L546: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 961358#L546 [3757] L546-->L546-1: Formula: (> v_ULTIMATE.start_eval_~tmp~0_4 0) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} OutVars{ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} AuxVars[] AssignedVars[] 961354#L546-1 [3164] L546-1-->L554: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_2 |v_ULTIMATE.start_eval_#t~nondet1_3|) (= 0 v_~m_st~0_10)) InVars {~m_st~0=v_~m_st~0_10, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_3|} OutVars{ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_2|, ~m_st~0=v_~m_st~0_10, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_1~0] 961351#L554 [2472] L554-->L551: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} AuxVars[] AssignedVars[] 961349#L551 [2690] L551-->L568: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_2~0_2 |v_ULTIMATE.start_eval_#t~nondet2_3|) (= 0 v_~t1_st~0_11)) InVars {~t1_st~0=v_~t1_st~0_11, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_3|} OutVars{ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_2|, ~t1_st~0=v_~t1_st~0_11, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_2~0] 946502#L568 [3161] L568-->L565: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_2~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_5} AuxVars[] AssignedVars[] 961345#L565 [2469] L565-->L582: Formula: (and (= v_~t2_st~0_12 0) (= v_ULTIMATE.start_eval_~tmp_ndt_3~0_2 |v_ULTIMATE.start_eval_#t~nondet3_3|)) InVars {ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_3|, ~t2_st~0=v_~t2_st~0_12} OutVars{ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_2|, ~t2_st~0=v_~t2_st~0_12, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_~tmp_ndt_3~0] 961190#L582 [2901] L582-->L579: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_3~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_5} AuxVars[] AssignedVars[] 961344#L579 [3158] L579-->L596: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_4~0_2 |v_ULTIMATE.start_eval_#t~nondet4_3|) (= 0 v_~t3_st~0_14)) InVars {ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_3|, ~t3_st~0=v_~t3_st~0_14} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_2|, ~t3_st~0=v_~t3_st~0_14, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_~tmp_ndt_4~0] 961394#L596 [2608] L596-->L593: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_4~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_5} AuxVars[] AssignedVars[] 961391#L593 [3803] L593-->L607: Formula: (> 0 v_~t4_st~0_20) InVars {~t4_st~0=v_~t4_st~0_20} OutVars{~t4_st~0=v_~t4_st~0_20} AuxVars[] AssignedVars[] 961383#L607 [3815] L607-->L621: Formula: (< v_~t5_st~0_21 0) InVars {~t5_st~0=v_~t5_st~0_21} OutVars{~t5_st~0=v_~t5_st~0_21} AuxVars[] AssignedVars[] 961372#L621 [3829] L621-->L635: Formula: (< 0 v_~t6_st~0_21) InVars {~t6_st~0=v_~t6_st~0_21} OutVars{~t6_st~0=v_~t6_st~0_21} AuxVars[] AssignedVars[] 961369#L635 [2020-06-22 00:13:55,638 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:55,638 INFO L82 PathProgramCache]: Analyzing trace with hash 218945922, now seen corresponding path program 7 times [2020-06-22 00:13:55,638 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:55,638 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:55,639 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:55,639 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:55,639 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:55,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:13:55,646 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:13:55,654 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:55,655 INFO L82 PathProgramCache]: Analyzing trace with hash -1365029351, now seen corresponding path program 1 times [2020-06-22 00:13:55,655 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:55,655 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:55,656 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:55,656 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:55,656 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:55,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:13:55,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:13:55,660 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:55,660 INFO L82 PathProgramCache]: Analyzing trace with hash -1213586824, now seen corresponding path program 1 times [2020-06-22 00:13:55,661 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:55,661 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:55,661 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:55,661 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:55,661 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:55,665 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:55,684 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:55,684 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:55,684 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-06-22 00:13:55,795 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-06-22 00:13:55,795 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-06-22 00:13:55,796 INFO L87 Difference]: Start difference. First operand 75049 states and 110923 transitions. cyclomatic complexity: 35877 Second operand 3 states. [2020-06-22 00:13:56,306 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-06-22 00:13:56,306 INFO L93 Difference]: Finished difference Result 75049 states and 110443 transitions. [2020-06-22 00:13:56,307 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-06-22 00:13:56,307 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 75049 states and 110443 transitions. [2020-06-22 00:13:56,645 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 74976 [2020-06-22 00:13:56,855 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 75049 states to 75049 states and 110443 transitions. [2020-06-22 00:13:56,856 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 75049 [2020-06-22 00:13:56,909 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 75049 [2020-06-22 00:13:56,909 INFO L73 IsDeterministic]: Start isDeterministic. Operand 75049 states and 110443 transitions. [2020-06-22 00:13:56,958 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-06-22 00:13:56,959 INFO L706 BuchiCegarLoop]: Abstraction has 75049 states and 110443 transitions. [2020-06-22 00:13:57,431 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 75049 states and 110443 transitions. [2020-06-22 00:13:57,972 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 75049 to 75049. [2020-06-22 00:13:57,973 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 75049 states. [2020-06-22 00:13:58,113 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 75049 states to 75049 states and 110443 transitions. [2020-06-22 00:13:58,114 INFO L729 BuchiCegarLoop]: Abstraction has 75049 states and 110443 transitions. [2020-06-22 00:13:58,114 INFO L609 BuchiCegarLoop]: Abstraction has 75049 states and 110443 transitions. [2020-06-22 00:13:58,114 INFO L442 BuchiCegarLoop]: ======== Iteration 50============ [2020-06-22 00:13:58,114 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 75049 states and 110443 transitions. [2020-06-22 00:13:58,396 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 74976 [2020-06-22 00:13:58,396 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-06-22 00:13:58,396 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-06-22 00:13:58,397 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:58,397 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:13:58,398 INFO L794 eck$LassoCheckResult]: Stem: 1096134#ULTIMATE.startENTRY [4266] ULTIMATE.startENTRY-->L444: Formula: (and (= 1 v_~t6_i~0_7) (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~M_E~0_37 2) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 0 v_~t6_pc~0_26) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_6~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= v_~T6_E~0_18 2) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~t6_st~0_24) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t6_pc~0=v_~t6_pc~0_26, ~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~T6_E~0=v_~T6_E~0_18, ~M_E~0=v_~M_E~0_37, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ~T4_E~0=v_~T4_E~0_18, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_4|, ~t6_i~0=v_~t6_i~0_7, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ULTIMATE.start_main_~__retres1~8=v_ULTIMATE.start_main_~__retres1~8_6, ~T2_E~0=v_~T2_E~0_18, ~t6_st~0=v_~t6_st~0_24, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_6~0=v_~E_6~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t6_pc~0, ~t5_i~0, ~t1_pc~0, ~t5_st~0, ~T6_E~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ~T4_E~0, ULTIMATE.start_start_simulation_#t~ret17, ~t6_i~0, ~t2_st~0, ~t2_pc~0, ULTIMATE.start_main_~__retres1~8, ~T2_E~0, ~t6_st~0, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_6~0, ULTIMATE.start_main_#res, ~E_2~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 1095724#L444 [2453] L444-->L451-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 1095725#L451-1 [3030] L451-1-->L456-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 1095811#L456-1 [2574] L456-1-->L461-1: Formula: (and (= v_~t2_st~0_2 0) (= 1 v_~t2_i~0_3)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_2} AuxVars[] AssignedVars[~t2_st~0] 1095812#L461-1 [2880] L461-1-->L466-1: Formula: (and (= v_~t3_st~0_3 0) (= v_~t3_i~0_3 1)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_3, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 1095726#L466-1 [2457] L466-1-->L471-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 1095727#L471-1 [3209] L471-1-->L476-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 1095963#L476-1 [2761] L476-1-->L481-1: Formula: (and (= 1 v_~t6_i~0_3) (= v_~t6_st~0_4 0)) InVars {~t6_i~0=v_~t6_i~0_3} OutVars{~t6_st~0=v_~t6_st~0_4, ~t6_i~0=v_~t6_i~0_3} AuxVars[] AssignedVars[~t6_st~0] 1095964#L481-1 [3652] L481-1-->L660-1: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 1096152#L660-1 [3654] L660-1-->L665-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 1095642#L665-1 [3655] L665-1-->L670-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 1095643#L670-1 [3658] L670-1-->L675-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 1095733#L675-1 [3659] L675-1-->L680-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 1095734#L680-1 [3661] L680-1-->L685-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 1095977#L685-1 [3663] L685-1-->L690-1: Formula: (< 0 v_~T6_E~0_4) InVars {~T6_E~0=v_~T6_E~0_4} OutVars{~T6_E~0=v_~T6_E~0_4} AuxVars[] AssignedVars[] 1095978#L690-1 [3665] L690-1-->L695-1: Formula: (> v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 1095851#L695-1 [3668] L695-1-->L700-1: Formula: (> v_~E_2~0_6 0) InVars {~E_2~0=v_~E_2~0_6} OutVars{~E_2~0=v_~E_2~0_6} AuxVars[] AssignedVars[] 1095852#L700-1 [3670] L700-1-->L705-1: Formula: (> v_~E_3~0_6 0) InVars {~E_3~0=v_~E_3~0_6} OutVars{~E_3~0=v_~E_3~0_6} AuxVars[] AssignedVars[] 1096116#L705-1 [3672] L705-1-->L710-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 1095791#L710-1 [3674] L710-1-->L715-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 1095792#L715-1 [3675] L715-1-->L720-1: Formula: (> v_~E_6~0_4 0) InVars {~E_6~0=v_~E_6~0_4} OutVars{~E_6~0=v_~E_6~0_4} AuxVars[] AssignedVars[] 1095676#L720-1 [2412] L720-1-->L310: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_7, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_4|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_4|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_7, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_4, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_4, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_2|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_2|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_4|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_4|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_7, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_2|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_4} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 1095677#L310 [3678] L310-->L310-2: Formula: (< v_~m_pc~0_5 1) InVars {~m_pc~0=v_~m_pc~0_5} OutVars{~m_pc~0=v_~m_pc~0_5} AuxVars[] AssignedVars[] 1095824#L310-2 [2805] L310-2-->L321: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_11 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 1095822#L321 [4267] L321-->L815: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 1095823#L815 [2976] L815-->L815-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_12) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} AuxVars[] AssignedVars[] 1096111#L815-2 [2961] L815-2-->L329: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 1096034#L329 [3683] L329-->L329-2: Formula: (< v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 1096035#L329-2 [2861] L329-2-->L340: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 1096032#L340 [4268] L340-->L823: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 1096033#L823 [3234] L823-->L823-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} AuxVars[] AssignedVars[] 1096251#L823-2 [3235] L823-2-->L348: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_4|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 1096216#L348 [3690] L348-->L348-2: Formula: (< v_~t2_pc~0_5 1) InVars {~t2_pc~0=v_~t2_pc~0_5} OutVars{~t2_pc~0=v_~t2_pc~0_5} AuxVars[] AssignedVars[] 1096218#L348-2 [3153] L348-2-->L359: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 1096215#L359 [4269] L359-->L831: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 1095800#L831 [2537] L831-->L831-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} AuxVars[] AssignedVars[] 1095786#L831-2 [2520] L831-2-->L367: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_4|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 1095729#L367 [3695] L367-->L367-2: Formula: (> 1 v_~t3_pc~0_5) InVars {~t3_pc~0=v_~t3_pc~0_5} OutVars{~t3_pc~0=v_~t3_pc~0_5} AuxVars[] AssignedVars[] 1095706#L367-2 [2438] L367-2-->L378: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 1095707#L378 [4270] L378-->L839: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 1095728#L839 [2791] L839-->L839-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} AuxVars[] AssignedVars[] 1095991#L839-2 [2794] L839-2-->L386: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_7, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 1095901#L386 [3702] L386-->L386-2: Formula: (< v_~t4_pc~0_5 1) InVars {~t4_pc~0=v_~t4_pc~0_5} OutVars{~t4_pc~0=v_~t4_pc~0_5} AuxVars[] AssignedVars[] 1095902#L386-2 [2680] L386-2-->L397: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 1095899#L397 [4271] L397-->L847: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 1095900#L847 [3084] L847-->L847-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} AuxVars[] AssignedVars[] 1096160#L847-2 [3064] L847-2-->L405: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_4|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 1096161#L405 [3708] L405-->L405-2: Formula: (> 1 v_~t5_pc~0_5) InVars {~t5_pc~0=v_~t5_pc~0_5} OutVars{~t5_pc~0=v_~t5_pc~0_5} AuxVars[] AssignedVars[] 1096064#L405-2 [2940] L405-2-->L416: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 1096100#L416 [4272] L416-->L855: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 1096175#L855 [3091] L855-->L855-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_12} AuxVars[] AssignedVars[] 1096176#L855-2 [3093] L855-2-->L424: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_4|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 1095771#L424 [3713] L424-->L424-2: Formula: (< v_~t6_pc~0_5 1) InVars {~t6_pc~0=v_~t6_pc~0_5} OutVars{~t6_pc~0=v_~t6_pc~0_5} AuxVars[] AssignedVars[] 1095772#L424-2 [2503] L424-2-->L435: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 1095770#L435 [4273] L435-->L863: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___5~0_49 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_28|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_28|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 1095692#L863 [2425] L863-->L863-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___5~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} AuxVars[] AssignedVars[] 1095666#L863-2 [3719] L863-2-->L733-1: Formula: (> v_~M_E~0_15 1) InVars {~M_E~0=v_~M_E~0_15} OutVars{~M_E~0=v_~M_E~0_15} AuxVars[] AssignedVars[] 1095667#L733-1 [3722] L733-1-->L738-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 1096114#L738-1 [3723] L738-1-->L743-1: Formula: (< 1 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 1095789#L743-1 [3726] L743-1-->L748-1: Formula: (< 1 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 1095790#L748-1 [3728] L748-1-->L753-1: Formula: (> v_~T4_E~0_10 1) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 1095671#L753-1 [3729] L753-1-->L758-1: Formula: (< 1 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 1095672#L758-1 [3731] L758-1-->L763-1: Formula: (> v_~T6_E~0_10 1) InVars {~T6_E~0=v_~T6_E~0_10} OutVars{~T6_E~0=v_~T6_E~0_10} AuxVars[] AssignedVars[] 1095744#L763-1 [3733] L763-1-->L768-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 1095745#L768-1 [3736] L768-1-->L773-1: Formula: (< 1 v_~E_2~0_14) InVars {~E_2~0=v_~E_2~0_14} OutVars{~E_2~0=v_~E_2~0_14} AuxVars[] AssignedVars[] 1095969#L773-1 [3737] L773-1-->L778-1: Formula: (< 1 v_~E_3~0_14) InVars {~E_3~0=v_~E_3~0_14} OutVars{~E_3~0=v_~E_3~0_14} AuxVars[] AssignedVars[] 1095970#L778-1 [3740] L778-1-->L783-1: Formula: (< 1 v_~E_4~0_14) InVars {~E_4~0=v_~E_4~0_14} OutVars{~E_4~0=v_~E_4~0_14} AuxVars[] AssignedVars[] 1095845#L783-1 [3741] L783-1-->L788-1: Formula: (< 1 v_~E_5~0_14) InVars {~E_5~0=v_~E_5~0_14} OutVars{~E_5~0=v_~E_5~0_14} AuxVars[] AssignedVars[] 1095846#L788-1 [3744] L788-1-->L1014-1: Formula: (< 1 v_~E_6~0_14) InVars {~E_6~0=v_~E_6~0_14} OutVars{~E_6~0=v_~E_6~0_14} AuxVars[] AssignedVars[] 1096234#L1014-1 [4274] L1014-1-->L635: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp_ndt_7~0=v_ULTIMATE.start_eval_~tmp_ndt_7~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp_ndt_7~0] 1104917#L635 [2020-06-22 00:13:58,399 INFO L796 eck$LassoCheckResult]: Loop: 1104917#L635 [4275] L635-->L494: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_37} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 1150818#L494 [2876] L494-->L531: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21 1) (= v_~m_st~0_8 0)) InVars {~m_st~0=v_~m_st~0_8} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21, ~m_st~0=v_~m_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 1150817#L531 [4276] L531-->L546: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 1150816#L546 [3757] L546-->L546-1: Formula: (> v_ULTIMATE.start_eval_~tmp~0_4 0) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} OutVars{ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} AuxVars[] AssignedVars[] 1150814#L546-1 [3164] L546-1-->L554: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_2 |v_ULTIMATE.start_eval_#t~nondet1_3|) (= 0 v_~m_st~0_10)) InVars {~m_st~0=v_~m_st~0_10, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_3|} OutVars{ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_2|, ~m_st~0=v_~m_st~0_10, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_1~0] 1150813#L554 [2472] L554-->L551: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} AuxVars[] AssignedVars[] 1104371#L551 [2690] L551-->L568: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_2~0_2 |v_ULTIMATE.start_eval_#t~nondet2_3|) (= 0 v_~t1_st~0_11)) InVars {~t1_st~0=v_~t1_st~0_11, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_3|} OutVars{ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_2|, ~t1_st~0=v_~t1_st~0_11, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_2~0] 1103160#L568 [3161] L568-->L565: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_2~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_5} AuxVars[] AssignedVars[] 1103161#L565 [2469] L565-->L582: Formula: (and (= v_~t2_st~0_12 0) (= v_ULTIMATE.start_eval_~tmp_ndt_3~0_2 |v_ULTIMATE.start_eval_#t~nondet3_3|)) InVars {ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_3|, ~t2_st~0=v_~t2_st~0_12} OutVars{ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_2|, ~t2_st~0=v_~t2_st~0_12, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_~tmp_ndt_3~0] 1104252#L582 [2901] L582-->L579: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_3~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_5} AuxVars[] AssignedVars[] 1104249#L579 [3158] L579-->L596: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_4~0_2 |v_ULTIMATE.start_eval_#t~nondet4_3|) (= 0 v_~t3_st~0_14)) InVars {ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_3|, ~t3_st~0=v_~t3_st~0_14} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_2|, ~t3_st~0=v_~t3_st~0_14, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_~tmp_ndt_4~0] 1104226#L596 [2608] L596-->L593: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_4~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_5} AuxVars[] AssignedVars[] 1104245#L593 [3804] L593-->L607: Formula: (< 0 v_~t4_st~0_20) InVars {~t4_st~0=v_~t4_st~0_20} OutVars{~t4_st~0=v_~t4_st~0_20} AuxVars[] AssignedVars[] 1105045#L607 [3815] L607-->L621: Formula: (< v_~t5_st~0_21 0) InVars {~t5_st~0=v_~t5_st~0_21} OutVars{~t5_st~0=v_~t5_st~0_21} AuxVars[] AssignedVars[] 1104921#L621 [3829] L621-->L635: Formula: (< 0 v_~t6_st~0_21) InVars {~t6_st~0=v_~t6_st~0_21} OutVars{~t6_st~0=v_~t6_st~0_21} AuxVars[] AssignedVars[] 1104917#L635 [2020-06-22 00:13:58,399 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:58,399 INFO L82 PathProgramCache]: Analyzing trace with hash 218945922, now seen corresponding path program 8 times [2020-06-22 00:13:58,399 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:58,399 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:58,400 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:58,400 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:58,400 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:58,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:13:58,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:13:58,415 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:58,415 INFO L82 PathProgramCache]: Analyzing trace with hash -1365028390, now seen corresponding path program 1 times [2020-06-22 00:13:58,415 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:58,415 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:58,416 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:58,416 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2020-06-22 00:13:58,416 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:58,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:13:58,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:13:58,420 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:13:58,420 INFO L82 PathProgramCache]: Analyzing trace with hash -1213585863, now seen corresponding path program 1 times [2020-06-22 00:13:58,421 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:13:58,421 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:13:58,421 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:58,421 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:13:58,421 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:13:58,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:13:58,444 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:13:58,445 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:13:58,445 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-06-22 00:13:58,554 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-06-22 00:13:58,554 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-06-22 00:13:58,554 INFO L87 Difference]: Start difference. First operand 75049 states and 110443 transitions. cyclomatic complexity: 35397 Second operand 3 states. [2020-06-22 00:13:59,486 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-06-22 00:13:59,486 INFO L93 Difference]: Finished difference Result 138939 states and 203817 transitions. [2020-06-22 00:13:59,487 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-06-22 00:13:59,487 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 138939 states and 203817 transitions. [2020-06-22 00:14:00,135 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 138866 [2020-06-22 00:14:00,550 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 138939 states to 138939 states and 203817 transitions. [2020-06-22 00:14:00,550 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 138939 [2020-06-22 00:14:00,658 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 138939 [2020-06-22 00:14:00,658 INFO L73 IsDeterministic]: Start isDeterministic. Operand 138939 states and 203817 transitions. [2020-06-22 00:14:00,751 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-06-22 00:14:00,751 INFO L706 BuchiCegarLoop]: Abstraction has 138939 states and 203817 transitions. [2020-06-22 00:14:00,824 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 138939 states and 203817 transitions. [2020-06-22 00:14:04,115 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 138939 to 135963. [2020-06-22 00:14:04,115 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 135963 states. [2020-06-22 00:14:04,380 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 135963 states to 135963 states and 199305 transitions. [2020-06-22 00:14:04,381 INFO L729 BuchiCegarLoop]: Abstraction has 135963 states and 199305 transitions. [2020-06-22 00:14:04,381 INFO L609 BuchiCegarLoop]: Abstraction has 135963 states and 199305 transitions. [2020-06-22 00:14:04,381 INFO L442 BuchiCegarLoop]: ======== Iteration 51============ [2020-06-22 00:14:04,381 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 135963 states and 199305 transitions. [2020-06-22 00:14:04,898 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 135890 [2020-06-22 00:14:04,898 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-06-22 00:14:04,898 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-06-22 00:14:04,899 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:14:04,899 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:14:04,900 INFO L794 eck$LassoCheckResult]: Stem: 1310154#ULTIMATE.startENTRY [4266] ULTIMATE.startENTRY-->L444: Formula: (and (= 1 v_~t6_i~0_7) (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~M_E~0_37 2) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 0 v_~t6_pc~0_26) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_6~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= v_~T6_E~0_18 2) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~t6_st~0_24) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t6_pc~0=v_~t6_pc~0_26, ~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~T6_E~0=v_~T6_E~0_18, ~M_E~0=v_~M_E~0_37, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ~T4_E~0=v_~T4_E~0_18, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_4|, ~t6_i~0=v_~t6_i~0_7, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ULTIMATE.start_main_~__retres1~8=v_ULTIMATE.start_main_~__retres1~8_6, ~T2_E~0=v_~T2_E~0_18, ~t6_st~0=v_~t6_st~0_24, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_6~0=v_~E_6~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t6_pc~0, ~t5_i~0, ~t1_pc~0, ~t5_st~0, ~T6_E~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ~T4_E~0, ULTIMATE.start_start_simulation_#t~ret17, ~t6_i~0, ~t2_st~0, ~t2_pc~0, ULTIMATE.start_main_~__retres1~8, ~T2_E~0, ~t6_st~0, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_6~0, ULTIMATE.start_main_#res, ~E_2~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 1309718#L444 [2453] L444-->L451-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 1309719#L451-1 [3030] L451-1-->L456-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 1309812#L456-1 [2574] L456-1-->L461-1: Formula: (and (= v_~t2_st~0_2 0) (= 1 v_~t2_i~0_3)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_2} AuxVars[] AssignedVars[~t2_st~0] 1309813#L461-1 [2880] L461-1-->L466-1: Formula: (and (= v_~t3_st~0_3 0) (= v_~t3_i~0_3 1)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_3, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 1309722#L466-1 [2457] L466-1-->L471-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 1309723#L471-1 [3209] L471-1-->L476-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 1309975#L476-1 [2761] L476-1-->L481-1: Formula: (and (= 1 v_~t6_i~0_3) (= v_~t6_st~0_4 0)) InVars {~t6_i~0=v_~t6_i~0_3} OutVars{~t6_st~0=v_~t6_st~0_4, ~t6_i~0=v_~t6_i~0_3} AuxVars[] AssignedVars[~t6_st~0] 1309976#L481-1 [3652] L481-1-->L660-1: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 1310177#L660-1 [3654] L660-1-->L665-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 1309636#L665-1 [3655] L665-1-->L670-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 1309637#L670-1 [3658] L670-1-->L675-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 1309729#L675-1 [3659] L675-1-->L680-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 1309730#L680-1 [3661] L680-1-->L685-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 1309987#L685-1 [3663] L685-1-->L690-1: Formula: (< 0 v_~T6_E~0_4) InVars {~T6_E~0=v_~T6_E~0_4} OutVars{~T6_E~0=v_~T6_E~0_4} AuxVars[] AssignedVars[] 1309988#L690-1 [3665] L690-1-->L695-1: Formula: (> v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 1309852#L695-1 [3668] L695-1-->L700-1: Formula: (> v_~E_2~0_6 0) InVars {~E_2~0=v_~E_2~0_6} OutVars{~E_2~0=v_~E_2~0_6} AuxVars[] AssignedVars[] 1309853#L700-1 [3670] L700-1-->L705-1: Formula: (> v_~E_3~0_6 0) InVars {~E_3~0=v_~E_3~0_6} OutVars{~E_3~0=v_~E_3~0_6} AuxVars[] AssignedVars[] 1310135#L705-1 [3672] L705-1-->L710-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 1309788#L710-1 [3674] L710-1-->L715-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 1309789#L715-1 [3675] L715-1-->L720-1: Formula: (> v_~E_6~0_4 0) InVars {~E_6~0=v_~E_6~0_4} OutVars{~E_6~0=v_~E_6~0_4} AuxVars[] AssignedVars[] 1309673#L720-1 [2412] L720-1-->L310: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_7, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_4|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_4|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_7, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_4, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_4, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_2|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_2|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_4|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_4|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_7, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_2|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_4} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 1309674#L310 [3678] L310-->L310-2: Formula: (< v_~m_pc~0_5 1) InVars {~m_pc~0=v_~m_pc~0_5} OutVars{~m_pc~0=v_~m_pc~0_5} AuxVars[] AssignedVars[] 1309825#L310-2 [2805] L310-2-->L321: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_11 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 1309820#L321 [4267] L321-->L815: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 1309821#L815 [2976] L815-->L815-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_12) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} AuxVars[] AssignedVars[] 1310131#L815-2 [2961] L815-2-->L329: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 1310048#L329 [3683] L329-->L329-2: Formula: (< v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 1310049#L329-2 [2861] L329-2-->L340: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 1310044#L340 [4268] L340-->L823: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 1310045#L823 [3234] L823-->L823-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} AuxVars[] AssignedVars[] 1310285#L823-2 [3235] L823-2-->L348: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_4|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 1310242#L348 [3690] L348-->L348-2: Formula: (< v_~t2_pc~0_5 1) InVars {~t2_pc~0=v_~t2_pc~0_5} OutVars{~t2_pc~0=v_~t2_pc~0_5} AuxVars[] AssignedVars[] 1310244#L348-2 [3153] L348-2-->L359: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 1310239#L359 [4269] L359-->L831: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 1309797#L831 [2537] L831-->L831-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} AuxVars[] AssignedVars[] 1309783#L831-2 [2520] L831-2-->L367: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_4|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 1309725#L367 [3695] L367-->L367-2: Formula: (> 1 v_~t3_pc~0_5) InVars {~t3_pc~0=v_~t3_pc~0_5} OutVars{~t3_pc~0=v_~t3_pc~0_5} AuxVars[] AssignedVars[] 1309704#L367-2 [2438] L367-2-->L378: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 1309705#L378 [4270] L378-->L839: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 1309724#L839 [2791] L839-->L839-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} AuxVars[] AssignedVars[] 1310002#L839-2 [2794] L839-2-->L386: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_7, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 1309906#L386 [3702] L386-->L386-2: Formula: (< v_~t4_pc~0_5 1) InVars {~t4_pc~0=v_~t4_pc~0_5} OutVars{~t4_pc~0=v_~t4_pc~0_5} AuxVars[] AssignedVars[] 1309907#L386-2 [2680] L386-2-->L397: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 1309904#L397 [4271] L397-->L847: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 1309905#L847 [3084] L847-->L847-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} AuxVars[] AssignedVars[] 1310188#L847-2 [3064] L847-2-->L405: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_4|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 1310189#L405 [3708] L405-->L405-2: Formula: (> 1 v_~t5_pc~0_5) InVars {~t5_pc~0=v_~t5_pc~0_5} OutVars{~t5_pc~0=v_~t5_pc~0_5} AuxVars[] AssignedVars[] 1310078#L405-2 [2940] L405-2-->L416: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 1310117#L416 [4272] L416-->L855: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 1310200#L855 [3091] L855-->L855-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_12} AuxVars[] AssignedVars[] 1310201#L855-2 [3093] L855-2-->L424: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_4|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 1309768#L424 [3713] L424-->L424-2: Formula: (< v_~t6_pc~0_5 1) InVars {~t6_pc~0=v_~t6_pc~0_5} OutVars{~t6_pc~0=v_~t6_pc~0_5} AuxVars[] AssignedVars[] 1309769#L424-2 [2503] L424-2-->L435: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 1309765#L435 [4273] L435-->L863: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___5~0_49 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_28|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_28|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 1309687#L863 [2425] L863-->L863-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___5~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} AuxVars[] AssignedVars[] 1309659#L863-2 [3719] L863-2-->L733-1: Formula: (> v_~M_E~0_15 1) InVars {~M_E~0=v_~M_E~0_15} OutVars{~M_E~0=v_~M_E~0_15} AuxVars[] AssignedVars[] 1309660#L733-1 [3722] L733-1-->L738-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 1310133#L738-1 [3723] L738-1-->L743-1: Formula: (< 1 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 1309786#L743-1 [3726] L743-1-->L748-1: Formula: (< 1 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 1309787#L748-1 [3728] L748-1-->L753-1: Formula: (> v_~T4_E~0_10 1) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 1309667#L753-1 [3729] L753-1-->L758-1: Formula: (< 1 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 1309668#L758-1 [3731] L758-1-->L763-1: Formula: (> v_~T6_E~0_10 1) InVars {~T6_E~0=v_~T6_E~0_10} OutVars{~T6_E~0=v_~T6_E~0_10} AuxVars[] AssignedVars[] 1309740#L763-1 [3733] L763-1-->L768-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 1309741#L768-1 [3736] L768-1-->L773-1: Formula: (< 1 v_~E_2~0_14) InVars {~E_2~0=v_~E_2~0_14} OutVars{~E_2~0=v_~E_2~0_14} AuxVars[] AssignedVars[] 1309979#L773-1 [3737] L773-1-->L778-1: Formula: (< 1 v_~E_3~0_14) InVars {~E_3~0=v_~E_3~0_14} OutVars{~E_3~0=v_~E_3~0_14} AuxVars[] AssignedVars[] 1309980#L778-1 [3740] L778-1-->L783-1: Formula: (< 1 v_~E_4~0_14) InVars {~E_4~0=v_~E_4~0_14} OutVars{~E_4~0=v_~E_4~0_14} AuxVars[] AssignedVars[] 1309844#L783-1 [3741] L783-1-->L788-1: Formula: (< 1 v_~E_5~0_14) InVars {~E_5~0=v_~E_5~0_14} OutVars{~E_5~0=v_~E_5~0_14} AuxVars[] AssignedVars[] 1309845#L788-1 [3744] L788-1-->L1014-1: Formula: (< 1 v_~E_6~0_14) InVars {~E_6~0=v_~E_6~0_14} OutVars{~E_6~0=v_~E_6~0_14} AuxVars[] AssignedVars[] 1310264#L1014-1 [4274] L1014-1-->L635: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp_ndt_7~0=v_ULTIMATE.start_eval_~tmp_ndt_7~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp_ndt_7~0] 1351860#L635 [2020-06-22 00:14:04,901 INFO L796 eck$LassoCheckResult]: Loop: 1351860#L635 [4275] L635-->L494: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_37} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 1351849#L494 [2876] L494-->L531: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21 1) (= v_~m_st~0_8 0)) InVars {~m_st~0=v_~m_st~0_8} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21, ~m_st~0=v_~m_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 1351841#L531 [4276] L531-->L546: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 1351835#L546 [3757] L546-->L546-1: Formula: (> v_ULTIMATE.start_eval_~tmp~0_4 0) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} OutVars{ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} AuxVars[] AssignedVars[] 1351825#L546-1 [3164] L546-1-->L554: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_2 |v_ULTIMATE.start_eval_#t~nondet1_3|) (= 0 v_~m_st~0_10)) InVars {~m_st~0=v_~m_st~0_10, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_3|} OutVars{ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_2|, ~m_st~0=v_~m_st~0_10, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_1~0] 1351816#L554 [2472] L554-->L551: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} AuxVars[] AssignedVars[] 1351809#L551 [2690] L551-->L568: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_2~0_2 |v_ULTIMATE.start_eval_#t~nondet2_3|) (= 0 v_~t1_st~0_11)) InVars {~t1_st~0=v_~t1_st~0_11, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_3|} OutVars{ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_2|, ~t1_st~0=v_~t1_st~0_11, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_2~0] 1346778#L568 [3161] L568-->L565: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_2~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_5} AuxVars[] AssignedVars[] 1351792#L565 [2469] L565-->L582: Formula: (and (= v_~t2_st~0_12 0) (= v_ULTIMATE.start_eval_~tmp_ndt_3~0_2 |v_ULTIMATE.start_eval_#t~nondet3_3|)) InVars {ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_3|, ~t2_st~0=v_~t2_st~0_12} OutVars{ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_2|, ~t2_st~0=v_~t2_st~0_12, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_~tmp_ndt_3~0] 1351770#L582 [2901] L582-->L579: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_3~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_5} AuxVars[] AssignedVars[] 1351785#L579 [3158] L579-->L596: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_4~0_2 |v_ULTIMATE.start_eval_#t~nondet4_3|) (= 0 v_~t3_st~0_14)) InVars {ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_3|, ~t3_st~0=v_~t3_st~0_14} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_2|, ~t3_st~0=v_~t3_st~0_14, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_~tmp_ndt_4~0] 1352160#L596 [2608] L596-->L593: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_4~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_5} AuxVars[] AssignedVars[] 1350474#L593 [2898] L593-->L610: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_5~0_2 |v_ULTIMATE.start_eval_#t~nondet5_3|) (= 0 v_~t4_st~0_16)) InVars {ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_3|, ~t4_st~0=v_~t4_st~0_16} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_2, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_2|, ~t4_st~0=v_~t4_st~0_16} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_#t~nondet5] 1350266#L610 [2390] L610-->L607: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_5~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_5} AuxVars[] AssignedVars[] 1350267#L607 [3815] L607-->L621: Formula: (< v_~t5_st~0_21 0) InVars {~t5_st~0=v_~t5_st~0_21} OutVars{~t5_st~0=v_~t5_st~0_21} AuxVars[] AssignedVars[] 1351867#L621 [3829] L621-->L635: Formula: (< 0 v_~t6_st~0_21) InVars {~t6_st~0=v_~t6_st~0_21} OutVars{~t6_st~0=v_~t6_st~0_21} AuxVars[] AssignedVars[] 1351860#L635 [2020-06-22 00:14:04,901 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:14:04,901 INFO L82 PathProgramCache]: Analyzing trace with hash 218945922, now seen corresponding path program 9 times [2020-06-22 00:14:04,901 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:14:04,901 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:14:04,902 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:14:04,902 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:14:04,902 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:14:04,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:14:04,909 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:14:04,917 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:14:04,917 INFO L82 PathProgramCache]: Analyzing trace with hash 605436194, now seen corresponding path program 1 times [2020-06-22 00:14:04,917 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:14:04,917 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:14:04,918 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:14:04,918 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2020-06-22 00:14:04,918 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:14:04,919 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:14:04,921 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:14:04,922 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:14:04,922 INFO L82 PathProgramCache]: Analyzing trace with hash 1005187235, now seen corresponding path program 1 times [2020-06-22 00:14:04,923 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:14:04,923 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:14:04,923 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:14:04,923 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:14:04,923 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:14:04,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:14:04,946 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:14:04,946 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:14:04,946 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-06-22 00:14:05,056 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-06-22 00:14:05,057 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-06-22 00:14:05,057 INFO L87 Difference]: Start difference. First operand 135963 states and 199305 transitions. cyclomatic complexity: 63345 Second operand 3 states. [2020-06-22 00:14:05,753 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-06-22 00:14:05,753 INFO L93 Difference]: Finished difference Result 135963 states and 198441 transitions. [2020-06-22 00:14:05,753 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-06-22 00:14:05,754 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 135963 states and 198441 transitions. [2020-06-22 00:14:06,384 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 135890 [2020-06-22 00:14:06,792 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 135963 states to 135963 states and 198441 transitions. [2020-06-22 00:14:06,793 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 135963 [2020-06-22 00:14:06,896 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 135963 [2020-06-22 00:14:06,896 INFO L73 IsDeterministic]: Start isDeterministic. Operand 135963 states and 198441 transitions. [2020-06-22 00:14:06,984 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-06-22 00:14:06,984 INFO L706 BuchiCegarLoop]: Abstraction has 135963 states and 198441 transitions. [2020-06-22 00:14:07,055 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 135963 states and 198441 transitions. [2020-06-22 00:14:08,805 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 135963 to 135963. [2020-06-22 00:14:08,805 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 135963 states. [2020-06-22 00:14:09,074 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 135963 states to 135963 states and 198441 transitions. [2020-06-22 00:14:09,074 INFO L729 BuchiCegarLoop]: Abstraction has 135963 states and 198441 transitions. [2020-06-22 00:14:09,074 INFO L609 BuchiCegarLoop]: Abstraction has 135963 states and 198441 transitions. [2020-06-22 00:14:09,074 INFO L442 BuchiCegarLoop]: ======== Iteration 52============ [2020-06-22 00:14:09,074 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 135963 states and 198441 transitions. [2020-06-22 00:14:09,592 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 135890 [2020-06-22 00:14:09,592 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-06-22 00:14:09,593 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-06-22 00:14:09,593 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:14:09,593 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:14:09,594 INFO L794 eck$LassoCheckResult]: Stem: 1582073#ULTIMATE.startENTRY [4266] ULTIMATE.startENTRY-->L444: Formula: (and (= 1 v_~t6_i~0_7) (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~M_E~0_37 2) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 0 v_~t6_pc~0_26) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_6~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= v_~T6_E~0_18 2) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~t6_st~0_24) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t6_pc~0=v_~t6_pc~0_26, ~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~T6_E~0=v_~T6_E~0_18, ~M_E~0=v_~M_E~0_37, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ~T4_E~0=v_~T4_E~0_18, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_4|, ~t6_i~0=v_~t6_i~0_7, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ULTIMATE.start_main_~__retres1~8=v_ULTIMATE.start_main_~__retres1~8_6, ~T2_E~0=v_~T2_E~0_18, ~t6_st~0=v_~t6_st~0_24, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_6~0=v_~E_6~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t6_pc~0, ~t5_i~0, ~t1_pc~0, ~t5_st~0, ~T6_E~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ~T4_E~0, ULTIMATE.start_start_simulation_#t~ret17, ~t6_i~0, ~t2_st~0, ~t2_pc~0, ULTIMATE.start_main_~__retres1~8, ~T2_E~0, ~t6_st~0, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_6~0, ULTIMATE.start_main_#res, ~E_2~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 1581650#L444 [2453] L444-->L451-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 1581651#L451-1 [3030] L451-1-->L456-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 1581741#L456-1 [2574] L456-1-->L461-1: Formula: (and (= v_~t2_st~0_2 0) (= 1 v_~t2_i~0_3)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_2} AuxVars[] AssignedVars[~t2_st~0] 1581742#L461-1 [2880] L461-1-->L466-1: Formula: (and (= v_~t3_st~0_3 0) (= v_~t3_i~0_3 1)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_3, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 1581654#L466-1 [2457] L466-1-->L471-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 1581655#L471-1 [3209] L471-1-->L476-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 1581904#L476-1 [2761] L476-1-->L481-1: Formula: (and (= 1 v_~t6_i~0_3) (= v_~t6_st~0_4 0)) InVars {~t6_i~0=v_~t6_i~0_3} OutVars{~t6_st~0=v_~t6_st~0_4, ~t6_i~0=v_~t6_i~0_3} AuxVars[] AssignedVars[~t6_st~0] 1581905#L481-1 [3652] L481-1-->L660-1: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 1582096#L660-1 [3654] L660-1-->L665-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 1581572#L665-1 [3655] L665-1-->L670-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 1581573#L670-1 [3658] L670-1-->L675-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 1581661#L675-1 [3659] L675-1-->L680-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 1581662#L680-1 [3661] L680-1-->L685-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 1581917#L685-1 [3663] L685-1-->L690-1: Formula: (< 0 v_~T6_E~0_4) InVars {~T6_E~0=v_~T6_E~0_4} OutVars{~T6_E~0=v_~T6_E~0_4} AuxVars[] AssignedVars[] 1581918#L690-1 [3665] L690-1-->L695-1: Formula: (> v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 1581781#L695-1 [3668] L695-1-->L700-1: Formula: (> v_~E_2~0_6 0) InVars {~E_2~0=v_~E_2~0_6} OutVars{~E_2~0=v_~E_2~0_6} AuxVars[] AssignedVars[] 1581782#L700-1 [3670] L700-1-->L705-1: Formula: (> v_~E_3~0_6 0) InVars {~E_3~0=v_~E_3~0_6} OutVars{~E_3~0=v_~E_3~0_6} AuxVars[] AssignedVars[] 1582057#L705-1 [3672] L705-1-->L710-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 1581720#L710-1 [3674] L710-1-->L715-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 1581721#L715-1 [3675] L715-1-->L720-1: Formula: (> v_~E_6~0_4 0) InVars {~E_6~0=v_~E_6~0_4} OutVars{~E_6~0=v_~E_6~0_4} AuxVars[] AssignedVars[] 1581607#L720-1 [2412] L720-1-->L310: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_7, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_4|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_4|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_7, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_4, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_4, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_2|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_2|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_4|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_4|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_7, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_2|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_4} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 1581608#L310 [3678] L310-->L310-2: Formula: (< v_~m_pc~0_5 1) InVars {~m_pc~0=v_~m_pc~0_5} OutVars{~m_pc~0=v_~m_pc~0_5} AuxVars[] AssignedVars[] 1581754#L310-2 [2805] L310-2-->L321: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_11 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 1581749#L321 [4267] L321-->L815: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 1581750#L815 [2976] L815-->L815-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_12) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} AuxVars[] AssignedVars[] 1582052#L815-2 [2961] L815-2-->L329: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 1581974#L329 [3683] L329-->L329-2: Formula: (< v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 1581975#L329-2 [2861] L329-2-->L340: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 1581970#L340 [4268] L340-->L823: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 1581971#L823 [3234] L823-->L823-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} AuxVars[] AssignedVars[] 1582198#L823-2 [3235] L823-2-->L348: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_4|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 1582154#L348 [3690] L348-->L348-2: Formula: (< v_~t2_pc~0_5 1) InVars {~t2_pc~0=v_~t2_pc~0_5} OutVars{~t2_pc~0=v_~t2_pc~0_5} AuxVars[] AssignedVars[] 1582156#L348-2 [3153] L348-2-->L359: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 1582150#L359 [4269] L359-->L831: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 1581729#L831 [2537] L831-->L831-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} AuxVars[] AssignedVars[] 1581715#L831-2 [2520] L831-2-->L367: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_4|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 1581657#L367 [3695] L367-->L367-2: Formula: (> 1 v_~t3_pc~0_5) InVars {~t3_pc~0=v_~t3_pc~0_5} OutVars{~t3_pc~0=v_~t3_pc~0_5} AuxVars[] AssignedVars[] 1581636#L367-2 [2438] L367-2-->L378: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 1581637#L378 [4270] L378-->L839: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 1581656#L839 [2791] L839-->L839-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} AuxVars[] AssignedVars[] 1581929#L839-2 [2794] L839-2-->L386: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_7, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 1581835#L386 [3702] L386-->L386-2: Formula: (< v_~t4_pc~0_5 1) InVars {~t4_pc~0=v_~t4_pc~0_5} OutVars{~t4_pc~0=v_~t4_pc~0_5} AuxVars[] AssignedVars[] 1581836#L386-2 [2680] L386-2-->L397: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 1581833#L397 [4271] L397-->L847: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 1581834#L847 [3084] L847-->L847-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} AuxVars[] AssignedVars[] 1582103#L847-2 [3064] L847-2-->L405: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_4|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 1582104#L405 [3708] L405-->L405-2: Formula: (> 1 v_~t5_pc~0_5) InVars {~t5_pc~0=v_~t5_pc~0_5} OutVars{~t5_pc~0=v_~t5_pc~0_5} AuxVars[] AssignedVars[] 1582004#L405-2 [2940] L405-2-->L416: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 1582037#L416 [4272] L416-->L855: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 1582114#L855 [3091] L855-->L855-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_12} AuxVars[] AssignedVars[] 1582115#L855-2 [3093] L855-2-->L424: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_4|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 1581698#L424 [3713] L424-->L424-2: Formula: (< v_~t6_pc~0_5 1) InVars {~t6_pc~0=v_~t6_pc~0_5} OutVars{~t6_pc~0=v_~t6_pc~0_5} AuxVars[] AssignedVars[] 1581699#L424-2 [2503] L424-2-->L435: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 1581695#L435 [4273] L435-->L863: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___5~0_49 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_28|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_28|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 1581623#L863 [2425] L863-->L863-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___5~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} AuxVars[] AssignedVars[] 1581594#L863-2 [3719] L863-2-->L733-1: Formula: (> v_~M_E~0_15 1) InVars {~M_E~0=v_~M_E~0_15} OutVars{~M_E~0=v_~M_E~0_15} AuxVars[] AssignedVars[] 1581595#L733-1 [3722] L733-1-->L738-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 1582054#L738-1 [3723] L738-1-->L743-1: Formula: (< 1 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 1581718#L743-1 [3726] L743-1-->L748-1: Formula: (< 1 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 1581719#L748-1 [3728] L748-1-->L753-1: Formula: (> v_~T4_E~0_10 1) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 1581602#L753-1 [3729] L753-1-->L758-1: Formula: (< 1 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 1581603#L758-1 [3731] L758-1-->L763-1: Formula: (> v_~T6_E~0_10 1) InVars {~T6_E~0=v_~T6_E~0_10} OutVars{~T6_E~0=v_~T6_E~0_10} AuxVars[] AssignedVars[] 1581672#L763-1 [3733] L763-1-->L768-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 1581673#L768-1 [3736] L768-1-->L773-1: Formula: (< 1 v_~E_2~0_14) InVars {~E_2~0=v_~E_2~0_14} OutVars{~E_2~0=v_~E_2~0_14} AuxVars[] AssignedVars[] 1581907#L773-1 [3737] L773-1-->L778-1: Formula: (< 1 v_~E_3~0_14) InVars {~E_3~0=v_~E_3~0_14} OutVars{~E_3~0=v_~E_3~0_14} AuxVars[] AssignedVars[] 1581908#L778-1 [3740] L778-1-->L783-1: Formula: (< 1 v_~E_4~0_14) InVars {~E_4~0=v_~E_4~0_14} OutVars{~E_4~0=v_~E_4~0_14} AuxVars[] AssignedVars[] 1581773#L783-1 [3741] L783-1-->L788-1: Formula: (< 1 v_~E_5~0_14) InVars {~E_5~0=v_~E_5~0_14} OutVars{~E_5~0=v_~E_5~0_14} AuxVars[] AssignedVars[] 1581774#L788-1 [3744] L788-1-->L1014-1: Formula: (< 1 v_~E_6~0_14) InVars {~E_6~0=v_~E_6~0_14} OutVars{~E_6~0=v_~E_6~0_14} AuxVars[] AssignedVars[] 1582178#L1014-1 [4274] L1014-1-->L635: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp_ndt_7~0=v_ULTIMATE.start_eval_~tmp_ndt_7~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp_ndt_7~0] 1646464#L635 [2020-06-22 00:14:09,595 INFO L796 eck$LassoCheckResult]: Loop: 1646464#L635 [4275] L635-->L494: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_37} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 1694808#L494 [2876] L494-->L531: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21 1) (= v_~m_st~0_8 0)) InVars {~m_st~0=v_~m_st~0_8} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21, ~m_st~0=v_~m_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 1694810#L531 [4276] L531-->L546: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 1698130#L546 [3757] L546-->L546-1: Formula: (> v_ULTIMATE.start_eval_~tmp~0_4 0) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} OutVars{ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} AuxVars[] AssignedVars[] 1698118#L546-1 [3164] L546-1-->L554: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_2 |v_ULTIMATE.start_eval_#t~nondet1_3|) (= 0 v_~m_st~0_10)) InVars {~m_st~0=v_~m_st~0_10, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_3|} OutVars{ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_2|, ~m_st~0=v_~m_st~0_10, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_1~0] 1581667#L554 [2472] L554-->L551: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} AuxVars[] AssignedVars[] 1581668#L551 [2690] L551-->L568: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_2~0_2 |v_ULTIMATE.start_eval_#t~nondet2_3|) (= 0 v_~t1_st~0_11)) InVars {~t1_st~0=v_~t1_st~0_11, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_3|} OutVars{ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_2|, ~t1_st~0=v_~t1_st~0_11, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_2~0] 1645355#L568 [3161] L568-->L565: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_2~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_5} AuxVars[] AssignedVars[] 1645353#L565 [2469] L565-->L582: Formula: (and (= v_~t2_st~0_12 0) (= v_ULTIMATE.start_eval_~tmp_ndt_3~0_2 |v_ULTIMATE.start_eval_#t~nondet3_3|)) InVars {ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_3|, ~t2_st~0=v_~t2_st~0_12} OutVars{ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_2|, ~t2_st~0=v_~t2_st~0_12, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_~tmp_ndt_3~0] 1645351#L582 [2901] L582-->L579: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_3~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_5} AuxVars[] AssignedVars[] 1645350#L579 [3158] L579-->L596: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_4~0_2 |v_ULTIMATE.start_eval_#t~nondet4_3|) (= 0 v_~t3_st~0_14)) InVars {ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_3|, ~t3_st~0=v_~t3_st~0_14} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_2|, ~t3_st~0=v_~t3_st~0_14, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_~tmp_ndt_4~0] 1645340#L596 [2608] L596-->L593: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_4~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_5} AuxVars[] AssignedVars[] 1645349#L593 [2898] L593-->L610: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_5~0_2 |v_ULTIMATE.start_eval_#t~nondet5_3|) (= 0 v_~t4_st~0_16)) InVars {ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_3|, ~t4_st~0=v_~t4_st~0_16} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_2, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_2|, ~t4_st~0=v_~t4_st~0_16} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_#t~nondet5] 1606574#L610 [2390] L610-->L607: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_5~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_5} AuxVars[] AssignedVars[] 1646471#L607 [3816] L607-->L621: Formula: (> v_~t5_st~0_21 0) InVars {~t5_st~0=v_~t5_st~0_21} OutVars{~t5_st~0=v_~t5_st~0_21} AuxVars[] AssignedVars[] 1646466#L621 [3829] L621-->L635: Formula: (< 0 v_~t6_st~0_21) InVars {~t6_st~0=v_~t6_st~0_21} OutVars{~t6_st~0=v_~t6_st~0_21} AuxVars[] AssignedVars[] 1646464#L635 [2020-06-22 00:14:09,595 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:14:09,595 INFO L82 PathProgramCache]: Analyzing trace with hash 218945922, now seen corresponding path program 10 times [2020-06-22 00:14:09,595 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:14:09,595 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:14:09,596 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:14:09,596 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:14:09,596 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:14:09,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:14:09,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:14:09,610 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:14:09,610 INFO L82 PathProgramCache]: Analyzing trace with hash 605436225, now seen corresponding path program 1 times [2020-06-22 00:14:09,611 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:14:09,611 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:14:09,611 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:14:09,611 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2020-06-22 00:14:09,611 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:14:09,613 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:14:09,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:14:09,616 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:14:09,616 INFO L82 PathProgramCache]: Analyzing trace with hash 1005187266, now seen corresponding path program 1 times [2020-06-22 00:14:09,616 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:14:09,616 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:14:09,617 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:14:09,617 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:14:09,617 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:14:09,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:14:09,639 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:14:09,640 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:14:09,640 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-06-22 00:14:09,778 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-06-22 00:14:09,778 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-06-22 00:14:09,778 INFO L87 Difference]: Start difference. First operand 135963 states and 198441 transitions. cyclomatic complexity: 62481 Second operand 3 states. [2020-06-22 00:14:11,066 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-06-22 00:14:11,066 INFO L93 Difference]: Finished difference Result 241311 states and 351226 transitions. [2020-06-22 00:14:11,067 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-06-22 00:14:11,067 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 241311 states and 351226 transitions. [2020-06-22 00:14:12,243 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 241172 [2020-06-22 00:14:15,985 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 241311 states to 241311 states and 351226 transitions. [2020-06-22 00:14:15,985 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 241311 [2020-06-22 00:14:16,162 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 241311 [2020-06-22 00:14:16,162 INFO L73 IsDeterministic]: Start isDeterministic. Operand 241311 states and 351226 transitions. [2020-06-22 00:14:16,306 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-06-22 00:14:16,306 INFO L706 BuchiCegarLoop]: Abstraction has 241311 states and 351226 transitions. [2020-06-22 00:14:16,435 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 241311 states and 351226 transitions. [2020-06-22 00:14:18,442 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 241311 to 234783. [2020-06-22 00:14:18,443 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 234783 states. [2020-06-22 00:14:18,939 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 234783 states to 234783 states and 342778 transitions. [2020-06-22 00:14:18,939 INFO L729 BuchiCegarLoop]: Abstraction has 234783 states and 342778 transitions. [2020-06-22 00:14:18,939 INFO L609 BuchiCegarLoop]: Abstraction has 234783 states and 342778 transitions. [2020-06-22 00:14:18,939 INFO L442 BuchiCegarLoop]: ======== Iteration 53============ [2020-06-22 00:14:18,939 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 234783 states and 342778 transitions. [2020-06-22 00:14:20,411 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 234644 [2020-06-22 00:14:20,411 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-06-22 00:14:20,412 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-06-22 00:14:20,413 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:14:20,413 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:14:20,414 INFO L794 eck$LassoCheckResult]: Stem: 1959390#ULTIMATE.startENTRY [4266] ULTIMATE.startENTRY-->L444: Formula: (and (= 1 v_~t6_i~0_7) (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~M_E~0_37 2) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 0 v_~t6_pc~0_26) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_6~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= v_~T6_E~0_18 2) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~t6_st~0_24) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t6_pc~0=v_~t6_pc~0_26, ~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~T6_E~0=v_~T6_E~0_18, ~M_E~0=v_~M_E~0_37, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ~T4_E~0=v_~T4_E~0_18, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_4|, ~t6_i~0=v_~t6_i~0_7, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ULTIMATE.start_main_~__retres1~8=v_ULTIMATE.start_main_~__retres1~8_6, ~T2_E~0=v_~T2_E~0_18, ~t6_st~0=v_~t6_st~0_24, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_6~0=v_~E_6~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t6_pc~0, ~t5_i~0, ~t1_pc~0, ~t5_st~0, ~T6_E~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ~T4_E~0, ULTIMATE.start_start_simulation_#t~ret17, ~t6_i~0, ~t2_st~0, ~t2_pc~0, ULTIMATE.start_main_~__retres1~8, ~T2_E~0, ~t6_st~0, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_6~0, ULTIMATE.start_main_#res, ~E_2~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 1958935#L444 [2453] L444-->L451-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 1958936#L451-1 [3030] L451-1-->L456-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 1959030#L456-1 [2574] L456-1-->L461-1: Formula: (and (= v_~t2_st~0_2 0) (= 1 v_~t2_i~0_3)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_2} AuxVars[] AssignedVars[~t2_st~0] 1959031#L461-1 [2880] L461-1-->L466-1: Formula: (and (= v_~t3_st~0_3 0) (= v_~t3_i~0_3 1)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_3, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 1958939#L466-1 [2457] L466-1-->L471-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 1958940#L471-1 [3648] L471-1-->L476-1: Formula: (and (= v_~t5_st~0_5 2) (> v_~t5_i~0_4 1)) InVars {~t5_i~0=v_~t5_i~0_4} OutVars{~t5_i~0=v_~t5_i~0_4, ~t5_st~0=v_~t5_st~0_5} AuxVars[] AssignedVars[~t5_st~0] 1959528#L476-1 [2761] L476-1-->L481-1: Formula: (and (= 1 v_~t6_i~0_3) (= v_~t6_st~0_4 0)) InVars {~t6_i~0=v_~t6_i~0_3} OutVars{~t6_st~0=v_~t6_st~0_4, ~t6_i~0=v_~t6_i~0_3} AuxVars[] AssignedVars[~t6_st~0] 2050211#L481-1 [3652] L481-1-->L660-1: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 2050210#L660-1 [3654] L660-1-->L665-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 2050209#L665-1 [3655] L665-1-->L670-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 2050208#L670-1 [3658] L670-1-->L675-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 2050207#L675-1 [3659] L675-1-->L680-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 2050206#L680-1 [3661] L680-1-->L685-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 2050205#L685-1 [3663] L685-1-->L690-1: Formula: (< 0 v_~T6_E~0_4) InVars {~T6_E~0=v_~T6_E~0_4} OutVars{~T6_E~0=v_~T6_E~0_4} AuxVars[] AssignedVars[] 2050204#L690-1 [3665] L690-1-->L695-1: Formula: (> v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 2050203#L695-1 [3668] L695-1-->L700-1: Formula: (> v_~E_2~0_6 0) InVars {~E_2~0=v_~E_2~0_6} OutVars{~E_2~0=v_~E_2~0_6} AuxVars[] AssignedVars[] 2050202#L700-1 [3670] L700-1-->L705-1: Formula: (> v_~E_3~0_6 0) InVars {~E_3~0=v_~E_3~0_6} OutVars{~E_3~0=v_~E_3~0_6} AuxVars[] AssignedVars[] 2050201#L705-1 [3672] L705-1-->L710-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 2050200#L710-1 [3674] L710-1-->L715-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 2050199#L715-1 [3675] L715-1-->L720-1: Formula: (> v_~E_6~0_4 0) InVars {~E_6~0=v_~E_6~0_4} OutVars{~E_6~0=v_~E_6~0_4} AuxVars[] AssignedVars[] 2050198#L720-1 [2412] L720-1-->L310: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_7, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_4|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_4|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_7, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_4, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_4, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_2|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_2|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_4|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_4|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_7, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_2|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_4} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 2050197#L310 [3678] L310-->L310-2: Formula: (< v_~m_pc~0_5 1) InVars {~m_pc~0=v_~m_pc~0_5} OutVars{~m_pc~0=v_~m_pc~0_5} AuxVars[] AssignedVars[] 2050196#L310-2 [2805] L310-2-->L321: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_11 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 2050195#L321 [4267] L321-->L815: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 2050194#L815 [2976] L815-->L815-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_12) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} AuxVars[] AssignedVars[] 2050193#L815-2 [2961] L815-2-->L329: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 2050192#L329 [3683] L329-->L329-2: Formula: (< v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 2050191#L329-2 [2861] L329-2-->L340: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 2050190#L340 [4268] L340-->L823: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 2050189#L823 [3234] L823-->L823-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} AuxVars[] AssignedVars[] 2050188#L823-2 [3235] L823-2-->L348: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_4|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 2050186#L348 [3690] L348-->L348-2: Formula: (< v_~t2_pc~0_5 1) InVars {~t2_pc~0=v_~t2_pc~0_5} OutVars{~t2_pc~0=v_~t2_pc~0_5} AuxVars[] AssignedVars[] 2050185#L348-2 [3153] L348-2-->L359: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 2050184#L359 [4269] L359-->L831: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 2050183#L831 [2537] L831-->L831-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} AuxVars[] AssignedVars[] 1959002#L831-2 [2520] L831-2-->L367: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_4|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 1958943#L367 [3695] L367-->L367-2: Formula: (> 1 v_~t3_pc~0_5) InVars {~t3_pc~0=v_~t3_pc~0_5} OutVars{~t3_pc~0=v_~t3_pc~0_5} AuxVars[] AssignedVars[] 1958922#L367-2 [2438] L367-2-->L378: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 1958923#L378 [4270] L378-->L839: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 2050170#L839 [2791] L839-->L839-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} AuxVars[] AssignedVars[] 2050168#L839-2 [2794] L839-2-->L386: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_7, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 2050167#L386 [3702] L386-->L386-2: Formula: (< v_~t4_pc~0_5 1) InVars {~t4_pc~0=v_~t4_pc~0_5} OutVars{~t4_pc~0=v_~t4_pc~0_5} AuxVars[] AssignedVars[] 1959131#L386-2 [2680] L386-2-->L397: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 1959132#L397 [4271] L397-->L847: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 1959434#L847 [3084] L847-->L847-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} AuxVars[] AssignedVars[] 1959435#L847-2 [3064] L847-2-->L405: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_4|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 1959531#L405 [3708] L405-->L405-2: Formula: (> 1 v_~t5_pc~0_5) InVars {~t5_pc~0=v_~t5_pc~0_5} OutVars{~t5_pc~0=v_~t5_pc~0_5} AuxVars[] AssignedVars[] 1959307#L405-2 [2940] L405-2-->L416: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 1959529#L416 [4272] L416-->L855: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 1959530#L855 [3712] L855-->L855-2: Formula: (and (= v_~t5_st~0_7 0) (< v_ULTIMATE.start_activate_threads_~tmp___4~0_11 0)) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_11} OutVars{~t5_st~0=v_~t5_st~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_11} AuxVars[] AssignedVars[~t5_st~0] 1959441#L855-2 [3093] L855-2-->L424: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_4|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 1958985#L424 [3713] L424-->L424-2: Formula: (< v_~t6_pc~0_5 1) InVars {~t6_pc~0=v_~t6_pc~0_5} OutVars{~t6_pc~0=v_~t6_pc~0_5} AuxVars[] AssignedVars[] 1958986#L424-2 [2503] L424-2-->L435: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 1958981#L435 [4273] L435-->L863: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___5~0_49 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_28|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_28|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 1958982#L863 [2425] L863-->L863-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___5~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} AuxVars[] AssignedVars[] 1958876#L863-2 [3719] L863-2-->L733-1: Formula: (> v_~M_E~0_15 1) InVars {~M_E~0=v_~M_E~0_15} OutVars{~M_E~0=v_~M_E~0_15} AuxVars[] AssignedVars[] 1958877#L733-1 [3722] L733-1-->L738-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 1959368#L738-1 [3723] L738-1-->L743-1: Formula: (< 1 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 1959369#L743-1 [3726] L743-1-->L748-1: Formula: (< 1 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 1959426#L748-1 [3728] L748-1-->L753-1: Formula: (> v_~T4_E~0_10 1) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 1959427#L753-1 [3729] L753-1-->L758-1: Formula: (< 1 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 1959324#L758-1 [3731] L758-1-->L763-1: Formula: (> v_~T6_E~0_10 1) InVars {~T6_E~0=v_~T6_E~0_10} OutVars{~T6_E~0=v_~T6_E~0_10} AuxVars[] AssignedVars[] 1959325#L763-1 [3733] L763-1-->L768-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 1959539#L768-1 [3736] L768-1-->L773-1: Formula: (< 1 v_~E_2~0_14) InVars {~E_2~0=v_~E_2~0_14} OutVars{~E_2~0=v_~E_2~0_14} AuxVars[] AssignedVars[] 1959540#L773-1 [3737] L773-1-->L778-1: Formula: (< 1 v_~E_3~0_14) InVars {~E_3~0=v_~E_3~0_14} OutVars{~E_3~0=v_~E_3~0_14} AuxVars[] AssignedVars[] 1959571#L778-1 [3740] L778-1-->L783-1: Formula: (< 1 v_~E_4~0_14) InVars {~E_4~0=v_~E_4~0_14} OutVars{~E_4~0=v_~E_4~0_14} AuxVars[] AssignedVars[] 1959572#L783-1 [3741] L783-1-->L788-1: Formula: (< 1 v_~E_5~0_14) InVars {~E_5~0=v_~E_5~0_14} OutVars{~E_5~0=v_~E_5~0_14} AuxVars[] AssignedVars[] 1959507#L788-1 [3744] L788-1-->L1014-1: Formula: (< 1 v_~E_6~0_14) InVars {~E_6~0=v_~E_6~0_14} OutVars{~E_6~0=v_~E_6~0_14} AuxVars[] AssignedVars[] 1959508#L1014-1 [4274] L1014-1-->L635: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp_ndt_7~0=v_ULTIMATE.start_eval_~tmp_ndt_7~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp_ndt_7~0] 2094707#L635 [2020-06-22 00:14:20,414 INFO L796 eck$LassoCheckResult]: Loop: 2094707#L635 [4275] L635-->L494: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_37} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 2094703#L494 [2876] L494-->L531: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21 1) (= v_~m_st~0_8 0)) InVars {~m_st~0=v_~m_st~0_8} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21, ~m_st~0=v_~m_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 2094699#L531 [4276] L531-->L546: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 2094697#L546 [3757] L546-->L546-1: Formula: (> v_ULTIMATE.start_eval_~tmp~0_4 0) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} OutVars{ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} AuxVars[] AssignedVars[] 2094694#L546-1 [3164] L546-1-->L554: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_2 |v_ULTIMATE.start_eval_#t~nondet1_3|) (= 0 v_~m_st~0_10)) InVars {~m_st~0=v_~m_st~0_10, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_3|} OutVars{ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_2|, ~m_st~0=v_~m_st~0_10, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_1~0] 2094692#L554 [2472] L554-->L551: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} AuxVars[] AssignedVars[] 2015268#L551 [2690] L551-->L568: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_2~0_2 |v_ULTIMATE.start_eval_#t~nondet2_3|) (= 0 v_~t1_st~0_11)) InVars {~t1_st~0=v_~t1_st~0_11, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_3|} OutVars{ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_2|, ~t1_st~0=v_~t1_st~0_11, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_2~0] 2015263#L568 [3161] L568-->L565: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_2~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_5} AuxVars[] AssignedVars[] 2015264#L565 [2469] L565-->L582: Formula: (and (= v_~t2_st~0_12 0) (= v_ULTIMATE.start_eval_~tmp_ndt_3~0_2 |v_ULTIMATE.start_eval_#t~nondet3_3|)) InVars {ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_3|, ~t2_st~0=v_~t2_st~0_12} OutVars{ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_2|, ~t2_st~0=v_~t2_st~0_12, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_~tmp_ndt_3~0] 2052732#L582 [2901] L582-->L579: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_3~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_5} AuxVars[] AssignedVars[] 2052730#L579 [3158] L579-->L596: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_4~0_2 |v_ULTIMATE.start_eval_#t~nondet4_3|) (= 0 v_~t3_st~0_14)) InVars {ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_3|, ~t3_st~0=v_~t3_st~0_14} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_2|, ~t3_st~0=v_~t3_st~0_14, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_~tmp_ndt_4~0] 2052720#L596 [2608] L596-->L593: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_4~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_5} AuxVars[] AssignedVars[] 2052728#L593 [2898] L593-->L610: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_5~0_2 |v_ULTIMATE.start_eval_#t~nondet5_3|) (= 0 v_~t4_st~0_16)) InVars {ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_3|, ~t4_st~0=v_~t4_st~0_16} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_2, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_2|, ~t4_st~0=v_~t4_st~0_16} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_#t~nondet5] 2061871#L610 [2390] L610-->L607: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_5~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_5} AuxVars[] AssignedVars[] 2061991#L607 [2626] L607-->L624: Formula: (and (= v_~t5_st~0_17 0) (= v_ULTIMATE.start_eval_~tmp_ndt_6~0_2 |v_ULTIMATE.start_eval_#t~nondet6_3|)) InVars {ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_3|, ~t5_st~0=v_~t5_st~0_17} OutVars{ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_2, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_2|, ~t5_st~0=v_~t5_st~0_17} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_eval_#t~nondet6] 2049999#L624 [3318] L624-->L621: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_6~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_5} AuxVars[] AssignedVars[] 2064332#L621 [3829] L621-->L635: Formula: (< 0 v_~t6_st~0_21) InVars {~t6_st~0=v_~t6_st~0_21} OutVars{~t6_st~0=v_~t6_st~0_21} AuxVars[] AssignedVars[] 2094707#L635 [2020-06-22 00:14:20,415 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:14:20,415 INFO L82 PathProgramCache]: Analyzing trace with hash -1459650210, now seen corresponding path program 1 times [2020-06-22 00:14:20,415 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:14:20,415 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:14:20,416 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:14:20,416 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:14:20,416 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:14:20,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:14:20,429 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:14:20,429 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:14:20,429 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-06-22 00:14:20,430 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-06-22 00:14:20,430 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:14:20,430 INFO L82 PathProgramCache]: Analyzing trace with hash 1587498189, now seen corresponding path program 1 times [2020-06-22 00:14:20,430 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:14:20,430 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:14:20,431 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:14:20,431 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:14:20,431 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:14:20,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:14:20,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:14:20,553 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-06-22 00:14:20,553 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-06-22 00:14:20,553 INFO L87 Difference]: Start difference. First operand 234783 states and 342778 transitions. cyclomatic complexity: 107998 Second operand 3 states. [2020-06-22 00:14:21,582 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-06-22 00:14:21,582 INFO L93 Difference]: Finished difference Result 234717 states and 342694 transitions. [2020-06-22 00:14:21,583 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-06-22 00:14:21,583 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 234717 states and 342694 transitions. [2020-06-22 00:14:22,746 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 234644 [2020-06-22 00:14:23,478 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 234717 states to 234717 states and 342694 transitions. [2020-06-22 00:14:23,479 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 234717 [2020-06-22 00:14:23,660 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 234717 [2020-06-22 00:14:23,660 INFO L73 IsDeterministic]: Start isDeterministic. Operand 234717 states and 342694 transitions. [2020-06-22 00:14:23,818 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-06-22 00:14:23,818 INFO L706 BuchiCegarLoop]: Abstraction has 234717 states and 342694 transitions. [2020-06-22 00:14:23,945 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 234717 states and 342694 transitions. [2020-06-22 00:14:29,889 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 234717 to 234717. [2020-06-22 00:14:29,889 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 234717 states. [2020-06-22 00:14:30,385 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 234717 states to 234717 states and 342694 transitions. [2020-06-22 00:14:30,385 INFO L729 BuchiCegarLoop]: Abstraction has 234717 states and 342694 transitions. [2020-06-22 00:14:30,385 INFO L609 BuchiCegarLoop]: Abstraction has 234717 states and 342694 transitions. [2020-06-22 00:14:30,385 INFO L442 BuchiCegarLoop]: ======== Iteration 54============ [2020-06-22 00:14:30,385 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 234717 states and 342694 transitions. [2020-06-22 00:14:31,332 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 234644 [2020-06-22 00:14:31,333 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-06-22 00:14:31,333 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-06-22 00:14:31,334 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:14:31,334 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:14:31,335 INFO L794 eck$LassoCheckResult]: Stem: 2428882#ULTIMATE.startENTRY [4266] ULTIMATE.startENTRY-->L444: Formula: (and (= 1 v_~t6_i~0_7) (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~M_E~0_37 2) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 0 v_~t6_pc~0_26) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_6~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= v_~T6_E~0_18 2) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~t6_st~0_24) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t6_pc~0=v_~t6_pc~0_26, ~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~T6_E~0=v_~T6_E~0_18, ~M_E~0=v_~M_E~0_37, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ~T4_E~0=v_~T4_E~0_18, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_4|, ~t6_i~0=v_~t6_i~0_7, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ULTIMATE.start_main_~__retres1~8=v_ULTIMATE.start_main_~__retres1~8_6, ~T2_E~0=v_~T2_E~0_18, ~t6_st~0=v_~t6_st~0_24, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_6~0=v_~E_6~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t6_pc~0, ~t5_i~0, ~t1_pc~0, ~t5_st~0, ~T6_E~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ~T4_E~0, ULTIMATE.start_start_simulation_#t~ret17, ~t6_i~0, ~t2_st~0, ~t2_pc~0, ULTIMATE.start_main_~__retres1~8, ~T2_E~0, ~t6_st~0, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_6~0, ULTIMATE.start_main_#res, ~E_2~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 2428439#L444 [2453] L444-->L451-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 2428440#L451-1 [3030] L451-1-->L456-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 2428530#L456-1 [2574] L456-1-->L461-1: Formula: (and (= v_~t2_st~0_2 0) (= 1 v_~t2_i~0_3)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_2} AuxVars[] AssignedVars[~t2_st~0] 2428531#L461-1 [2880] L461-1-->L466-1: Formula: (and (= v_~t3_st~0_3 0) (= v_~t3_i~0_3 1)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_3, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 2428443#L466-1 [2457] L466-1-->L471-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 2428444#L471-1 [3209] L471-1-->L476-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 2428704#L476-1 [2761] L476-1-->L481-1: Formula: (and (= 1 v_~t6_i~0_3) (= v_~t6_st~0_4 0)) InVars {~t6_i~0=v_~t6_i~0_3} OutVars{~t6_st~0=v_~t6_st~0_4, ~t6_i~0=v_~t6_i~0_3} AuxVars[] AssignedVars[~t6_st~0] 2428705#L481-1 [3652] L481-1-->L660-1: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 2428906#L660-1 [3654] L660-1-->L665-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 2428358#L665-1 [3655] L665-1-->L670-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 2428359#L670-1 [3658] L670-1-->L675-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 2428450#L675-1 [3659] L675-1-->L680-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 2428451#L680-1 [3661] L680-1-->L685-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 2428717#L685-1 [3663] L685-1-->L690-1: Formula: (< 0 v_~T6_E~0_4) InVars {~T6_E~0=v_~T6_E~0_4} OutVars{~T6_E~0=v_~T6_E~0_4} AuxVars[] AssignedVars[] 2428718#L690-1 [3665] L690-1-->L695-1: Formula: (> v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 2428570#L695-1 [3668] L695-1-->L700-1: Formula: (> v_~E_2~0_6 0) InVars {~E_2~0=v_~E_2~0_6} OutVars{~E_2~0=v_~E_2~0_6} AuxVars[] AssignedVars[] 2428571#L700-1 [3670] L700-1-->L705-1: Formula: (> v_~E_3~0_6 0) InVars {~E_3~0=v_~E_3~0_6} OutVars{~E_3~0=v_~E_3~0_6} AuxVars[] AssignedVars[] 2428862#L705-1 [3672] L705-1-->L710-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 2428511#L710-1 [3674] L710-1-->L715-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 2428512#L715-1 [3675] L715-1-->L720-1: Formula: (> v_~E_6~0_4 0) InVars {~E_6~0=v_~E_6~0_4} OutVars{~E_6~0=v_~E_6~0_4} AuxVars[] AssignedVars[] 2428396#L720-1 [2412] L720-1-->L310: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_7, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_4|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_4|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_7, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_4, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_4, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_2|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_2|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_4|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_4|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_7, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_2|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_4} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 2428397#L310 [3678] L310-->L310-2: Formula: (< v_~m_pc~0_5 1) InVars {~m_pc~0=v_~m_pc~0_5} OutVars{~m_pc~0=v_~m_pc~0_5} AuxVars[] AssignedVars[] 2428543#L310-2 [2805] L310-2-->L321: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_11 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 2428538#L321 [4267] L321-->L815: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 2428539#L815 [2976] L815-->L815-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_12) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} AuxVars[] AssignedVars[] 2428858#L815-2 [2961] L815-2-->L329: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 2428773#L329 [3683] L329-->L329-2: Formula: (< v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 2428774#L329-2 [2861] L329-2-->L340: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 2428769#L340 [4268] L340-->L823: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 2428770#L823 [3234] L823-->L823-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} AuxVars[] AssignedVars[] 2429019#L823-2 [3235] L823-2-->L348: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_4|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 2428973#L348 [3690] L348-->L348-2: Formula: (< v_~t2_pc~0_5 1) InVars {~t2_pc~0=v_~t2_pc~0_5} OutVars{~t2_pc~0=v_~t2_pc~0_5} AuxVars[] AssignedVars[] 2428975#L348-2 [3153] L348-2-->L359: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 2428970#L359 [4269] L359-->L831: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 2428520#L831 [2537] L831-->L831-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} AuxVars[] AssignedVars[] 2428506#L831-2 [2520] L831-2-->L367: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_4|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 2428446#L367 [3695] L367-->L367-2: Formula: (> 1 v_~t3_pc~0_5) InVars {~t3_pc~0=v_~t3_pc~0_5} OutVars{~t3_pc~0=v_~t3_pc~0_5} AuxVars[] AssignedVars[] 2428425#L367-2 [2438] L367-2-->L378: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 2428426#L378 [4270] L378-->L839: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 2428445#L839 [2791] L839-->L839-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} AuxVars[] AssignedVars[] 2428731#L839-2 [2794] L839-2-->L386: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_7, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 2428630#L386 [3702] L386-->L386-2: Formula: (< v_~t4_pc~0_5 1) InVars {~t4_pc~0=v_~t4_pc~0_5} OutVars{~t4_pc~0=v_~t4_pc~0_5} AuxVars[] AssignedVars[] 2428631#L386-2 [2680] L386-2-->L397: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 2428628#L397 [4271] L397-->L847: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 2428629#L847 [3084] L847-->L847-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} AuxVars[] AssignedVars[] 2428919#L847-2 [3064] L847-2-->L405: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_4|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 2428920#L405 [3708] L405-->L405-2: Formula: (> 1 v_~t5_pc~0_5) InVars {~t5_pc~0=v_~t5_pc~0_5} OutVars{~t5_pc~0=v_~t5_pc~0_5} AuxVars[] AssignedVars[] 2428803#L405-2 [2940] L405-2-->L416: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 2428843#L416 [4272] L416-->L855: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 2428933#L855 [3091] L855-->L855-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_12} AuxVars[] AssignedVars[] 2428934#L855-2 [3093] L855-2-->L424: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_4|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 2428489#L424 [3713] L424-->L424-2: Formula: (< v_~t6_pc~0_5 1) InVars {~t6_pc~0=v_~t6_pc~0_5} OutVars{~t6_pc~0=v_~t6_pc~0_5} AuxVars[] AssignedVars[] 2428490#L424-2 [2503] L424-2-->L435: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 2428486#L435 [4273] L435-->L863: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___5~0_49 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_28|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_28|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 2428410#L863 [2425] L863-->L863-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___5~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} AuxVars[] AssignedVars[] 2428381#L863-2 [3719] L863-2-->L733-1: Formula: (> v_~M_E~0_15 1) InVars {~M_E~0=v_~M_E~0_15} OutVars{~M_E~0=v_~M_E~0_15} AuxVars[] AssignedVars[] 2428382#L733-1 [3722] L733-1-->L738-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 2428860#L738-1 [3723] L738-1-->L743-1: Formula: (< 1 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 2428509#L743-1 [3726] L743-1-->L748-1: Formula: (< 1 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 2428510#L748-1 [3728] L748-1-->L753-1: Formula: (> v_~T4_E~0_10 1) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 2428389#L753-1 [3729] L753-1-->L758-1: Formula: (< 1 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 2428390#L758-1 [3731] L758-1-->L763-1: Formula: (> v_~T6_E~0_10 1) InVars {~T6_E~0=v_~T6_E~0_10} OutVars{~T6_E~0=v_~T6_E~0_10} AuxVars[] AssignedVars[] 2428461#L763-1 [3733] L763-1-->L768-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 2428462#L768-1 [3736] L768-1-->L773-1: Formula: (< 1 v_~E_2~0_14) InVars {~E_2~0=v_~E_2~0_14} OutVars{~E_2~0=v_~E_2~0_14} AuxVars[] AssignedVars[] 2428708#L773-1 [3737] L773-1-->L778-1: Formula: (< 1 v_~E_3~0_14) InVars {~E_3~0=v_~E_3~0_14} OutVars{~E_3~0=v_~E_3~0_14} AuxVars[] AssignedVars[] 2428709#L778-1 [3740] L778-1-->L783-1: Formula: (< 1 v_~E_4~0_14) InVars {~E_4~0=v_~E_4~0_14} OutVars{~E_4~0=v_~E_4~0_14} AuxVars[] AssignedVars[] 2428562#L783-1 [3741] L783-1-->L788-1: Formula: (< 1 v_~E_5~0_14) InVars {~E_5~0=v_~E_5~0_14} OutVars{~E_5~0=v_~E_5~0_14} AuxVars[] AssignedVars[] 2428563#L788-1 [3744] L788-1-->L1014-1: Formula: (< 1 v_~E_6~0_14) InVars {~E_6~0=v_~E_6~0_14} OutVars{~E_6~0=v_~E_6~0_14} AuxVars[] AssignedVars[] 2428995#L1014-1 [4274] L1014-1-->L635: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp_ndt_7~0=v_ULTIMATE.start_eval_~tmp_ndt_7~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp_ndt_7~0] 2513621#L635 [2020-06-22 00:14:31,335 INFO L796 eck$LassoCheckResult]: Loop: 2513621#L635 [4275] L635-->L494: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_37} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 2530640#L494 [2876] L494-->L531: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21 1) (= v_~m_st~0_8 0)) InVars {~m_st~0=v_~m_st~0_8} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21, ~m_st~0=v_~m_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 2530638#L531 [4276] L531-->L546: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 2530636#L546 [3757] L546-->L546-1: Formula: (> v_ULTIMATE.start_eval_~tmp~0_4 0) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} OutVars{ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} AuxVars[] AssignedVars[] 2530632#L546-1 [3164] L546-1-->L554: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_2 |v_ULTIMATE.start_eval_#t~nondet1_3|) (= 0 v_~m_st~0_10)) InVars {~m_st~0=v_~m_st~0_10, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_3|} OutVars{ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_2|, ~m_st~0=v_~m_st~0_10, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_1~0] 2530629#L554 [2472] L554-->L551: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} AuxVars[] AssignedVars[] 2530627#L551 [2690] L551-->L568: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_2~0_2 |v_ULTIMATE.start_eval_#t~nondet2_3|) (= 0 v_~t1_st~0_11)) InVars {~t1_st~0=v_~t1_st~0_11, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_3|} OutVars{ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_2|, ~t1_st~0=v_~t1_st~0_11, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_2~0] 2521323#L568 [3161] L568-->L565: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_2~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_5} AuxVars[] AssignedVars[] 2530626#L565 [2469] L565-->L582: Formula: (and (= v_~t2_st~0_12 0) (= v_ULTIMATE.start_eval_~tmp_ndt_3~0_2 |v_ULTIMATE.start_eval_#t~nondet3_3|)) InVars {ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_3|, ~t2_st~0=v_~t2_st~0_12} OutVars{ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_2|, ~t2_st~0=v_~t2_st~0_12, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_~tmp_ndt_3~0] 2530588#L582 [2901] L582-->L579: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_3~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_5} AuxVars[] AssignedVars[] 2509176#L579 [3158] L579-->L596: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_4~0_2 |v_ULTIMATE.start_eval_#t~nondet4_3|) (= 0 v_~t3_st~0_14)) InVars {ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_3|, ~t3_st~0=v_~t3_st~0_14} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_2|, ~t3_st~0=v_~t3_st~0_14, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_~tmp_ndt_4~0] 2509173#L596 [2608] L596-->L593: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_4~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_5} AuxVars[] AssignedVars[] 2509172#L593 [2898] L593-->L610: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_5~0_2 |v_ULTIMATE.start_eval_#t~nondet5_3|) (= 0 v_~t4_st~0_16)) InVars {ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_3|, ~t4_st~0=v_~t4_st~0_16} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_2, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_2|, ~t4_st~0=v_~t4_st~0_16} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_#t~nondet5] 2509168#L610 [2390] L610-->L607: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_5~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_5} AuxVars[] AssignedVars[] 2509169#L607 [2626] L607-->L624: Formula: (and (= v_~t5_st~0_17 0) (= v_ULTIMATE.start_eval_~tmp_ndt_6~0_2 |v_ULTIMATE.start_eval_#t~nondet6_3|)) InVars {ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_3|, ~t5_st~0=v_~t5_st~0_17} OutVars{ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_2, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_2|, ~t5_st~0=v_~t5_st~0_17} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_eval_#t~nondet6] 2470372#L624 [3318] L624-->L621: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_6~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_5} AuxVars[] AssignedVars[] 2513623#L621 [3829] L621-->L635: Formula: (< 0 v_~t6_st~0_21) InVars {~t6_st~0=v_~t6_st~0_21} OutVars{~t6_st~0=v_~t6_st~0_21} AuxVars[] AssignedVars[] 2513621#L635 [2020-06-22 00:14:31,335 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:14:31,335 INFO L82 PathProgramCache]: Analyzing trace with hash 218945922, now seen corresponding path program 11 times [2020-06-22 00:14:31,335 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:14:31,336 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:14:31,336 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:14:31,336 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:14:31,336 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:14:31,340 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:14:31,343 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:14:31,349 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:14:31,349 INFO L82 PathProgramCache]: Analyzing trace with hash 1587498189, now seen corresponding path program 2 times [2020-06-22 00:14:31,350 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:14:31,350 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:14:31,350 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:14:31,350 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2020-06-22 00:14:31,350 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:14:31,352 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:14:31,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:14:31,355 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:14:31,355 INFO L82 PathProgramCache]: Analyzing trace with hash 1094878572, now seen corresponding path program 1 times [2020-06-22 00:14:31,355 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:14:31,355 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:14:31,356 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:14:31,356 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2020-06-22 00:14:31,356 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:14:31,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:14:31,378 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:14:31,378 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:14:31,378 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-06-22 00:14:31,495 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-06-22 00:14:31,495 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-06-22 00:14:31,495 INFO L87 Difference]: Start difference. First operand 234717 states and 342694 transitions. cyclomatic complexity: 107980 Second operand 3 states. [2020-06-22 00:14:33,604 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-06-22 00:14:33,605 INFO L93 Difference]: Finished difference Result 463954 states and 672130 transitions. [2020-06-22 00:14:33,605 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-06-22 00:14:33,606 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 463954 states and 672130 transitions. [2020-06-22 00:14:37,052 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 463792 [2020-06-22 00:14:38,186 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 463954 states to 463954 states and 672130 transitions. [2020-06-22 00:14:38,187 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 463954 [2020-06-22 00:14:38,442 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 463954 [2020-06-22 00:14:38,442 INFO L73 IsDeterministic]: Start isDeterministic. Operand 463954 states and 672130 transitions. [2020-06-22 00:14:38,684 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-06-22 00:14:38,685 INFO L706 BuchiCegarLoop]: Abstraction has 463954 states and 672130 transitions. [2020-06-22 00:14:38,905 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 463954 states and 672130 transitions. [2020-06-22 00:14:48,904 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 463954 to 463954. [2020-06-22 00:14:48,905 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 463954 states. [2020-06-22 00:14:49,965 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 463954 states to 463954 states and 672130 transitions. [2020-06-22 00:14:49,966 INFO L729 BuchiCegarLoop]: Abstraction has 463954 states and 672130 transitions. [2020-06-22 00:14:49,966 INFO L609 BuchiCegarLoop]: Abstraction has 463954 states and 672130 transitions. [2020-06-22 00:14:49,966 INFO L442 BuchiCegarLoop]: ======== Iteration 55============ [2020-06-22 00:14:49,966 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 463954 states and 672130 transitions. [2020-06-22 00:14:51,880 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 463792 [2020-06-22 00:14:51,880 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-06-22 00:14:51,880 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-06-22 00:14:51,881 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:14:51,881 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:14:51,882 INFO L794 eck$LassoCheckResult]: Stem: 3127565#ULTIMATE.startENTRY [4266] ULTIMATE.startENTRY-->L444: Formula: (and (= 1 v_~t6_i~0_7) (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~M_E~0_37 2) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 0 v_~t6_pc~0_26) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_6~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= v_~T6_E~0_18 2) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~t6_st~0_24) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t6_pc~0=v_~t6_pc~0_26, ~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~T6_E~0=v_~T6_E~0_18, ~M_E~0=v_~M_E~0_37, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ~T4_E~0=v_~T4_E~0_18, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_4|, ~t6_i~0=v_~t6_i~0_7, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ULTIMATE.start_main_~__retres1~8=v_ULTIMATE.start_main_~__retres1~8_6, ~T2_E~0=v_~T2_E~0_18, ~t6_st~0=v_~t6_st~0_24, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_6~0=v_~E_6~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t6_pc~0, ~t5_i~0, ~t1_pc~0, ~t5_st~0, ~T6_E~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ~T4_E~0, ULTIMATE.start_start_simulation_#t~ret17, ~t6_i~0, ~t2_st~0, ~t2_pc~0, ULTIMATE.start_main_~__retres1~8, ~T2_E~0, ~t6_st~0, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_6~0, ULTIMATE.start_main_#res, ~E_2~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 3127117#L444 [2453] L444-->L451-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 3127118#L451-1 [3030] L451-1-->L456-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 3127214#L456-1 [2574] L456-1-->L461-1: Formula: (and (= v_~t2_st~0_2 0) (= 1 v_~t2_i~0_3)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_2} AuxVars[] AssignedVars[~t2_st~0] 3127215#L461-1 [2880] L461-1-->L466-1: Formula: (and (= v_~t3_st~0_3 0) (= v_~t3_i~0_3 1)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_3, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 3127121#L466-1 [2457] L466-1-->L471-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 3127122#L471-1 [3209] L471-1-->L476-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 3127384#L476-1 [3650] L476-1-->L481-1: Formula: (and (= v_~t6_st~0_5 2) (> 1 v_~t6_i~0_4)) InVars {~t6_i~0=v_~t6_i~0_4} OutVars{~t6_st~0=v_~t6_st~0_5, ~t6_i~0=v_~t6_i~0_4} AuxVars[] AssignedVars[~t6_st~0] 3127385#L481-1 [3652] L481-1-->L660-1: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 3127585#L660-1 [3654] L660-1-->L665-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 3127037#L665-1 [3655] L665-1-->L670-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 3127038#L670-1 [3658] L670-1-->L675-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 3127128#L675-1 [3659] L675-1-->L680-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 3127129#L680-1 [3661] L680-1-->L685-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 3127398#L685-1 [3663] L685-1-->L690-1: Formula: (< 0 v_~T6_E~0_4) InVars {~T6_E~0=v_~T6_E~0_4} OutVars{~T6_E~0=v_~T6_E~0_4} AuxVars[] AssignedVars[] 3127399#L690-1 [3665] L690-1-->L695-1: Formula: (> v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 3127255#L695-1 [3668] L695-1-->L700-1: Formula: (> v_~E_2~0_6 0) InVars {~E_2~0=v_~E_2~0_6} OutVars{~E_2~0=v_~E_2~0_6} AuxVars[] AssignedVars[] 3127256#L700-1 [3670] L700-1-->L705-1: Formula: (> v_~E_3~0_6 0) InVars {~E_3~0=v_~E_3~0_6} OutVars{~E_3~0=v_~E_3~0_6} AuxVars[] AssignedVars[] 3127549#L705-1 [3672] L705-1-->L710-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 3127187#L710-1 [3674] L710-1-->L715-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 3127188#L715-1 [3675] L715-1-->L720-1: Formula: (> v_~E_6~0_4 0) InVars {~E_6~0=v_~E_6~0_4} OutVars{~E_6~0=v_~E_6~0_4} AuxVars[] AssignedVars[] 3127073#L720-1 [2412] L720-1-->L310: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_7, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_4|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_4|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_7, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_4, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_4, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_2|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_2|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_4|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_4|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_7, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_2|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_4} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 3127074#L310 [3678] L310-->L310-2: Formula: (< v_~m_pc~0_5 1) InVars {~m_pc~0=v_~m_pc~0_5} OutVars{~m_pc~0=v_~m_pc~0_5} AuxVars[] AssignedVars[] 3127228#L310-2 [2805] L310-2-->L321: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_11 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 3127223#L321 [4267] L321-->L815: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 3127224#L815 [2976] L815-->L815-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_12) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} AuxVars[] AssignedVars[] 3127545#L815-2 [2961] L815-2-->L329: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 3127460#L329 [3683] L329-->L329-2: Formula: (< v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 3127461#L329-2 [2861] L329-2-->L340: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 3127456#L340 [4268] L340-->L823: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 3127457#L823 [3234] L823-->L823-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} AuxVars[] AssignedVars[] 3127697#L823-2 [3235] L823-2-->L348: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_4|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 3127653#L348 [3690] L348-->L348-2: Formula: (< v_~t2_pc~0_5 1) InVars {~t2_pc~0=v_~t2_pc~0_5} OutVars{~t2_pc~0=v_~t2_pc~0_5} AuxVars[] AssignedVars[] 3127655#L348-2 [3153] L348-2-->L359: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 3127649#L359 [4269] L359-->L831: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 3127197#L831 [2537] L831-->L831-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} AuxVars[] AssignedVars[] 3127182#L831-2 [2520] L831-2-->L367: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_4|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 3127124#L367 [3695] L367-->L367-2: Formula: (> 1 v_~t3_pc~0_5) InVars {~t3_pc~0=v_~t3_pc~0_5} OutVars{~t3_pc~0=v_~t3_pc~0_5} AuxVars[] AssignedVars[] 3127103#L367-2 [2438] L367-2-->L378: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 3127104#L378 [4270] L378-->L839: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 3127123#L839 [2791] L839-->L839-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} AuxVars[] AssignedVars[] 3127411#L839-2 [2794] L839-2-->L386: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_7, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 3127312#L386 [3702] L386-->L386-2: Formula: (< v_~t4_pc~0_5 1) InVars {~t4_pc~0=v_~t4_pc~0_5} OutVars{~t4_pc~0=v_~t4_pc~0_5} AuxVars[] AssignedVars[] 3127313#L386-2 [2680] L386-2-->L397: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 3127310#L397 [4271] L397-->L847: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 3127311#L847 [3084] L847-->L847-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} AuxVars[] AssignedVars[] 3127597#L847-2 [3064] L847-2-->L405: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_4|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 3127598#L405 [3708] L405-->L405-2: Formula: (> 1 v_~t5_pc~0_5) InVars {~t5_pc~0=v_~t5_pc~0_5} OutVars{~t5_pc~0=v_~t5_pc~0_5} AuxVars[] AssignedVars[] 3127490#L405-2 [2940] L405-2-->L416: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 3127530#L416 [4272] L416-->L855: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 3127611#L855 [3091] L855-->L855-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_12} AuxVars[] AssignedVars[] 3127612#L855-2 [3093] L855-2-->L424: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_4|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 3127165#L424 [3713] L424-->L424-2: Formula: (< v_~t6_pc~0_5 1) InVars {~t6_pc~0=v_~t6_pc~0_5} OutVars{~t6_pc~0=v_~t6_pc~0_5} AuxVars[] AssignedVars[] 3127166#L424-2 [2503] L424-2-->L435: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 3127162#L435 [4273] L435-->L863: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___5~0_49 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_28|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_28|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 3127087#L863 [2425] L863-->L863-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___5~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} AuxVars[] AssignedVars[] 3127060#L863-2 [3719] L863-2-->L733-1: Formula: (> v_~M_E~0_15 1) InVars {~M_E~0=v_~M_E~0_15} OutVars{~M_E~0=v_~M_E~0_15} AuxVars[] AssignedVars[] 3127061#L733-1 [3722] L733-1-->L738-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 3127547#L738-1 [3723] L738-1-->L743-1: Formula: (< 1 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 3127185#L743-1 [3726] L743-1-->L748-1: Formula: (< 1 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 3127186#L748-1 [3728] L748-1-->L753-1: Formula: (> v_~T4_E~0_10 1) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 3127068#L753-1 [3729] L753-1-->L758-1: Formula: (< 1 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 3127069#L758-1 [3731] L758-1-->L763-1: Formula: (> v_~T6_E~0_10 1) InVars {~T6_E~0=v_~T6_E~0_10} OutVars{~T6_E~0=v_~T6_E~0_10} AuxVars[] AssignedVars[] 3127139#L763-1 [3733] L763-1-->L768-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 3127140#L768-1 [3736] L768-1-->L773-1: Formula: (< 1 v_~E_2~0_14) InVars {~E_2~0=v_~E_2~0_14} OutVars{~E_2~0=v_~E_2~0_14} AuxVars[] AssignedVars[] 3127389#L773-1 [3737] L773-1-->L778-1: Formula: (< 1 v_~E_3~0_14) InVars {~E_3~0=v_~E_3~0_14} OutVars{~E_3~0=v_~E_3~0_14} AuxVars[] AssignedVars[] 3127390#L778-1 [3740] L778-1-->L783-1: Formula: (< 1 v_~E_4~0_14) InVars {~E_4~0=v_~E_4~0_14} OutVars{~E_4~0=v_~E_4~0_14} AuxVars[] AssignedVars[] 3127247#L783-1 [3741] L783-1-->L788-1: Formula: (< 1 v_~E_5~0_14) InVars {~E_5~0=v_~E_5~0_14} OutVars{~E_5~0=v_~E_5~0_14} AuxVars[] AssignedVars[] 3127248#L788-1 [3744] L788-1-->L1014-1: Formula: (< 1 v_~E_6~0_14) InVars {~E_6~0=v_~E_6~0_14} OutVars{~E_6~0=v_~E_6~0_14} AuxVars[] AssignedVars[] 3127676#L1014-1 [4274] L1014-1-->L635: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp_ndt_7~0=v_ULTIMATE.start_eval_~tmp_ndt_7~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp_ndt_7~0] 3409492#L635 [2020-06-22 00:14:51,883 INFO L796 eck$LassoCheckResult]: Loop: 3409492#L635 [4275] L635-->L494: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_37} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 3409486#L494 [2876] L494-->L531: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21 1) (= v_~m_st~0_8 0)) InVars {~m_st~0=v_~m_st~0_8} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21, ~m_st~0=v_~m_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 3409484#L531 [4276] L531-->L546: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 3409482#L546 [3757] L546-->L546-1: Formula: (> v_ULTIMATE.start_eval_~tmp~0_4 0) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} OutVars{ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} AuxVars[] AssignedVars[] 3409476#L546-1 [3164] L546-1-->L554: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_2 |v_ULTIMATE.start_eval_#t~nondet1_3|) (= 0 v_~m_st~0_10)) InVars {~m_st~0=v_~m_st~0_10, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_3|} OutVars{ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_2|, ~m_st~0=v_~m_st~0_10, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_1~0] 3409472#L554 [2472] L554-->L551: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} AuxVars[] AssignedVars[] 3409470#L551 [2690] L551-->L568: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_2~0_2 |v_ULTIMATE.start_eval_#t~nondet2_3|) (= 0 v_~t1_st~0_11)) InVars {~t1_st~0=v_~t1_st~0_11, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_3|} OutVars{ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_2|, ~t1_st~0=v_~t1_st~0_11, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_2~0] 3409453#L568 [3161] L568-->L565: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_2~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_5} AuxVars[] AssignedVars[] 3398930#L565 [2469] L565-->L582: Formula: (and (= v_~t2_st~0_12 0) (= v_ULTIMATE.start_eval_~tmp_ndt_3~0_2 |v_ULTIMATE.start_eval_#t~nondet3_3|)) InVars {ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_3|, ~t2_st~0=v_~t2_st~0_12} OutVars{ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_2|, ~t2_st~0=v_~t2_st~0_12, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_~tmp_ndt_3~0] 3398557#L582 [2901] L582-->L579: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_3~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_5} AuxVars[] AssignedVars[] 3398928#L579 [3158] L579-->L596: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_4~0_2 |v_ULTIMATE.start_eval_#t~nondet4_3|) (= 0 v_~t3_st~0_14)) InVars {ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_3|, ~t3_st~0=v_~t3_st~0_14} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_2|, ~t3_st~0=v_~t3_st~0_14, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_~tmp_ndt_4~0] 3442534#L596 [2608] L596-->L593: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_4~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_5} AuxVars[] AssignedVars[] 3322866#L593 [2898] L593-->L610: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_5~0_2 |v_ULTIMATE.start_eval_#t~nondet5_3|) (= 0 v_~t4_st~0_16)) InVars {ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_3|, ~t4_st~0=v_~t4_st~0_16} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_2, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_2|, ~t4_st~0=v_~t4_st~0_16} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_#t~nondet5] 3322864#L610 [2390] L610-->L607: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_5~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_5} AuxVars[] AssignedVars[] 3322865#L607 [2626] L607-->L624: Formula: (and (= v_~t5_st~0_17 0) (= v_ULTIMATE.start_eval_~tmp_ndt_6~0_2 |v_ULTIMATE.start_eval_#t~nondet6_3|)) InVars {ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_3|, ~t5_st~0=v_~t5_st~0_17} OutVars{ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_2, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_2|, ~t5_st~0=v_~t5_st~0_17} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_eval_#t~nondet6] 3387700#L624 [3318] L624-->L621: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_6~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_5} AuxVars[] AssignedVars[] 3387729#L621 [3829] L621-->L635: Formula: (< 0 v_~t6_st~0_21) InVars {~t6_st~0=v_~t6_st~0_21} OutVars{~t6_st~0=v_~t6_st~0_21} AuxVars[] AssignedVars[] 3409492#L635 [2020-06-22 00:14:51,883 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:14:51,883 INFO L82 PathProgramCache]: Analyzing trace with hash -630251717, now seen corresponding path program 1 times [2020-06-22 00:14:51,883 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:14:51,883 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:14:51,884 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:14:51,884 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:14:51,884 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:14:51,886 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:14:51,896 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:14:51,896 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:14:51,896 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-06-22 00:14:51,897 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-06-22 00:14:51,897 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:14:51,897 INFO L82 PathProgramCache]: Analyzing trace with hash 1587498189, now seen corresponding path program 3 times [2020-06-22 00:14:51,897 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:14:51,897 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:14:51,898 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:14:51,898 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:14:51,898 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:14:51,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:14:51,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:14:52,032 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-06-22 00:14:52,032 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-06-22 00:14:52,032 INFO L87 Difference]: Start difference. First operand 463954 states and 672130 transitions. cyclomatic complexity: 208179 Second operand 3 states. [2020-06-22 00:14:54,907 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-06-22 00:14:54,907 INFO L93 Difference]: Finished difference Result 463954 states and 672129 transitions. [2020-06-22 00:14:54,908 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-06-22 00:14:54,908 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 463954 states and 672129 transitions. [2020-06-22 00:14:57,236 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 463792 [2020-06-22 00:14:58,671 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 463954 states to 463954 states and 672129 transitions. [2020-06-22 00:14:58,671 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 463954 [2020-06-22 00:14:59,007 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 463954 [2020-06-22 00:14:59,007 INFO L73 IsDeterministic]: Start isDeterministic. Operand 463954 states and 672129 transitions. [2020-06-22 00:14:59,295 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-06-22 00:14:59,296 INFO L706 BuchiCegarLoop]: Abstraction has 463954 states and 672129 transitions. [2020-06-22 00:14:59,545 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 463954 states and 672129 transitions. [2020-06-22 00:15:11,358 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 463954 to 463954. [2020-06-22 00:15:11,359 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 463954 states. [2020-06-22 00:15:12,415 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 463954 states to 463954 states and 672129 transitions. [2020-06-22 00:15:12,415 INFO L729 BuchiCegarLoop]: Abstraction has 463954 states and 672129 transitions. [2020-06-22 00:15:12,415 INFO L609 BuchiCegarLoop]: Abstraction has 463954 states and 672129 transitions. [2020-06-22 00:15:12,415 INFO L442 BuchiCegarLoop]: ======== Iteration 56============ [2020-06-22 00:15:12,415 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 463954 states and 672129 transitions. [2020-06-22 00:15:15,075 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 463792 [2020-06-22 00:15:15,076 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-06-22 00:15:15,076 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-06-22 00:15:15,077 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:15:15,077 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:15:15,078 INFO L794 eck$LassoCheckResult]: Stem: 4055468#ULTIMATE.startENTRY [4266] ULTIMATE.startENTRY-->L444: Formula: (and (= 1 v_~t6_i~0_7) (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~M_E~0_37 2) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 0 v_~t6_pc~0_26) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_6~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= v_~T6_E~0_18 2) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~t6_st~0_24) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t6_pc~0=v_~t6_pc~0_26, ~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~T6_E~0=v_~T6_E~0_18, ~M_E~0=v_~M_E~0_37, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ~T4_E~0=v_~T4_E~0_18, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_4|, ~t6_i~0=v_~t6_i~0_7, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ULTIMATE.start_main_~__retres1~8=v_ULTIMATE.start_main_~__retres1~8_6, ~T2_E~0=v_~T2_E~0_18, ~t6_st~0=v_~t6_st~0_24, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_6~0=v_~E_6~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t6_pc~0, ~t5_i~0, ~t1_pc~0, ~t5_st~0, ~T6_E~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ~T4_E~0, ULTIMATE.start_start_simulation_#t~ret17, ~t6_i~0, ~t2_st~0, ~t2_pc~0, ULTIMATE.start_main_~__retres1~8, ~T2_E~0, ~t6_st~0, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_6~0, ULTIMATE.start_main_#res, ~E_2~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 4055030#L444 [2453] L444-->L451-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 4055031#L451-1 [3030] L451-1-->L456-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 4055121#L456-1 [2574] L456-1-->L461-1: Formula: (and (= v_~t2_st~0_2 0) (= 1 v_~t2_i~0_3)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_2} AuxVars[] AssignedVars[~t2_st~0] 4055122#L461-1 [2880] L461-1-->L466-1: Formula: (and (= v_~t3_st~0_3 0) (= v_~t3_i~0_3 1)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_3, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 4055034#L466-1 [2457] L466-1-->L471-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 4055035#L471-1 [3209] L471-1-->L476-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 4055290#L476-1 [3649] L476-1-->L481-1: Formula: (and (= v_~t6_st~0_5 2) (< 1 v_~t6_i~0_4)) InVars {~t6_i~0=v_~t6_i~0_4} OutVars{~t6_st~0=v_~t6_st~0_5, ~t6_i~0=v_~t6_i~0_4} AuxVars[] AssignedVars[~t6_st~0] 4055291#L481-1 [3652] L481-1-->L660-1: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 4055489#L660-1 [3654] L660-1-->L665-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 4054951#L665-1 [3655] L665-1-->L670-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 4054952#L670-1 [3658] L670-1-->L675-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 4055041#L675-1 [3659] L675-1-->L680-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 4055042#L680-1 [3661] L680-1-->L685-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 4055304#L685-1 [3663] L685-1-->L690-1: Formula: (< 0 v_~T6_E~0_4) InVars {~T6_E~0=v_~T6_E~0_4} OutVars{~T6_E~0=v_~T6_E~0_4} AuxVars[] AssignedVars[] 4055305#L690-1 [3665] L690-1-->L695-1: Formula: (> v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 4055162#L695-1 [3668] L695-1-->L700-1: Formula: (> v_~E_2~0_6 0) InVars {~E_2~0=v_~E_2~0_6} OutVars{~E_2~0=v_~E_2~0_6} AuxVars[] AssignedVars[] 4055163#L700-1 [3670] L700-1-->L705-1: Formula: (> v_~E_3~0_6 0) InVars {~E_3~0=v_~E_3~0_6} OutVars{~E_3~0=v_~E_3~0_6} AuxVars[] AssignedVars[] 4055448#L705-1 [3672] L705-1-->L710-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 4055101#L710-1 [3674] L710-1-->L715-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 4055102#L715-1 [3675] L715-1-->L720-1: Formula: (> v_~E_6~0_4 0) InVars {~E_6~0=v_~E_6~0_4} OutVars{~E_6~0=v_~E_6~0_4} AuxVars[] AssignedVars[] 4054987#L720-1 [2412] L720-1-->L310: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_7, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_4|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_4|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_7, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_4, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_4, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_2|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_2|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_4|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_4|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_7, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_2|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_4} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 4054988#L310 [3678] L310-->L310-2: Formula: (< v_~m_pc~0_5 1) InVars {~m_pc~0=v_~m_pc~0_5} OutVars{~m_pc~0=v_~m_pc~0_5} AuxVars[] AssignedVars[] 4055135#L310-2 [2805] L310-2-->L321: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_11 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 4055130#L321 [4267] L321-->L815: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 4055131#L815 [2976] L815-->L815-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_12) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} AuxVars[] AssignedVars[] 4055444#L815-2 [2961] L815-2-->L329: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 4055364#L329 [3683] L329-->L329-2: Formula: (< v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 4055365#L329-2 [2861] L329-2-->L340: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 4055360#L340 [4268] L340-->L823: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 4055361#L823 [3234] L823-->L823-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} AuxVars[] AssignedVars[] 4055600#L823-2 [3235] L823-2-->L348: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_4|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 4055556#L348 [3690] L348-->L348-2: Formula: (< v_~t2_pc~0_5 1) InVars {~t2_pc~0=v_~t2_pc~0_5} OutVars{~t2_pc~0=v_~t2_pc~0_5} AuxVars[] AssignedVars[] 4055558#L348-2 [3153] L348-2-->L359: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 4055553#L359 [4269] L359-->L831: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 4055111#L831 [2537] L831-->L831-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} AuxVars[] AssignedVars[] 4055096#L831-2 [2520] L831-2-->L367: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_4|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 4055037#L367 [3695] L367-->L367-2: Formula: (> 1 v_~t3_pc~0_5) InVars {~t3_pc~0=v_~t3_pc~0_5} OutVars{~t3_pc~0=v_~t3_pc~0_5} AuxVars[] AssignedVars[] 4055017#L367-2 [2438] L367-2-->L378: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 4055018#L378 [4270] L378-->L839: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 4055036#L839 [2791] L839-->L839-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} AuxVars[] AssignedVars[] 4055317#L839-2 [2794] L839-2-->L386: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_7, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 4055220#L386 [3702] L386-->L386-2: Formula: (< v_~t4_pc~0_5 1) InVars {~t4_pc~0=v_~t4_pc~0_5} OutVars{~t4_pc~0=v_~t4_pc~0_5} AuxVars[] AssignedVars[] 4055221#L386-2 [2680] L386-2-->L397: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 4055218#L397 [4271] L397-->L847: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 4055219#L847 [3084] L847-->L847-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} AuxVars[] AssignedVars[] 4055500#L847-2 [3064] L847-2-->L405: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_4|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 4055501#L405 [3708] L405-->L405-2: Formula: (> 1 v_~t5_pc~0_5) InVars {~t5_pc~0=v_~t5_pc~0_5} OutVars{~t5_pc~0=v_~t5_pc~0_5} AuxVars[] AssignedVars[] 4055391#L405-2 [2940] L405-2-->L416: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 4055431#L416 [4272] L416-->L855: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 4055513#L855 [3091] L855-->L855-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_12} AuxVars[] AssignedVars[] 4055514#L855-2 [3093] L855-2-->L424: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_4|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 4055079#L424 [3713] L424-->L424-2: Formula: (< v_~t6_pc~0_5 1) InVars {~t6_pc~0=v_~t6_pc~0_5} OutVars{~t6_pc~0=v_~t6_pc~0_5} AuxVars[] AssignedVars[] 4055080#L424-2 [2503] L424-2-->L435: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 4055076#L435 [4273] L435-->L863: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___5~0_49 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_28|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_28|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 4055001#L863 [2425] L863-->L863-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___5~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} AuxVars[] AssignedVars[] 4054974#L863-2 [3719] L863-2-->L733-1: Formula: (> v_~M_E~0_15 1) InVars {~M_E~0=v_~M_E~0_15} OutVars{~M_E~0=v_~M_E~0_15} AuxVars[] AssignedVars[] 4054975#L733-1 [3722] L733-1-->L738-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 4055446#L738-1 [3723] L738-1-->L743-1: Formula: (< 1 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 4055099#L743-1 [3726] L743-1-->L748-1: Formula: (< 1 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 4055100#L748-1 [3728] L748-1-->L753-1: Formula: (> v_~T4_E~0_10 1) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 4054982#L753-1 [3729] L753-1-->L758-1: Formula: (< 1 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 4054983#L758-1 [3731] L758-1-->L763-1: Formula: (> v_~T6_E~0_10 1) InVars {~T6_E~0=v_~T6_E~0_10} OutVars{~T6_E~0=v_~T6_E~0_10} AuxVars[] AssignedVars[] 4055052#L763-1 [3733] L763-1-->L768-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 4055053#L768-1 [3736] L768-1-->L773-1: Formula: (< 1 v_~E_2~0_14) InVars {~E_2~0=v_~E_2~0_14} OutVars{~E_2~0=v_~E_2~0_14} AuxVars[] AssignedVars[] 4055296#L773-1 [3737] L773-1-->L778-1: Formula: (< 1 v_~E_3~0_14) InVars {~E_3~0=v_~E_3~0_14} OutVars{~E_3~0=v_~E_3~0_14} AuxVars[] AssignedVars[] 4055297#L778-1 [3740] L778-1-->L783-1: Formula: (< 1 v_~E_4~0_14) InVars {~E_4~0=v_~E_4~0_14} OutVars{~E_4~0=v_~E_4~0_14} AuxVars[] AssignedVars[] 4055154#L783-1 [3741] L783-1-->L788-1: Formula: (< 1 v_~E_5~0_14) InVars {~E_5~0=v_~E_5~0_14} OutVars{~E_5~0=v_~E_5~0_14} AuxVars[] AssignedVars[] 4055155#L788-1 [3744] L788-1-->L1014-1: Formula: (< 1 v_~E_6~0_14) InVars {~E_6~0=v_~E_6~0_14} OutVars{~E_6~0=v_~E_6~0_14} AuxVars[] AssignedVars[] 4055576#L1014-1 [4274] L1014-1-->L635: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp_ndt_7~0=v_ULTIMATE.start_eval_~tmp_ndt_7~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp_ndt_7~0] 4187105#L635 [2020-06-22 00:15:15,078 INFO L796 eck$LassoCheckResult]: Loop: 4187105#L635 [4275] L635-->L494: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_37} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 4187099#L494 [2876] L494-->L531: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21 1) (= v_~m_st~0_8 0)) InVars {~m_st~0=v_~m_st~0_8} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21, ~m_st~0=v_~m_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 4187097#L531 [4276] L531-->L546: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 4187093#L546 [3757] L546-->L546-1: Formula: (> v_ULTIMATE.start_eval_~tmp~0_4 0) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} OutVars{ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} AuxVars[] AssignedVars[] 4187089#L546-1 [3164] L546-1-->L554: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_2 |v_ULTIMATE.start_eval_#t~nondet1_3|) (= 0 v_~m_st~0_10)) InVars {~m_st~0=v_~m_st~0_10, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_3|} OutVars{ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_2|, ~m_st~0=v_~m_st~0_10, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_1~0] 4187086#L554 [2472] L554-->L551: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} AuxVars[] AssignedVars[] 4187082#L551 [2690] L551-->L568: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_2~0_2 |v_ULTIMATE.start_eval_#t~nondet2_3|) (= 0 v_~t1_st~0_11)) InVars {~t1_st~0=v_~t1_st~0_11, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_3|} OutVars{ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_2|, ~t1_st~0=v_~t1_st~0_11, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_2~0] 4187078#L568 [3161] L568-->L565: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_2~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_5} AuxVars[] AssignedVars[] 4187079#L565 [2469] L565-->L582: Formula: (and (= v_~t2_st~0_12 0) (= v_ULTIMATE.start_eval_~tmp_ndt_3~0_2 |v_ULTIMATE.start_eval_#t~nondet3_3|)) InVars {ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_3|, ~t2_st~0=v_~t2_st~0_12} OutVars{ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_2|, ~t2_st~0=v_~t2_st~0_12, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_~tmp_ndt_3~0] 4289442#L582 [2901] L582-->L579: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_3~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_5} AuxVars[] AssignedVars[] 4237980#L579 [3158] L579-->L596: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_4~0_2 |v_ULTIMATE.start_eval_#t~nondet4_3|) (= 0 v_~t3_st~0_14)) InVars {ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_3|, ~t3_st~0=v_~t3_st~0_14} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_2|, ~t3_st~0=v_~t3_st~0_14, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_~tmp_ndt_4~0] 4237977#L596 [2608] L596-->L593: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_4~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_5} AuxVars[] AssignedVars[] 4237743#L593 [2898] L593-->L610: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_5~0_2 |v_ULTIMATE.start_eval_#t~nondet5_3|) (= 0 v_~t4_st~0_16)) InVars {ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_3|, ~t4_st~0=v_~t4_st~0_16} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_2, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_2|, ~t4_st~0=v_~t4_st~0_16} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_#t~nondet5] 4237742#L610 [2390] L610-->L607: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_5~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_5} AuxVars[] AssignedVars[] 4187114#L607 [2626] L607-->L624: Formula: (and (= v_~t5_st~0_17 0) (= v_ULTIMATE.start_eval_~tmp_ndt_6~0_2 |v_ULTIMATE.start_eval_#t~nondet6_3|)) InVars {ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_3|, ~t5_st~0=v_~t5_st~0_17} OutVars{ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_2, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_2|, ~t5_st~0=v_~t5_st~0_17} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_eval_#t~nondet6] 4187111#L624 [3318] L624-->L621: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_6~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_5} AuxVars[] AssignedVars[] 4187108#L621 [3829] L621-->L635: Formula: (< 0 v_~t6_st~0_21) InVars {~t6_st~0=v_~t6_st~0_21} OutVars{~t6_st~0=v_~t6_st~0_21} AuxVars[] AssignedVars[] 4187105#L635 [2020-06-22 00:15:15,078 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:15:15,079 INFO L82 PathProgramCache]: Analyzing trace with hash -421553414, now seen corresponding path program 1 times [2020-06-22 00:15:15,079 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:15:15,079 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:15:15,079 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:15:15,080 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2020-06-22 00:15:15,080 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:15:15,082 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:15:15,092 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:15:15,092 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:15:15,092 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-06-22 00:15:15,092 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-06-22 00:15:15,093 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:15:15,093 INFO L82 PathProgramCache]: Analyzing trace with hash 1587498189, now seen corresponding path program 4 times [2020-06-22 00:15:15,093 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:15:15,093 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:15:15,093 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:15:15,094 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:15:15,094 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:15:15,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:15:15,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:15:15,218 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-06-22 00:15:15,218 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-06-22 00:15:15,218 INFO L87 Difference]: Start difference. First operand 463954 states and 672129 transitions. cyclomatic complexity: 208178 Second operand 3 states. [2020-06-22 00:15:17,132 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-06-22 00:15:17,133 INFO L93 Difference]: Finished difference Result 463889 states and 672048 transitions. [2020-06-22 00:15:17,133 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-06-22 00:15:17,133 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 463889 states and 672048 transitions. [2020-06-22 00:15:19,528 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 463792 [2020-06-22 00:15:21,016 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 463889 states to 463889 states and 672048 transitions. [2020-06-22 00:15:21,017 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 463889 [2020-06-22 00:15:21,374 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 463889 [2020-06-22 00:15:21,375 INFO L73 IsDeterministic]: Start isDeterministic. Operand 463889 states and 672048 transitions. [2020-06-22 00:15:21,678 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-06-22 00:15:21,678 INFO L706 BuchiCegarLoop]: Abstraction has 463889 states and 672048 transitions. [2020-06-22 00:15:21,931 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 463889 states and 672048 transitions. [2020-06-22 00:15:27,516 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 463889 to 463889. [2020-06-22 00:15:27,517 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 463889 states. [2020-06-22 00:15:28,581 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 463889 states to 463889 states and 672048 transitions. [2020-06-22 00:15:28,582 INFO L729 BuchiCegarLoop]: Abstraction has 463889 states and 672048 transitions. [2020-06-22 00:15:28,582 INFO L609 BuchiCegarLoop]: Abstraction has 463889 states and 672048 transitions. [2020-06-22 00:15:28,582 INFO L442 BuchiCegarLoop]: ======== Iteration 57============ [2020-06-22 00:15:28,582 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 463889 states and 672048 transitions. [2020-06-22 00:15:35,092 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 463792 [2020-06-22 00:15:35,093 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-06-22 00:15:35,093 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-06-22 00:15:35,094 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:15:35,094 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:15:35,095 INFO L794 eck$LassoCheckResult]: Stem: 4983318#ULTIMATE.startENTRY [4266] ULTIMATE.startENTRY-->L444: Formula: (and (= 1 v_~t6_i~0_7) (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~M_E~0_37 2) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 0 v_~t6_pc~0_26) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_6~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= v_~T6_E~0_18 2) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~t6_st~0_24) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t6_pc~0=v_~t6_pc~0_26, ~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~T6_E~0=v_~T6_E~0_18, ~M_E~0=v_~M_E~0_37, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ~T4_E~0=v_~T4_E~0_18, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_4|, ~t6_i~0=v_~t6_i~0_7, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ULTIMATE.start_main_~__retres1~8=v_ULTIMATE.start_main_~__retres1~8_6, ~T2_E~0=v_~T2_E~0_18, ~t6_st~0=v_~t6_st~0_24, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_6~0=v_~E_6~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t6_pc~0, ~t5_i~0, ~t1_pc~0, ~t5_st~0, ~T6_E~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ~T4_E~0, ULTIMATE.start_start_simulation_#t~ret17, ~t6_i~0, ~t2_st~0, ~t2_pc~0, ULTIMATE.start_main_~__retres1~8, ~T2_E~0, ~t6_st~0, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_6~0, ULTIMATE.start_main_#res, ~E_2~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 4982877#L444 [2453] L444-->L451-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 4982878#L451-1 [3030] L451-1-->L456-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 4982967#L456-1 [2574] L456-1-->L461-1: Formula: (and (= v_~t2_st~0_2 0) (= 1 v_~t2_i~0_3)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_2} AuxVars[] AssignedVars[~t2_st~0] 4982968#L461-1 [2880] L461-1-->L466-1: Formula: (and (= v_~t3_st~0_3 0) (= v_~t3_i~0_3 1)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_3, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 4982881#L466-1 [2457] L466-1-->L471-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 4982882#L471-1 [3209] L471-1-->L476-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 4983135#L476-1 [2761] L476-1-->L481-1: Formula: (and (= 1 v_~t6_i~0_3) (= v_~t6_st~0_4 0)) InVars {~t6_i~0=v_~t6_i~0_3} OutVars{~t6_st~0=v_~t6_st~0_4, ~t6_i~0=v_~t6_i~0_3} AuxVars[] AssignedVars[~t6_st~0] 4983136#L481-1 [3652] L481-1-->L660-1: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 4983341#L660-1 [3654] L660-1-->L665-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 4982800#L665-1 [3655] L665-1-->L670-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 4982801#L670-1 [3658] L670-1-->L675-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 4982888#L675-1 [3659] L675-1-->L680-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 4982889#L680-1 [3661] L680-1-->L685-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 4983151#L685-1 [3663] L685-1-->L690-1: Formula: (< 0 v_~T6_E~0_4) InVars {~T6_E~0=v_~T6_E~0_4} OutVars{~T6_E~0=v_~T6_E~0_4} AuxVars[] AssignedVars[] 4983152#L690-1 [3665] L690-1-->L695-1: Formula: (> v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 4983007#L695-1 [3668] L695-1-->L700-1: Formula: (> v_~E_2~0_6 0) InVars {~E_2~0=v_~E_2~0_6} OutVars{~E_2~0=v_~E_2~0_6} AuxVars[] AssignedVars[] 4983008#L700-1 [3670] L700-1-->L705-1: Formula: (> v_~E_3~0_6 0) InVars {~E_3~0=v_~E_3~0_6} OutVars{~E_3~0=v_~E_3~0_6} AuxVars[] AssignedVars[] 4983298#L705-1 [3672] L705-1-->L710-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 4982947#L710-1 [3674] L710-1-->L715-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 4982948#L715-1 [3675] L715-1-->L720-1: Formula: (> v_~E_6~0_4 0) InVars {~E_6~0=v_~E_6~0_4} OutVars{~E_6~0=v_~E_6~0_4} AuxVars[] AssignedVars[] 4982836#L720-1 [2412] L720-1-->L310: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_7, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_4|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_4|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_7, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_4, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_4, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_2|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_2|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_4|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_4|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_7, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_2|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_4} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 4982837#L310 [3678] L310-->L310-2: Formula: (< v_~m_pc~0_5 1) InVars {~m_pc~0=v_~m_pc~0_5} OutVars{~m_pc~0=v_~m_pc~0_5} AuxVars[] AssignedVars[] 4982980#L310-2 [2805] L310-2-->L321: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_11 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 4982975#L321 [4267] L321-->L815: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 4982976#L815 [2976] L815-->L815-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_12) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} AuxVars[] AssignedVars[] 4983294#L815-2 [2961] L815-2-->L329: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 4983213#L329 [3683] L329-->L329-2: Formula: (< v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 4983214#L329-2 [2861] L329-2-->L340: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 4983209#L340 [4268] L340-->L823: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 4983210#L823 [3234] L823-->L823-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} AuxVars[] AssignedVars[] 4983446#L823-2 [3235] L823-2-->L348: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_4|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 4983406#L348 [3690] L348-->L348-2: Formula: (< v_~t2_pc~0_5 1) InVars {~t2_pc~0=v_~t2_pc~0_5} OutVars{~t2_pc~0=v_~t2_pc~0_5} AuxVars[] AssignedVars[] 4983408#L348-2 [3153] L348-2-->L359: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 4983403#L359 [4269] L359-->L831: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 4982956#L831 [2537] L831-->L831-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} AuxVars[] AssignedVars[] 4982942#L831-2 [2520] L831-2-->L367: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_4|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 4982884#L367 [3695] L367-->L367-2: Formula: (> 1 v_~t3_pc~0_5) InVars {~t3_pc~0=v_~t3_pc~0_5} OutVars{~t3_pc~0=v_~t3_pc~0_5} AuxVars[] AssignedVars[] 4982865#L367-2 [2438] L367-2-->L378: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 4982866#L378 [4270] L378-->L839: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 4982883#L839 [2791] L839-->L839-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} AuxVars[] AssignedVars[] 4983164#L839-2 [2794] L839-2-->L386: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_7, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 4983061#L386 [3702] L386-->L386-2: Formula: (< v_~t4_pc~0_5 1) InVars {~t4_pc~0=v_~t4_pc~0_5} OutVars{~t4_pc~0=v_~t4_pc~0_5} AuxVars[] AssignedVars[] 4983062#L386-2 [2680] L386-2-->L397: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 4983059#L397 [4271] L397-->L847: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 4983060#L847 [3084] L847-->L847-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} AuxVars[] AssignedVars[] 4983353#L847-2 [3064] L847-2-->L405: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_4|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 4983354#L405 [3708] L405-->L405-2: Formula: (> 1 v_~t5_pc~0_5) InVars {~t5_pc~0=v_~t5_pc~0_5} OutVars{~t5_pc~0=v_~t5_pc~0_5} AuxVars[] AssignedVars[] 4983242#L405-2 [2940] L405-2-->L416: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 4983282#L416 [4272] L416-->L855: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 4983364#L855 [3091] L855-->L855-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_12} AuxVars[] AssignedVars[] 4983365#L855-2 [3093] L855-2-->L424: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_4|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 4982926#L424 [3713] L424-->L424-2: Formula: (< v_~t6_pc~0_5 1) InVars {~t6_pc~0=v_~t6_pc~0_5} OutVars{~t6_pc~0=v_~t6_pc~0_5} AuxVars[] AssignedVars[] 4982927#L424-2 [2503] L424-2-->L435: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 4982923#L435 [4273] L435-->L863: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___5~0_49 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_28|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_28|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 4982850#L863 [2425] L863-->L863-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___5~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} AuxVars[] AssignedVars[] 4982823#L863-2 [3719] L863-2-->L733-1: Formula: (> v_~M_E~0_15 1) InVars {~M_E~0=v_~M_E~0_15} OutVars{~M_E~0=v_~M_E~0_15} AuxVars[] AssignedVars[] 4982824#L733-1 [3722] L733-1-->L738-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 4983296#L738-1 [3723] L738-1-->L743-1: Formula: (< 1 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 4982945#L743-1 [3726] L743-1-->L748-1: Formula: (< 1 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 4982946#L748-1 [3728] L748-1-->L753-1: Formula: (> v_~T4_E~0_10 1) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 4982831#L753-1 [3729] L753-1-->L758-1: Formula: (< 1 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 4982832#L758-1 [3731] L758-1-->L763-1: Formula: (> v_~T6_E~0_10 1) InVars {~T6_E~0=v_~T6_E~0_10} OutVars{~T6_E~0=v_~T6_E~0_10} AuxVars[] AssignedVars[] 4982899#L763-1 [3733] L763-1-->L768-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 4982900#L768-1 [3736] L768-1-->L773-1: Formula: (< 1 v_~E_2~0_14) InVars {~E_2~0=v_~E_2~0_14} OutVars{~E_2~0=v_~E_2~0_14} AuxVars[] AssignedVars[] 4983141#L773-1 [3737] L773-1-->L778-1: Formula: (< 1 v_~E_3~0_14) InVars {~E_3~0=v_~E_3~0_14} OutVars{~E_3~0=v_~E_3~0_14} AuxVars[] AssignedVars[] 4983142#L778-1 [3740] L778-1-->L783-1: Formula: (< 1 v_~E_4~0_14) InVars {~E_4~0=v_~E_4~0_14} OutVars{~E_4~0=v_~E_4~0_14} AuxVars[] AssignedVars[] 4982999#L783-1 [3741] L783-1-->L788-1: Formula: (< 1 v_~E_5~0_14) InVars {~E_5~0=v_~E_5~0_14} OutVars{~E_5~0=v_~E_5~0_14} AuxVars[] AssignedVars[] 4983000#L788-1 [3744] L788-1-->L1014-1: Formula: (< 1 v_~E_6~0_14) InVars {~E_6~0=v_~E_6~0_14} OutVars{~E_6~0=v_~E_6~0_14} AuxVars[] AssignedVars[] 4983427#L1014-1 [4274] L1014-1-->L635: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp_ndt_7~0=v_ULTIMATE.start_eval_~tmp_ndt_7~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp_ndt_7~0] 5159288#L635 [2020-06-22 00:15:35,095 INFO L796 eck$LassoCheckResult]: Loop: 5159288#L635 [4275] L635-->L494: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_37} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 5256883#L494 [2876] L494-->L531: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21 1) (= v_~m_st~0_8 0)) InVars {~m_st~0=v_~m_st~0_8} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21, ~m_st~0=v_~m_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 5256881#L531 [4276] L531-->L546: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 5256878#L546 [3757] L546-->L546-1: Formula: (> v_ULTIMATE.start_eval_~tmp~0_4 0) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} OutVars{ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} AuxVars[] AssignedVars[] 5256874#L546-1 [3164] L546-1-->L554: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_2 |v_ULTIMATE.start_eval_#t~nondet1_3|) (= 0 v_~m_st~0_10)) InVars {~m_st~0=v_~m_st~0_10, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_3|} OutVars{ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_2|, ~m_st~0=v_~m_st~0_10, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_1~0] 5256871#L554 [2472] L554-->L551: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} AuxVars[] AssignedVars[] 5256869#L551 [2690] L551-->L568: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_2~0_2 |v_ULTIMATE.start_eval_#t~nondet2_3|) (= 0 v_~t1_st~0_11)) InVars {~t1_st~0=v_~t1_st~0_11, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_3|} OutVars{ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_2|, ~t1_st~0=v_~t1_st~0_11, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_2~0] 5203012#L568 [3161] L568-->L565: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_2~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_5} AuxVars[] AssignedVars[] 5234380#L565 [2469] L565-->L582: Formula: (and (= v_~t2_st~0_12 0) (= v_ULTIMATE.start_eval_~tmp_ndt_3~0_2 |v_ULTIMATE.start_eval_#t~nondet3_3|)) InVars {ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_3|, ~t2_st~0=v_~t2_st~0_12} OutVars{ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_2|, ~t2_st~0=v_~t2_st~0_12, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_~tmp_ndt_3~0] 5234377#L582 [2901] L582-->L579: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_3~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_5} AuxVars[] AssignedVars[] 5234376#L579 [3158] L579-->L596: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_4~0_2 |v_ULTIMATE.start_eval_#t~nondet4_3|) (= 0 v_~t3_st~0_14)) InVars {ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_3|, ~t3_st~0=v_~t3_st~0_14} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_2|, ~t3_st~0=v_~t3_st~0_14, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_~tmp_ndt_4~0] 5234372#L596 [2608] L596-->L593: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_4~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_5} AuxVars[] AssignedVars[] 5234370#L593 [2898] L593-->L610: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_5~0_2 |v_ULTIMATE.start_eval_#t~nondet5_3|) (= 0 v_~t4_st~0_16)) InVars {ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_3|, ~t4_st~0=v_~t4_st~0_16} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_2, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_2|, ~t4_st~0=v_~t4_st~0_16} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_#t~nondet5] 5215916#L610 [2390] L610-->L607: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_5~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_5} AuxVars[] AssignedVars[] 5234366#L607 [2626] L607-->L624: Formula: (and (= v_~t5_st~0_17 0) (= v_ULTIMATE.start_eval_~tmp_ndt_6~0_2 |v_ULTIMATE.start_eval_#t~nondet6_3|)) InVars {ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_3|, ~t5_st~0=v_~t5_st~0_17} OutVars{ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_2, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_2|, ~t5_st~0=v_~t5_st~0_17} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_eval_#t~nondet6] 5234089#L624 [3318] L624-->L621: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_6~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_5} AuxVars[] AssignedVars[] 5159289#L621 [3830] L621-->L635: Formula: (> 0 v_~t6_st~0_21) InVars {~t6_st~0=v_~t6_st~0_21} OutVars{~t6_st~0=v_~t6_st~0_21} AuxVars[] AssignedVars[] 5159288#L635 [2020-06-22 00:15:35,096 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:15:35,096 INFO L82 PathProgramCache]: Analyzing trace with hash 218945922, now seen corresponding path program 12 times [2020-06-22 00:15:35,096 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:15:35,096 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:15:35,097 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:15:35,097 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2020-06-22 00:15:35,097 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:15:35,100 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:15:35,103 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:15:35,109 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:15:35,110 INFO L82 PathProgramCache]: Analyzing trace with hash 1587498190, now seen corresponding path program 1 times [2020-06-22 00:15:35,110 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:15:35,110 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:15:35,110 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:15:35,111 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2020-06-22 00:15:35,111 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:15:35,112 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:15:35,113 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:15:35,115 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:15:35,115 INFO L82 PathProgramCache]: Analyzing trace with hash 1094878573, now seen corresponding path program 1 times [2020-06-22 00:15:35,115 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:15:35,115 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:15:35,116 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:15:35,116 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:15:35,116 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:15:35,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-06-22 00:15:35,138 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-06-22 00:15:35,139 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-06-22 00:15:35,139 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-06-22 00:15:35,258 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-06-22 00:15:35,258 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-06-22 00:15:35,258 INFO L87 Difference]: Start difference. First operand 463889 states and 672048 transitions. cyclomatic complexity: 208162 Second operand 3 states. [2020-06-22 00:15:37,030 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-06-22 00:15:37,031 INFO L93 Difference]: Finished difference Result 419273 states and 608144 transitions. [2020-06-22 00:15:37,031 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-06-22 00:15:37,031 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 419273 states and 608144 transitions. [2020-06-22 00:15:39,249 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 419176 [2020-06-22 00:15:40,617 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 419273 states to 419273 states and 608144 transitions. [2020-06-22 00:15:40,618 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 419273 [2020-06-22 00:15:40,945 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 419273 [2020-06-22 00:15:40,945 INFO L73 IsDeterministic]: Start isDeterministic. Operand 419273 states and 608144 transitions. [2020-06-22 00:15:41,220 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-06-22 00:15:41,221 INFO L706 BuchiCegarLoop]: Abstraction has 419273 states and 608144 transitions. [2020-06-22 00:15:41,452 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 419273 states and 608144 transitions. [2020-06-22 00:15:45,865 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 419273 to 419273. [2020-06-22 00:15:45,865 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 419273 states. [2020-06-22 00:15:46,849 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 419273 states to 419273 states and 608144 transitions. [2020-06-22 00:15:46,850 INFO L729 BuchiCegarLoop]: Abstraction has 419273 states and 608144 transitions. [2020-06-22 00:15:46,850 INFO L609 BuchiCegarLoop]: Abstraction has 419273 states and 608144 transitions. [2020-06-22 00:15:46,850 INFO L442 BuchiCegarLoop]: ======== Iteration 58============ [2020-06-22 00:15:46,850 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 419273 states and 608144 transitions. [2020-06-22 00:15:48,622 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 419176 [2020-06-22 00:15:48,622 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-06-22 00:15:48,622 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-06-22 00:15:48,623 INFO L867 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:15:48,624 INFO L868 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-06-22 00:15:48,625 INFO L794 eck$LassoCheckResult]: Stem: 5866472#ULTIMATE.startENTRY [4266] ULTIMATE.startENTRY-->L444: Formula: (and (= 1 v_~t6_i~0_7) (= 2 v_~E_3~0_38) (= 0 v_~t2_pc~0_26) (= 0 v_~t4_pc~0_26) (= 2 v_~E_5~0_38) (= v_~t5_st~0_24 0) (= 2 v_~E_2~0_38) (= v_~M_E~0_37 2) (= v_~t5_pc~0_26 0) (= v_~T4_E~0_18 2) (= v_~t4_i~0_7 1) (= v_ULTIMATE.start_start_simulation_~kernel_st~0_10 0) (= v_~T1_E~0_18 2) (= 2 v_~E_1~0_38) (= v_~m_i~0_7 1) (= 1 v_~t1_i~0_7) (= v_~t3_pc~0_26 0) (= 2 v_~T5_E~0_18) (= v_~t3_i~0_7 1) (= 0 v_~t4_st~0_24) (= 0 v_~t6_pc~0_26) (= 1 v_~t2_i~0_7) (= v_~m_pc~0_26 0) (= 2 v_~E_6~0_38) (= v_~t5_i~0_7 1) (= v_~t1_pc~0_26 0) (= 2 v_~T2_E~0_18) (= 0 v_~t3_st~0_24) (= 2 v_~T3_E~0_18) (= v_~T6_E~0_18 2) (= 0 v_~t1_st~0_24) (= 2 v_~E_4~0_38) (= 0 v_~t6_st~0_24) (= 0 v_~m_st~0_24) (= v_~t2_st~0_24 0)) InVars {} OutVars{~t6_pc~0=v_~t6_pc~0_26, ~t5_i~0=v_~t5_i~0_7, ~t1_pc~0=v_~t1_pc~0_26, ~t5_st~0=v_~t5_st~0_24, ~T6_E~0=v_~T6_E~0_18, ~M_E~0=v_~M_E~0_37, ~t4_pc~0=v_~t4_pc~0_26, ~t2_i~0=v_~t2_i~0_7, ~T3_E~0=v_~T3_E~0_18, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_10, ~t3_i~0=v_~t3_i~0_7, ~E_1~0=v_~E_1~0_38, ~E_5~0=v_~E_5~0_38, ~T1_E~0=v_~T1_E~0_18, ~E_3~0=v_~E_3~0_38, ULTIMATE.start_start_simulation_#t~ret16=|v_ULTIMATE.start_start_simulation_#t~ret16_4|, ~T4_E~0=v_~T4_E~0_18, ULTIMATE.start_start_simulation_#t~ret17=|v_ULTIMATE.start_start_simulation_#t~ret17_4|, ~t6_i~0=v_~t6_i~0_7, ~t2_st~0=v_~t2_st~0_24, ~t2_pc~0=v_~t2_pc~0_26, ULTIMATE.start_main_~__retres1~8=v_ULTIMATE.start_main_~__retres1~8_6, ~T2_E~0=v_~T2_E~0_18, ~t6_st~0=v_~t6_st~0_24, ~t1_st~0=v_~t1_st~0_24, ~T5_E~0=v_~T5_E~0_18, ~t4_i~0=v_~t4_i~0_7, ~t5_pc~0=v_~t5_pc~0_26, ~m_i~0=v_~m_i~0_7, ULTIMATE.start_start_simulation_~tmp___0~1=v_ULTIMATE.start_start_simulation_~tmp___0~1_7, ULTIMATE.start_start_simulation_~tmp~3=v_ULTIMATE.start_start_simulation_~tmp~3_7, ~t4_st~0=v_~t4_st~0_24, ~E_4~0=v_~E_4~0_38, ~t3_st~0=v_~t3_st~0_24, ~t3_pc~0=v_~t3_pc~0_26, ~E_6~0=v_~E_6~0_38, ULTIMATE.start_main_#res=|v_ULTIMATE.start_main_#res_5|, ~E_2~0=v_~E_2~0_38, ~t1_i~0=v_~t1_i~0_7, ~m_st~0=v_~m_st~0_24, ~m_pc~0=v_~m_pc~0_26} AuxVars[] AssignedVars[~t6_pc~0, ~t5_i~0, ~t1_pc~0, ~t5_st~0, ~T6_E~0, ~M_E~0, ~t4_pc~0, ~t2_i~0, ~T3_E~0, ULTIMATE.start_start_simulation_~kernel_st~0, ~t3_i~0, ~E_1~0, ~E_5~0, ~T1_E~0, ~E_3~0, ULTIMATE.start_start_simulation_#t~ret16, ~T4_E~0, ULTIMATE.start_start_simulation_#t~ret17, ~t6_i~0, ~t2_st~0, ~t2_pc~0, ULTIMATE.start_main_~__retres1~8, ~T2_E~0, ~t6_st~0, ~t1_st~0, ~T5_E~0, ~t4_i~0, ~t5_pc~0, ~m_i~0, ULTIMATE.start_start_simulation_~tmp___0~1, ULTIMATE.start_start_simulation_~tmp~3, ~t4_st~0, ~E_4~0, ~t3_st~0, ~t3_pc~0, ~E_6~0, ULTIMATE.start_main_#res, ~E_2~0, ~t1_i~0, ~m_st~0, ~m_pc~0] 5866047#L444 [2453] L444-->L451-1: Formula: (and (= v_~m_i~0_3 1) (= v_~m_st~0_2 0)) InVars {~m_i~0=v_~m_i~0_3} OutVars{~m_st~0=v_~m_st~0_2, ~m_i~0=v_~m_i~0_3} AuxVars[] AssignedVars[~m_st~0] 5866048#L451-1 [3030] L451-1-->L456-1: Formula: (and (= v_~t1_st~0_2 0) (= 1 v_~t1_i~0_3)) InVars {~t1_i~0=v_~t1_i~0_3} OutVars{~t1_st~0=v_~t1_st~0_2, ~t1_i~0=v_~t1_i~0_3} AuxVars[] AssignedVars[~t1_st~0] 5866136#L456-1 [2574] L456-1-->L461-1: Formula: (and (= v_~t2_st~0_2 0) (= 1 v_~t2_i~0_3)) InVars {~t2_i~0=v_~t2_i~0_3} OutVars{~t2_i~0=v_~t2_i~0_3, ~t2_st~0=v_~t2_st~0_2} AuxVars[] AssignedVars[~t2_st~0] 5866137#L461-1 [2880] L461-1-->L466-1: Formula: (and (= v_~t3_st~0_3 0) (= v_~t3_i~0_3 1)) InVars {~t3_i~0=v_~t3_i~0_3} OutVars{~t3_st~0=v_~t3_st~0_3, ~t3_i~0=v_~t3_i~0_3} AuxVars[] AssignedVars[~t3_st~0] 5866051#L466-1 [2457] L466-1-->L471-1: Formula: (and (= v_~t4_i~0_3 1) (= v_~t4_st~0_4 0)) InVars {~t4_i~0=v_~t4_i~0_3} OutVars{~t4_i~0=v_~t4_i~0_3, ~t4_st~0=v_~t4_st~0_4} AuxVars[] AssignedVars[~t4_st~0] 5866052#L471-1 [3209] L471-1-->L476-1: Formula: (and (= v_~t5_st~0_4 0) (= v_~t5_i~0_3 1)) InVars {~t5_i~0=v_~t5_i~0_3} OutVars{~t5_i~0=v_~t5_i~0_3, ~t5_st~0=v_~t5_st~0_4} AuxVars[] AssignedVars[~t5_st~0] 5866303#L476-1 [2761] L476-1-->L481-1: Formula: (and (= 1 v_~t6_i~0_3) (= v_~t6_st~0_4 0)) InVars {~t6_i~0=v_~t6_i~0_3} OutVars{~t6_st~0=v_~t6_st~0_4, ~t6_i~0=v_~t6_i~0_3} AuxVars[] AssignedVars[~t6_st~0] 5866304#L481-1 [3652] L481-1-->L660-1: Formula: (< 0 v_~M_E~0_7) InVars {~M_E~0=v_~M_E~0_7} OutVars{~M_E~0=v_~M_E~0_7} AuxVars[] AssignedVars[] 5866494#L660-1 [3654] L660-1-->L665-1: Formula: (< 0 v_~T1_E~0_4) InVars {~T1_E~0=v_~T1_E~0_4} OutVars{~T1_E~0=v_~T1_E~0_4} AuxVars[] AssignedVars[] 5865970#L665-1 [3655] L665-1-->L670-1: Formula: (< 0 v_~T2_E~0_4) InVars {~T2_E~0=v_~T2_E~0_4} OutVars{~T2_E~0=v_~T2_E~0_4} AuxVars[] AssignedVars[] 5865971#L670-1 [3658] L670-1-->L675-1: Formula: (> v_~T3_E~0_4 0) InVars {~T3_E~0=v_~T3_E~0_4} OutVars{~T3_E~0=v_~T3_E~0_4} AuxVars[] AssignedVars[] 5866058#L675-1 [3659] L675-1-->L680-1: Formula: (> v_~T4_E~0_4 0) InVars {~T4_E~0=v_~T4_E~0_4} OutVars{~T4_E~0=v_~T4_E~0_4} AuxVars[] AssignedVars[] 5866059#L680-1 [3661] L680-1-->L685-1: Formula: (> v_~T5_E~0_4 0) InVars {~T5_E~0=v_~T5_E~0_4} OutVars{~T5_E~0=v_~T5_E~0_4} AuxVars[] AssignedVars[] 5866315#L685-1 [3663] L685-1-->L690-1: Formula: (< 0 v_~T6_E~0_4) InVars {~T6_E~0=v_~T6_E~0_4} OutVars{~T6_E~0=v_~T6_E~0_4} AuxVars[] AssignedVars[] 5866316#L690-1 [3665] L690-1-->L695-1: Formula: (> v_~E_1~0_6 0) InVars {~E_1~0=v_~E_1~0_6} OutVars{~E_1~0=v_~E_1~0_6} AuxVars[] AssignedVars[] 5866176#L695-1 [3668] L695-1-->L700-1: Formula: (> v_~E_2~0_6 0) InVars {~E_2~0=v_~E_2~0_6} OutVars{~E_2~0=v_~E_2~0_6} AuxVars[] AssignedVars[] 5866177#L700-1 [3670] L700-1-->L705-1: Formula: (> v_~E_3~0_6 0) InVars {~E_3~0=v_~E_3~0_6} OutVars{~E_3~0=v_~E_3~0_6} AuxVars[] AssignedVars[] 5866453#L705-1 [3672] L705-1-->L710-1: Formula: (> v_~E_4~0_4 0) InVars {~E_4~0=v_~E_4~0_4} OutVars{~E_4~0=v_~E_4~0_4} AuxVars[] AssignedVars[] 5866116#L710-1 [3674] L710-1-->L715-1: Formula: (> v_~E_5~0_4 0) InVars {~E_5~0=v_~E_5~0_4} OutVars{~E_5~0=v_~E_5~0_4} AuxVars[] AssignedVars[] 5866117#L715-1 [3675] L715-1-->L720-1: Formula: (> v_~E_6~0_4 0) InVars {~E_6~0=v_~E_6~0_4} OutVars{~E_6~0=v_~E_6~0_4} AuxVars[] AssignedVars[] 5866005#L720-1 [2412] L720-1-->L310: Formula: true InVars {} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_7, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_7, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_4|, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_4|, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_4|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_7, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_4, ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_4, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_2|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_2|, ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_4|, ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_4|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_7, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_2|, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_7, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_4} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_is_master_triggered_~__retres1~0, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_is_master_triggered_#res, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_activate_threads_~tmp___5~0, ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___2~0, ULTIMATE.start_activate_threads_~tmp___4~0] 5866006#L310 [3678] L310-->L310-2: Formula: (< v_~m_pc~0_5 1) InVars {~m_pc~0=v_~m_pc~0_5} OutVars{~m_pc~0=v_~m_pc~0_5} AuxVars[] AssignedVars[] 5866149#L310-2 [2805] L310-2-->L321: Formula: (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_11 0) InVars {} OutVars{ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_11} AuxVars[] AssignedVars[ULTIMATE.start_is_master_triggered_~__retres1~0] 5866144#L321 [4267] L321-->L815: Formula: (and (= v_ULTIMATE.start_is_master_triggered_~__retres1~0_49 |v_ULTIMATE.start_is_master_triggered_#res_28|) (= |v_ULTIMATE.start_is_master_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp~1_49)) InVars {ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_49, ULTIMATE.start_activate_threads_#t~ret8=|v_ULTIMATE.start_activate_threads_#t~ret8_28|, ULTIMATE.start_is_master_triggered_~__retres1~0=v_ULTIMATE.start_is_master_triggered_~__retres1~0_49, ULTIMATE.start_is_master_triggered_#res=|v_ULTIMATE.start_is_master_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp~1, ULTIMATE.start_activate_threads_#t~ret8, ULTIMATE.start_is_master_triggered_#res] 5866145#L815 [2976] L815-->L815-2: Formula: (= 0 v_ULTIMATE.start_activate_threads_~tmp~1_12) InVars {ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} OutVars{ULTIMATE.start_activate_threads_~tmp~1=v_ULTIMATE.start_activate_threads_~tmp~1_12} AuxVars[] AssignedVars[] 5866449#L815-2 [2961] L815-2-->L329: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_7, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1, ULTIMATE.start_is_transmit1_triggered_#res] 5866372#L329 [3683] L329-->L329-2: Formula: (< v_~t1_pc~0_5 1) InVars {~t1_pc~0=v_~t1_pc~0_5} OutVars{~t1_pc~0=v_~t1_pc~0_5} AuxVars[] AssignedVars[] 5866373#L329-2 [2861] L329-2-->L340: Formula: (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit1_triggered_~__retres1~1] 5866368#L340 [4268] L340-->L823: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___0~0_49 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55 |v_ULTIMATE.start_is_transmit1_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55} OutVars{ULTIMATE.start_is_transmit1_triggered_~__retres1~1=v_ULTIMATE.start_is_transmit1_triggered_~__retres1~1_55, ULTIMATE.start_activate_threads_#t~ret9=|v_ULTIMATE.start_activate_threads_#t~ret9_28|, ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_49, ULTIMATE.start_is_transmit1_triggered_#res=|v_ULTIMATE.start_is_transmit1_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret9, ULTIMATE.start_activate_threads_~tmp___0~0, ULTIMATE.start_is_transmit1_triggered_#res] 5866369#L823 [3234] L823-->L823-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___0~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___0~0=v_ULTIMATE.start_activate_threads_~tmp___0~0_12} AuxVars[] AssignedVars[] 5866595#L823-2 [3235] L823-2-->L348: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_4|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_#res, ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 5866559#L348 [3690] L348-->L348-2: Formula: (< v_~t2_pc~0_5 1) InVars {~t2_pc~0=v_~t2_pc~0_5} OutVars{~t2_pc~0=v_~t2_pc~0_5} AuxVars[] AssignedVars[] 5866561#L348-2 [3153] L348-2-->L359: Formula: (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit2_triggered_~__retres1~2] 5866556#L359 [4269] L359-->L831: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___1~0_49 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55 |v_ULTIMATE.start_is_transmit2_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} OutVars{ULTIMATE.start_activate_threads_#t~ret10=|v_ULTIMATE.start_activate_threads_#t~ret10_28|, ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_49, ULTIMATE.start_is_transmit2_triggered_#res=|v_ULTIMATE.start_is_transmit2_triggered_#res_28|, ULTIMATE.start_is_transmit2_triggered_~__retres1~2=v_ULTIMATE.start_is_transmit2_triggered_~__retres1~2_55} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret10, ULTIMATE.start_activate_threads_~tmp___1~0, ULTIMATE.start_is_transmit2_triggered_#res] 5866126#L831 [2537] L831-->L831-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___1~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___1~0=v_ULTIMATE.start_activate_threads_~tmp___1~0_12} AuxVars[] AssignedVars[] 5866111#L831-2 [2520] L831-2-->L367: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_4|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 5866054#L367 [3695] L367-->L367-2: Formula: (> 1 v_~t3_pc~0_5) InVars {~t3_pc~0=v_~t3_pc~0_5} OutVars{~t3_pc~0=v_~t3_pc~0_5} AuxVars[] AssignedVars[] 5866035#L367-2 [2438] L367-2-->L378: Formula: (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit3_triggered_~__retres1~3] 5866036#L378 [4270] L378-->L839: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___2~0_49 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55 |v_ULTIMATE.start_is_transmit3_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55} OutVars{ULTIMATE.start_activate_threads_#t~ret11=|v_ULTIMATE.start_activate_threads_#t~ret11_28|, ULTIMATE.start_is_transmit3_triggered_#res=|v_ULTIMATE.start_is_transmit3_triggered_#res_28|, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=v_ULTIMATE.start_is_transmit3_triggered_~__retres1~3_55, ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_49} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_#t~ret11, ULTIMATE.start_is_transmit3_triggered_#res, ULTIMATE.start_activate_threads_~tmp___2~0] 5866053#L839 [2791] L839-->L839-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___2~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___2~0=v_ULTIMATE.start_activate_threads_~tmp___2~0_12} AuxVars[] AssignedVars[] 5866328#L839-2 [2794] L839-2-->L386: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_7, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_4|} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4, ULTIMATE.start_is_transmit4_triggered_#res] 5866233#L386 [3702] L386-->L386-2: Formula: (< v_~t4_pc~0_5 1) InVars {~t4_pc~0=v_~t4_pc~0_5} OutVars{~t4_pc~0=v_~t4_pc~0_5} AuxVars[] AssignedVars[] 5866234#L386-2 [2680] L386-2-->L397: Formula: (= v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit4_triggered_~__retres1~4] 5866231#L397 [4271] L397-->L847: Formula: (and (= |v_ULTIMATE.start_is_transmit4_triggered_#res_28| v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55) (= v_ULTIMATE.start_activate_threads_~tmp___3~0_49 |v_ULTIMATE.start_is_transmit4_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_49, ULTIMATE.start_is_transmit4_triggered_~__retres1~4=v_ULTIMATE.start_is_transmit4_triggered_~__retres1~4_55, ULTIMATE.start_activate_threads_#t~ret12=|v_ULTIMATE.start_activate_threads_#t~ret12_28|, ULTIMATE.start_is_transmit4_triggered_#res=|v_ULTIMATE.start_is_transmit4_triggered_#res_28|} AuxVars[] AssignedVars[ULTIMATE.start_activate_threads_~tmp___3~0, ULTIMATE.start_activate_threads_#t~ret12, ULTIMATE.start_is_transmit4_triggered_#res] 5866232#L847 [3084] L847-->L847-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___3~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___3~0=v_ULTIMATE.start_activate_threads_~tmp___3~0_12} AuxVars[] AssignedVars[] 5866505#L847-2 [3064] L847-2-->L405: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_4|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 5866506#L405 [3708] L405-->L405-2: Formula: (> 1 v_~t5_pc~0_5) InVars {~t5_pc~0=v_~t5_pc~0_5} OutVars{~t5_pc~0=v_~t5_pc~0_5} AuxVars[] AssignedVars[] 5866399#L405-2 [2940] L405-2-->L416: Formula: (= v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_~__retres1~5] 5866435#L416 [4272] L416-->L855: Formula: (and (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55) (= |v_ULTIMATE.start_is_transmit5_triggered_#res_28| v_ULTIMATE.start_activate_threads_~tmp___4~0_49)) InVars {ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55} OutVars{ULTIMATE.start_is_transmit5_triggered_#res=|v_ULTIMATE.start_is_transmit5_triggered_#res_28|, ULTIMATE.start_activate_threads_#t~ret13=|v_ULTIMATE.start_activate_threads_#t~ret13_28|, ULTIMATE.start_is_transmit5_triggered_~__retres1~5=v_ULTIMATE.start_is_transmit5_triggered_~__retres1~5_55, ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit5_triggered_#res, ULTIMATE.start_activate_threads_#t~ret13, ULTIMATE.start_activate_threads_~tmp___4~0] 5866518#L855 [3091] L855-->L855-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___4~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___4~0=v_ULTIMATE.start_activate_threads_~tmp___4~0_12} AuxVars[] AssignedVars[] 5866519#L855-2 [3093] L855-2-->L424: Formula: true InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_4|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_7} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 5866096#L424 [3713] L424-->L424-2: Formula: (< v_~t6_pc~0_5 1) InVars {~t6_pc~0=v_~t6_pc~0_5} OutVars{~t6_pc~0=v_~t6_pc~0_5} AuxVars[] AssignedVars[] 5866097#L424-2 [2503] L424-2-->L435: Formula: (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11 0) InVars {} OutVars{ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_11} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_~__retres1~6] 5866093#L435 [4273] L435-->L863: Formula: (and (= v_ULTIMATE.start_activate_threads_~tmp___5~0_49 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|) (= v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55 |v_ULTIMATE.start_is_transmit6_triggered_#res_28|)) InVars {ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55} OutVars{ULTIMATE.start_is_transmit6_triggered_#res=|v_ULTIMATE.start_is_transmit6_triggered_#res_28|, ULTIMATE.start_is_transmit6_triggered_~__retres1~6=v_ULTIMATE.start_is_transmit6_triggered_~__retres1~6_55, ULTIMATE.start_activate_threads_#t~ret14=|v_ULTIMATE.start_activate_threads_#t~ret14_28|, ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_49} AuxVars[] AssignedVars[ULTIMATE.start_is_transmit6_triggered_#res, ULTIMATE.start_activate_threads_#t~ret14, ULTIMATE.start_activate_threads_~tmp___5~0] 5866019#L863 [2425] L863-->L863-2: Formula: (= v_ULTIMATE.start_activate_threads_~tmp___5~0_12 0) InVars {ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} OutVars{ULTIMATE.start_activate_threads_~tmp___5~0=v_ULTIMATE.start_activate_threads_~tmp___5~0_12} AuxVars[] AssignedVars[] 5865992#L863-2 [3719] L863-2-->L733-1: Formula: (> v_~M_E~0_15 1) InVars {~M_E~0=v_~M_E~0_15} OutVars{~M_E~0=v_~M_E~0_15} AuxVars[] AssignedVars[] 5865993#L733-1 [3722] L733-1-->L738-1: Formula: (> v_~T1_E~0_10 1) InVars {~T1_E~0=v_~T1_E~0_10} OutVars{~T1_E~0=v_~T1_E~0_10} AuxVars[] AssignedVars[] 5866451#L738-1 [3723] L738-1-->L743-1: Formula: (< 1 v_~T2_E~0_10) InVars {~T2_E~0=v_~T2_E~0_10} OutVars{~T2_E~0=v_~T2_E~0_10} AuxVars[] AssignedVars[] 5866114#L743-1 [3726] L743-1-->L748-1: Formula: (< 1 v_~T3_E~0_10) InVars {~T3_E~0=v_~T3_E~0_10} OutVars{~T3_E~0=v_~T3_E~0_10} AuxVars[] AssignedVars[] 5866115#L748-1 [3728] L748-1-->L753-1: Formula: (> v_~T4_E~0_10 1) InVars {~T4_E~0=v_~T4_E~0_10} OutVars{~T4_E~0=v_~T4_E~0_10} AuxVars[] AssignedVars[] 5866000#L753-1 [3729] L753-1-->L758-1: Formula: (< 1 v_~T5_E~0_10) InVars {~T5_E~0=v_~T5_E~0_10} OutVars{~T5_E~0=v_~T5_E~0_10} AuxVars[] AssignedVars[] 5866001#L758-1 [3731] L758-1-->L763-1: Formula: (> v_~T6_E~0_10 1) InVars {~T6_E~0=v_~T6_E~0_10} OutVars{~T6_E~0=v_~T6_E~0_10} AuxVars[] AssignedVars[] 5866069#L763-1 [3733] L763-1-->L768-1: Formula: (< 1 v_~E_1~0_14) InVars {~E_1~0=v_~E_1~0_14} OutVars{~E_1~0=v_~E_1~0_14} AuxVars[] AssignedVars[] 5866070#L768-1 [3736] L768-1-->L773-1: Formula: (< 1 v_~E_2~0_14) InVars {~E_2~0=v_~E_2~0_14} OutVars{~E_2~0=v_~E_2~0_14} AuxVars[] AssignedVars[] 5866306#L773-1 [3737] L773-1-->L778-1: Formula: (< 1 v_~E_3~0_14) InVars {~E_3~0=v_~E_3~0_14} OutVars{~E_3~0=v_~E_3~0_14} AuxVars[] AssignedVars[] 5866307#L778-1 [3740] L778-1-->L783-1: Formula: (< 1 v_~E_4~0_14) InVars {~E_4~0=v_~E_4~0_14} OutVars{~E_4~0=v_~E_4~0_14} AuxVars[] AssignedVars[] 5866168#L783-1 [3741] L783-1-->L788-1: Formula: (< 1 v_~E_5~0_14) InVars {~E_5~0=v_~E_5~0_14} OutVars{~E_5~0=v_~E_5~0_14} AuxVars[] AssignedVars[] 5866169#L788-1 [3744] L788-1-->L1014-1: Formula: (< 1 v_~E_6~0_14) InVars {~E_6~0=v_~E_6~0_14} OutVars{~E_6~0=v_~E_6~0_14} AuxVars[] AssignedVars[] 5866578#L1014-1 [4274] L1014-1-->L635: Formula: (= v_ULTIMATE.start_start_simulation_~kernel_st~0_11 1) InVars {} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_6, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_6, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_6, ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_4|, ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_4|, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_4|, ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_6, ULTIMATE.start_start_simulation_~kernel_st~0=v_ULTIMATE.start_start_simulation_~kernel_st~0_11, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_4|, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_6, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_6, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_4|, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_4|, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_4|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_6, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_4|, ULTIMATE.start_eval_~tmp_ndt_7~0=v_ULTIMATE.start_eval_~tmp_ndt_7~0_6} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_~tmp_ndt_2~0, ULTIMATE.start_eval_~tmp_ndt_3~0, ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_start_simulation_~kernel_st~0, ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_4~0, ULTIMATE.start_eval_~tmp_ndt_1~0, ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_#t~nondet6, ULTIMATE.start_eval_#t~nondet5, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0, ULTIMATE.start_eval_~tmp_ndt_7~0] 6043645#L635 [2020-06-22 00:15:48,625 INFO L796 eck$LassoCheckResult]: Loop: 6043645#L635 [4275] L635-->L494: Formula: true InVars {} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_10|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_37} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_exists_runnable_thread_~__retres1~7] 6070824#L494 [2876] L494-->L531: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21 1) (= v_~m_st~0_8 0)) InVars {~m_st~0=v_~m_st~0_8} OutVars{ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_21, ~m_st~0=v_~m_st~0_8} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_~__retres1~7] 6070821#L531 [4276] L531-->L546: Formula: (and (= v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38 |v_ULTIMATE.start_exists_runnable_thread_#res_11|) (= v_ULTIMATE.start_eval_~tmp~0_7 |v_ULTIMATE.start_exists_runnable_thread_#res_11|)) InVars {ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} OutVars{ULTIMATE.start_exists_runnable_thread_#res=|v_ULTIMATE.start_exists_runnable_thread_#res_11|, ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_7, ULTIMATE.start_eval_#t~ret0=|v_ULTIMATE.start_eval_#t~ret0_5|, ULTIMATE.start_exists_runnable_thread_~__retres1~7=v_ULTIMATE.start_exists_runnable_thread_~__retres1~7_38} AuxVars[] AssignedVars[ULTIMATE.start_exists_runnable_thread_#res, ULTIMATE.start_eval_~tmp~0, ULTIMATE.start_eval_#t~ret0] 6070819#L546 [3757] L546-->L546-1: Formula: (> v_ULTIMATE.start_eval_~tmp~0_4 0) InVars {ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} OutVars{ULTIMATE.start_eval_~tmp~0=v_ULTIMATE.start_eval_~tmp~0_4} AuxVars[] AssignedVars[] 6070815#L546-1 [3164] L546-1-->L554: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_2 |v_ULTIMATE.start_eval_#t~nondet1_3|) (= 0 v_~m_st~0_10)) InVars {~m_st~0=v_~m_st~0_10, ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_3|} OutVars{ULTIMATE.start_eval_#t~nondet1=|v_ULTIMATE.start_eval_#t~nondet1_2|, ~m_st~0=v_~m_st~0_10, ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet1, ULTIMATE.start_eval_~tmp_ndt_1~0] 6070810#L554 [2472] L554-->L551: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_1~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_1~0=v_ULTIMATE.start_eval_~tmp_ndt_1~0_5} AuxVars[] AssignedVars[] 6070808#L551 [2690] L551-->L568: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_2~0_2 |v_ULTIMATE.start_eval_#t~nondet2_3|) (= 0 v_~t1_st~0_11)) InVars {~t1_st~0=v_~t1_st~0_11, ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_3|} OutVars{ULTIMATE.start_eval_#t~nondet2=|v_ULTIMATE.start_eval_#t~nondet2_2|, ~t1_st~0=v_~t1_st~0_11, ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet2, ULTIMATE.start_eval_~tmp_ndt_2~0] 6067478#L568 [3161] L568-->L565: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_2~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_2~0=v_ULTIMATE.start_eval_~tmp_ndt_2~0_5} AuxVars[] AssignedVars[] 6070806#L565 [2469] L565-->L582: Formula: (and (= v_~t2_st~0_12 0) (= v_ULTIMATE.start_eval_~tmp_ndt_3~0_2 |v_ULTIMATE.start_eval_#t~nondet3_3|)) InVars {ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_3|, ~t2_st~0=v_~t2_st~0_12} OutVars{ULTIMATE.start_eval_#t~nondet3=|v_ULTIMATE.start_eval_#t~nondet3_2|, ~t2_st~0=v_~t2_st~0_12, ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet3, ULTIMATE.start_eval_~tmp_ndt_3~0] 6070798#L582 [2901] L582-->L579: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_3~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_3~0=v_ULTIMATE.start_eval_~tmp_ndt_3~0_5} AuxVars[] AssignedVars[] 6063729#L579 [3158] L579-->L596: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_4~0_2 |v_ULTIMATE.start_eval_#t~nondet4_3|) (= 0 v_~t3_st~0_14)) InVars {ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_3|, ~t3_st~0=v_~t3_st~0_14} OutVars{ULTIMATE.start_eval_#t~nondet4=|v_ULTIMATE.start_eval_#t~nondet4_2|, ~t3_st~0=v_~t3_st~0_14, ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_2} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet4, ULTIMATE.start_eval_~tmp_ndt_4~0] 6063726#L596 [2608] L596-->L593: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_4~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_4~0=v_ULTIMATE.start_eval_~tmp_ndt_4~0_5} AuxVars[] AssignedVars[] 6063723#L593 [2898] L593-->L610: Formula: (and (= v_ULTIMATE.start_eval_~tmp_ndt_5~0_2 |v_ULTIMATE.start_eval_#t~nondet5_3|) (= 0 v_~t4_st~0_16)) InVars {ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_3|, ~t4_st~0=v_~t4_st~0_16} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_2, ULTIMATE.start_eval_#t~nondet5=|v_ULTIMATE.start_eval_#t~nondet5_2|, ~t4_st~0=v_~t4_st~0_16} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_5~0, ULTIMATE.start_eval_#t~nondet5] 6063720#L610 [2390] L610-->L607: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_5~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_5~0=v_ULTIMATE.start_eval_~tmp_ndt_5~0_5} AuxVars[] AssignedVars[] 6063721#L607 [2626] L607-->L624: Formula: (and (= v_~t5_st~0_17 0) (= v_ULTIMATE.start_eval_~tmp_ndt_6~0_2 |v_ULTIMATE.start_eval_#t~nondet6_3|)) InVars {ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_3|, ~t5_st~0=v_~t5_st~0_17} OutVars{ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_2, ULTIMATE.start_eval_#t~nondet6=|v_ULTIMATE.start_eval_#t~nondet6_2|, ~t5_st~0=v_~t5_st~0_17} AuxVars[] AssignedVars[ULTIMATE.start_eval_~tmp_ndt_6~0, ULTIMATE.start_eval_#t~nondet6] 6151761#L624 [3318] L624-->L621: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_6~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_6~0=v_ULTIMATE.start_eval_~tmp_ndt_6~0_5} AuxVars[] AssignedVars[] 6043646#L621 [2386] L621-->L638: Formula: (and (= 0 v_~t6_st~0_18) (= v_ULTIMATE.start_eval_~tmp_ndt_7~0_2 |v_ULTIMATE.start_eval_#t~nondet7_3|)) InVars {~t6_st~0=v_~t6_st~0_18, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_3|} OutVars{~t6_st~0=v_~t6_st~0_18, ULTIMATE.start_eval_~tmp_ndt_7~0=v_ULTIMATE.start_eval_~tmp_ndt_7~0_2, ULTIMATE.start_eval_#t~nondet7=|v_ULTIMATE.start_eval_#t~nondet7_2|} AuxVars[] AssignedVars[ULTIMATE.start_eval_#t~nondet7, ULTIMATE.start_eval_~tmp_ndt_7~0] 6043644#L638 [3045] L638-->L635: Formula: (= v_ULTIMATE.start_eval_~tmp_ndt_7~0_5 0) InVars {ULTIMATE.start_eval_~tmp_ndt_7~0=v_ULTIMATE.start_eval_~tmp_ndt_7~0_5} OutVars{ULTIMATE.start_eval_~tmp_ndt_7~0=v_ULTIMATE.start_eval_~tmp_ndt_7~0_5} AuxVars[] AssignedVars[] 6043645#L635 [2020-06-22 00:15:48,625 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:15:48,625 INFO L82 PathProgramCache]: Analyzing trace with hash 218945922, now seen corresponding path program 13 times [2020-06-22 00:15:48,626 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:15:48,626 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:15:48,626 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:15:48,626 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:15:48,626 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:15:48,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:15:48,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:15:48,639 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:15:48,639 INFO L82 PathProgramCache]: Analyzing trace with hash 1967761915, now seen corresponding path program 1 times [2020-06-22 00:15:48,639 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:15:48,639 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:15:48,640 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:15:48,640 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:15:48,640 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:15:48,642 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:15:48,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:15:48,644 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-06-22 00:15:48,645 INFO L82 PathProgramCache]: Analyzing trace with hash -418544324, now seen corresponding path program 1 times [2020-06-22 00:15:48,645 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2020-06-22 00:15:48,645 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2020-06-22 00:15:48,645 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:15:48,646 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-06-22 00:15:48,646 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2020-06-22 00:15:48,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:15:48,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-06-22 00:15:48,781 WARN L188 SmtUtils]: Spent 115.00 ms on a formula simplification. DAG size of input: 52 DAG size of output: 51 [2020-06-22 00:15:49,403 WARN L188 SmtUtils]: Spent 569.00 ms on a formula simplification. DAG size of input: 172 DAG size of output: 132 [2020-06-22 00:15:49,563 WARN L188 SmtUtils]: Spent 157.00 ms on a formula simplification that was a NOOP. DAG size: 116 [2020-06-22 00:15:49,606 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 22.06 12:15:49 BasicIcfg [2020-06-22 00:15:49,607 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2020-06-22 00:15:49,607 INFO L168 Benchmark]: Toolchain (without parser) took 173589.71 ms. Allocated memory was 649.6 MB in the beginning and 11.1 GB in the end (delta: 10.4 GB). Free memory was 558.8 MB in the beginning and 5.1 GB in the end (delta: -4.5 GB). Peak memory consumption was 5.9 GB. Max. memory is 50.3 GB. [2020-06-22 00:15:49,608 INFO L168 Benchmark]: CDTParser took 0.17 ms. Allocated memory is still 649.6 MB. Free memory is still 580.4 MB. There was no memory consumed. Max. memory is 50.3 GB. [2020-06-22 00:15:49,608 INFO L168 Benchmark]: CACSL2BoogieTranslator took 434.50 ms. Allocated memory was 649.6 MB in the beginning and 674.8 MB in the end (delta: 25.2 MB). Free memory was 558.8 MB in the beginning and 627.3 MB in the end (delta: -68.5 MB). Peak memory consumption was 33.1 MB. Max. memory is 50.3 GB. [2020-06-22 00:15:49,609 INFO L168 Benchmark]: Boogie Procedure Inliner took 82.16 ms. Allocated memory is still 674.8 MB. Free memory was 627.3 MB in the beginning and 619.2 MB in the end (delta: 8.2 MB). Peak memory consumption was 8.2 MB. Max. memory is 50.3 GB. [2020-06-22 00:15:49,610 INFO L168 Benchmark]: Boogie Preprocessor took 72.16 ms. Allocated memory is still 674.8 MB. Free memory was 619.2 MB in the beginning and 612.4 MB in the end (delta: 6.7 MB). Peak memory consumption was 6.7 MB. Max. memory is 50.3 GB. [2020-06-22 00:15:49,610 INFO L168 Benchmark]: RCFGBuilder took 1352.50 ms. Allocated memory is still 674.8 MB. Free memory was 612.4 MB in the beginning and 460.2 MB in the end (delta: 152.2 MB). Peak memory consumption was 152.2 MB. Max. memory is 50.3 GB. [2020-06-22 00:15:49,610 INFO L168 Benchmark]: BlockEncodingV2 took 378.94 ms. Allocated memory is still 674.8 MB. Free memory was 460.2 MB in the beginning and 391.4 MB in the end (delta: 68.8 MB). Peak memory consumption was 68.8 MB. Max. memory is 50.3 GB. [2020-06-22 00:15:49,611 INFO L168 Benchmark]: TraceAbstraction took 411.50 ms. Allocated memory was 674.8 MB in the beginning and 760.7 MB in the end (delta: 86.0 MB). Free memory was 390.1 MB in the beginning and 657.7 MB in the end (delta: -267.6 MB). Peak memory consumption was 31.1 MB. Max. memory is 50.3 GB. [2020-06-22 00:15:49,612 INFO L168 Benchmark]: BuchiAutomizer took 170852.37 ms. Allocated memory was 760.7 MB in the beginning and 11.1 GB in the end (delta: 10.3 GB). Free memory was 657.7 MB in the beginning and 5.1 GB in the end (delta: -4.4 GB). Peak memory consumption was 5.9 GB. Max. memory is 50.3 GB. [2020-06-22 00:15:49,616 INFO L337 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.plugins.blockencoding: - StatisticsResult: Initial Icfg 611 locations, 944 edges - StatisticsResult: Encoded RCFG 518 locations, 1143 edges * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.17 ms. Allocated memory is still 649.6 MB. Free memory is still 580.4 MB. There was no memory consumed. Max. memory is 50.3 GB. * CACSL2BoogieTranslator took 434.50 ms. Allocated memory was 649.6 MB in the beginning and 674.8 MB in the end (delta: 25.2 MB). Free memory was 558.8 MB in the beginning and 627.3 MB in the end (delta: -68.5 MB). Peak memory consumption was 33.1 MB. Max. memory is 50.3 GB. * Boogie Procedure Inliner took 82.16 ms. Allocated memory is still 674.8 MB. Free memory was 627.3 MB in the beginning and 619.2 MB in the end (delta: 8.2 MB). Peak memory consumption was 8.2 MB. Max. memory is 50.3 GB. * Boogie Preprocessor took 72.16 ms. Allocated memory is still 674.8 MB. Free memory was 619.2 MB in the beginning and 612.4 MB in the end (delta: 6.7 MB). Peak memory consumption was 6.7 MB. Max. memory is 50.3 GB. * RCFGBuilder took 1352.50 ms. Allocated memory is still 674.8 MB. Free memory was 612.4 MB in the beginning and 460.2 MB in the end (delta: 152.2 MB). Peak memory consumption was 152.2 MB. Max. memory is 50.3 GB. * BlockEncodingV2 took 378.94 ms. Allocated memory is still 674.8 MB. Free memory was 460.2 MB in the beginning and 391.4 MB in the end (delta: 68.8 MB). Peak memory consumption was 68.8 MB. Max. memory is 50.3 GB. * TraceAbstraction took 411.50 ms. Allocated memory was 674.8 MB in the beginning and 760.7 MB in the end (delta: 86.0 MB). Free memory was 390.1 MB in the beginning and 657.7 MB in the end (delta: -267.6 MB). Peak memory consumption was 31.1 MB. Max. memory is 50.3 GB. * BuchiAutomizer took 170852.37 ms. Allocated memory was 760.7 MB in the beginning and 11.1 GB in the end (delta: 10.3 GB). Free memory was 657.7 MB in the beginning and 5.1 GB in the end (delta: -4.4 GB). Peak memory consumption was 5.9 GB. Max. memory is 50.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - AllSpecificationsHoldResult: All specifications hold We were not able to verify any specifiation because the program does not contain any specification. - InvariantResult [Line: 175]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 328]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 541]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 656]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 328]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 1]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 328]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 309]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 309]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 309]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 328]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 328]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 733]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 328]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 60]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 328]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 328]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 1]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 656]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 328]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 347]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 347]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 984]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 347]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 347]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 347]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 541]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 347]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 366]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 366]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 171]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 366]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 347]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 541]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 347]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 347]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 366]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 541]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 366]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 546]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 366]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 210]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 366]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 729]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 366]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 1033]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 385]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 385]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 1033]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 1]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 385]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 451]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 385]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 385]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 366]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 404]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 404]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 385]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 385]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 385]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 541]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 105]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 385]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 404]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 404]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 541]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 404]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 404]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 206]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 404]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 423]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 101]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 423]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 423]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 729]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 423]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 404]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 404]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 423]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 423]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 423]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 423]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 423]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 241]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 245]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: -1]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 493]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 493]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 493]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 60]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 136]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 733]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 140]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 896]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 309]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 1]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 1]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 660]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 1]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 309]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 309]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 309]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 1]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 309]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 541]: Loop Invariant Derived loop invariant: 1 - InvariantResult [Line: 309]: Loop Invariant Derived loop invariant: 1 - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 518 locations, 0 error locations. SAFE Result, 0.3s OverallTime, 0 OverallIterations, 0 TraceHistogramMax, 0.0s AutomataDifference, 0.0s DeadEndRemovalTime, 0.2s HoareAnnotationTime, HoareTripleCheckerStatistics: No data available, PredicateUnifierStatistics: No data available, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=518occurred in iteration=0, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: No data available, HoareAnnotationStatistics: 0.0s HoareAnnotationTime, 106 LocationsWithAnnotation, 106 PreInvPairs, 106 NumberOfFragments, 106 HoareAnnotationTreeSize, 106 FomulaSimplifications, 0 FormulaSimplificationTreeSizeReduction, 0.1s HoareSimplificationTime, 106 FomulaSimplificationsInter, 0 FormulaSimplificationTreeSizeReductionInter, 0.0s HoareSimplificationTimeInter, RefinementEngineStatistics: No data available, ReuseStatistics: No data available - StatisticsResult: Constructed decomposition of program Your program was decomposed into 57 terminating modules (57 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.57 modules have a trivial ranking function, the largest among these consists of 6 locations. The remainder module has 419273 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 170.7s and 58 iterations. TraceHistogramMax:1. Analysis of lassos took 6.0s. Construction of modules took 30.9s. Büchi inclusion checks took 21.9s. Highest rank in rank-based complementation 0. Minimization of det autom 57. Minimization of nondet autom 0. Automata minimization 59.5s AutomataMinimizationTime, 57 MinimizatonAttempts, 55874 StatesRemovedByMinimization, 22 NontrivialMinimizations. Non-live state removal took 29.5s Buchi closure took 2.2s. Biggest automaton had 463954 states and ocurred in iteration 54. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 27126 SDtfs, 85458 SDslu, 35562 SDs, 0 SdLazy, 50391 SolverSat, 1265 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 30.9s Time LassoAnalysisResults: nont1 unkn0 SFLI9 SFLT0 conc12 concLT0 SILN5 SILU0 SILI31 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 541]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {} State at position 1 is {__retres1=0, t3_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@44c74785=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@287a75e7=0, tmp=1, t5_i=1, __retres1=0, kernel_st=1, \result=0, t2_st=0, t4_i=1, E_3=2, t4_pc=0, E_5=2, T6_E=2, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7993e7c2=0, E_1=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5c38b669=0, tmp_ndt_2=0, \result=0, __retres1=0, \result=0, tmp_ndt_4=0, tmp_ndt_6=0, m_st=0, t6_pc=0, tmp___2=0, tmp___0=0, t3_pc=0, tmp=0, __retres1=0, \result=0, t6_i=1, m_pc=0, tmp___4=0, \result=0, __retres1=0, t6_st=0, E_6=2, \result=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@626a6df6=0, \result=0, T2_E=2, tmp___0=0, t1_pc=0, __retres1=1, t5_st=0, E_2=2, E_4=2, T1_E=2, tmp_ndt_1=0, M_E=2, tmp=0, tmp_ndt_3=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@393581a4=0, __retres1=0, T5_E=2, t2_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4e350961=0, T4_E=2, t3_i=1, t4_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5b988b17=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@18cf4ff0=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@27a48830=0, t1_st=0, tmp_ndt_5=0, t5_pc=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2f019b1a=0, t2_pc=0, tmp_ndt_7=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4dd3ed9f=0, tmp___3=0, tmp___1=0, T3_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3a70815d=0, t1_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7840980a=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2b66c4d1=0, \result=1, tmp___5=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@18fe55fc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7566891e=0} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 541]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int t3_pc = 0; [L19] int t4_pc = 0; [L20] int t5_pc = 0; [L21] int t6_pc = 0; [L22] int m_st ; [L23] int t1_st ; [L24] int t2_st ; [L25] int t3_st ; [L26] int t4_st ; [L27] int t5_st ; [L28] int t6_st ; [L29] int m_i ; [L30] int t1_i ; [L31] int t2_i ; [L32] int t3_i ; [L33] int t4_i ; [L34] int t5_i ; [L35] int t6_i ; [L36] int M_E = 2; [L37] int T1_E = 2; [L38] int T2_E = 2; [L39] int T3_E = 2; [L40] int T4_E = 2; [L41] int T5_E = 2; [L42] int T6_E = 2; [L43] int E_1 = 2; [L44] int E_2 = 2; [L45] int E_3 = 2; [L46] int E_4 = 2; [L47] int E_5 = 2; [L48] int E_6 = 2; [L1059] int __retres1 ; [L969] m_i = 1 [L970] t1_i = 1 [L971] t2_i = 1 [L972] t3_i = 1 [L973] t4_i = 1 [L974] t5_i = 1 [L975] t6_i = 1 [L1000] int kernel_st ; [L1001] int tmp ; [L1002] int tmp___0 ; [L1006] kernel_st = 0 [L451] COND TRUE m_i == 1 [L452] m_st = 0 [L456] COND TRUE t1_i == 1 [L457] t1_st = 0 [L461] COND TRUE t2_i == 1 [L462] t2_st = 0 [L466] COND TRUE t3_i == 1 [L467] t3_st = 0 [L471] COND TRUE t4_i == 1 [L472] t4_st = 0 [L476] COND TRUE t5_i == 1 [L477] t5_st = 0 [L481] COND TRUE t6_i == 1 [L482] t6_st = 0 [L660] COND FALSE !(M_E == 0) [L665] COND FALSE !(T1_E == 0) [L670] COND FALSE !(T2_E == 0) [L675] COND FALSE !(T3_E == 0) [L680] COND FALSE !(T4_E == 0) [L685] COND FALSE !(T5_E == 0) [L690] COND FALSE !(T6_E == 0) [L695] COND FALSE !(E_1 == 0) [L700] COND FALSE !(E_2 == 0) [L705] COND FALSE !(E_3 == 0) [L710] COND FALSE !(E_4 == 0) [L715] COND FALSE !(E_5 == 0) [L720] COND FALSE !(E_6 == 0) [L803] int tmp ; [L804] int tmp___0 ; [L805] int tmp___1 ; [L806] int tmp___2 ; [L807] int tmp___3 ; [L808] int tmp___4 ; [L809] int tmp___5 ; [L307] int __retres1 ; [L310] COND FALSE !(m_pc == 1) [L320] __retres1 = 0 [L322] return (__retres1); [L813] tmp = is_master_triggered() [L815] COND FALSE !(\read(tmp)) [L326] int __retres1 ; [L329] COND FALSE !(t1_pc == 1) [L339] __retres1 = 0 [L341] return (__retres1); [L821] tmp___0 = is_transmit1_triggered() [L823] COND FALSE !(\read(tmp___0)) [L345] int __retres1 ; [L348] COND FALSE !(t2_pc == 1) [L358] __retres1 = 0 [L360] return (__retres1); [L829] tmp___1 = is_transmit2_triggered() [L831] COND FALSE !(\read(tmp___1)) [L364] int __retres1 ; [L367] COND FALSE !(t3_pc == 1) [L377] __retres1 = 0 [L379] return (__retres1); [L837] tmp___2 = is_transmit3_triggered() [L839] COND FALSE !(\read(tmp___2)) [L383] int __retres1 ; [L386] COND FALSE !(t4_pc == 1) [L396] __retres1 = 0 [L398] return (__retres1); [L845] tmp___3 = is_transmit4_triggered() [L847] COND FALSE !(\read(tmp___3)) [L402] int __retres1 ; [L405] COND FALSE !(t5_pc == 1) [L415] __retres1 = 0 [L417] return (__retres1); [L853] tmp___4 = is_transmit5_triggered() [L855] COND FALSE !(\read(tmp___4)) [L421] int __retres1 ; [L424] COND FALSE !(t6_pc == 1) [L434] __retres1 = 0 [L436] return (__retres1); [L861] tmp___5 = is_transmit6_triggered() [L863] COND FALSE !(\read(tmp___5)) [L733] COND FALSE !(M_E == 1) [L738] COND FALSE !(T1_E == 1) [L743] COND FALSE !(T2_E == 1) [L748] COND FALSE !(T3_E == 1) [L753] COND FALSE !(T4_E == 1) [L758] COND FALSE !(T5_E == 1) [L763] COND FALSE !(T6_E == 1) [L768] COND FALSE !(E_1 == 1) [L773] COND FALSE !(E_2 == 1) [L778] COND FALSE !(E_3 == 1) [L783] COND FALSE !(E_4 == 1) [L788] COND FALSE !(E_5 == 1) [L793] COND FALSE !(E_6 == 1) [L1014] COND TRUE 1 [L1017] kernel_st = 1 [L537] int tmp ; Loop: [L541] COND TRUE 1 [L491] int __retres1 ; [L494] COND TRUE m_st == 0 [L495] __retres1 = 1 [L532] return (__retres1); [L544] tmp = exists_runnable_thread() [L546] COND TRUE \read(tmp) [L551] COND TRUE m_st == 0 [L552] int tmp_ndt_1; [L553] tmp_ndt_1 = __VERIFIER_nondet_int() [L554] COND FALSE !(\read(tmp_ndt_1)) [L565] COND TRUE t1_st == 0 [L566] int tmp_ndt_2; [L567] tmp_ndt_2 = __VERIFIER_nondet_int() [L568] COND FALSE !(\read(tmp_ndt_2)) [L579] COND TRUE t2_st == 0 [L580] int tmp_ndt_3; [L581] tmp_ndt_3 = __VERIFIER_nondet_int() [L582] COND FALSE !(\read(tmp_ndt_3)) [L593] COND TRUE t3_st == 0 [L594] int tmp_ndt_4; [L595] tmp_ndt_4 = __VERIFIER_nondet_int() [L596] COND FALSE !(\read(tmp_ndt_4)) [L607] COND TRUE t4_st == 0 [L608] int tmp_ndt_5; [L609] tmp_ndt_5 = __VERIFIER_nondet_int() [L610] COND FALSE !(\read(tmp_ndt_5)) [L621] COND TRUE t5_st == 0 [L622] int tmp_ndt_6; [L623] tmp_ndt_6 = __VERIFIER_nondet_int() [L624] COND FALSE !(\read(tmp_ndt_6)) [L635] COND TRUE t6_st == 0 [L636] int tmp_ndt_7; [L637] tmp_ndt_7 = __VERIFIER_nondet_int() [L638] COND FALSE !(\read(tmp_ndt_7)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! !SESSION 2020-06-22 00:12:52.768 ----------------------------------------------- eclipse.buildId=unknown java.version=1.8.0_242 java.vendor=Oracle Corporation BootLoader constants: OS=linux, ARCH=x86_64, WS=gtk, NL=en_US Framework arguments: -tc ./../AutomizerAndBuchiAutomizerCInlineWithBlockEncoding.xml -s ./../termcomp2017.epf -i /export/starexec/sandbox/benchmark/theBenchmark.c Command-line arguments: -os linux -ws gtk -arch x86_64 -consoleLog -data @user.home/.ultimate -tc ./../AutomizerAndBuchiAutomizerCInlineWithBlockEncoding.xml -s ./../termcomp2017.epf -data /export/starexec/sandbox/tmp -i /export/starexec/sandbox/benchmark/theBenchmark.c !ENTRY org.eclipse.core.resources 2 10035 2020-06-22 00:15:49.873 !MESSAGE The workspace will exit with unsaved changes in this session. Received shutdown request... Ultimate: GTK+ Version Check