/export/starexec/sandbox/solver/bin/starexec_run_tc20-std.sh /export/starexec/sandbox/benchmark/theBenchmark.xml /export/starexec/sandbox/output/output_files


--------------------------------------------------------------------------------


YES
**************************************************
summary
**************************************************
SRS with 15 rules on 8 letters       DP
SRS with 25 strict rules and 15 weak rules on 14 letters       weights
SRS with 6 strict rules and 15 weak rules on 11 letters       EDG
3 sub-proofs
  1 SRS with 2 strict rules and 15 weak rules on 9 letters       Matrix   { monotone = Weak, domain = Arctic, shape = Full, bits = 5, dim = 2, solver = Minisatapi, verbose = False, tracing = False}
  SRS with 1 strict rules and 15 weak rules on 9 letters       EDG
  SRS with 1 strict rules and 15 weak rules on 9 letters       Matrix   { monotone = Weak, domain = Arctic, shape = Full, bits = 5, dim = 2, solver = Minisatapi, verbose = False, tracing = False}
  SRS with 0 strict rules and 15 weak rules on 8 letters       EDG
  
  2 SRS with 2 strict rules and 15 weak rules on 9 letters       Matrix   { monotone = Weak, domain = Arctic, shape = Full, bits = 5, dim = 2, solver = Minisatapi, verbose = False, tracing = False}
  SRS with 1 strict rules and 15 weak rules on 9 letters       EDG
  SRS with 1 strict rules and 15 weak rules on 9 letters       Matrix   { monotone = Weak, domain = Arctic, shape = Full, bits = 5, dim = 2, solver = Minisatapi, verbose = False, tracing = False}
  SRS with 0 strict rules and 15 weak rules on 8 letters       EDG
  
  3 SRS with 2 strict rules and 15 weak rules on 9 letters       Matrix   { monotone = Weak, domain = Arctic, shape = Full, bits = 5, dim = 2, solver = Minisatapi, verbose = False, tracing = False}
  SRS with 0 strict rules and 15 weak rules on 8 letters       EDG
  
**************************************************
proof
**************************************************
property Termination
has value Just True
for SRS
  [r0, 0] -> [0, r0] {- Input 0 -}
  [r0, 1] -> [1, r0] {- Input 1 -}
  [r0, m] -> [m, r0] {- Input 2 -}
  [r1, 0] -> [0, r1] {- Input 3 -}
  [r1, 1] -> [1, r1] {- Input 4 -}
  [r1, m] -> [m, r1] {- Input 5 -}
  [r0, b] -> [qr, 0, b] {- Input 6 -}
  [r1, b] -> [qr, 1, b] {- Input 7 -}
  [0, qr] -> [qr, 0] {- Input 8 -}
  [1, qr] -> [qr, 1] {- Input 9 -}
  [m, qr] -> [ql, m] {- Input 10 -}
  [0, ql] -> [ql, 0] {- Input 11 -}
  [1, ql] -> [ql, 1] {- Input 12 -}
  [b, ql, 0] -> [0, b, r0] {- Input 13 -}
  [b, ql, 1] -> [1, b, r1] {- Input 14 -}
reason
  DP
   property Termination
has value Just True
for SRS
  [r0, 0] ->= [0, r0] {- DP Nontop (Input 0) -}
  [r0, 1] ->= [1, r0] {- DP Nontop (Input 1) -}
  [r0, m] ->= [m, r0] {- DP Nontop (Input 2) -}
  [r1, 0] ->= [0, r1] {- DP Nontop (Input 3) -}
  [r1, 1] ->= [1, r1] {- DP Nontop (Input 4) -}
  [r1, m] ->= [m, r1] {- DP Nontop (Input 5) -}
  [r0, b] ->= [qr, 0, b] {- DP Nontop (Input 6) -}
  [r1, b] ->= [qr, 1, b] {- DP Nontop (Input 7) -}
  [0, qr] ->= [qr, 0] {- DP Nontop (Input 8) -}
  [1, qr] ->= [qr, 1] {- DP Nontop (Input 9) -}
  [m, qr] ->= [ql, m] {- DP Nontop (Input 10) -}
  [0, ql] ->= [ql, 0] {- DP Nontop (Input 11) -}
  [1, ql] ->= [ql, 1] {- DP Nontop (Input 12) -}
  [b, ql, 0] ->= [0, b, r0] {- DP Nontop (Input 13) -}
  [b, ql, 1] ->= [1, b, r1] {- DP Nontop (Input 14) -}
  [r0#, 0] |-> [r0#] {- DP (Top 1) (Input 0) -}
  [r0#, 0] |-> [0#, r0] {- DP (Top 0) (Input 0) -}
  [r0#, 1] |-> [r0#] {- DP (Top 1) (Input 1) -}
  [r0#, 1] |-> [1#, r0] {- DP (Top 0) (Input 1) -}
  [r0#, m] |-> [r0#] {- DP (Top 1) (Input 2) -}
  [r0#, m] |-> [m#, r0] {- DP (Top 0) (Input 2) -}
  [r0#, b] |-> [0#, b] {- DP (Top 1) (Input 6) -}
  [0#, qr] |-> [0#] {- DP (Top 1) (Input 8) -}
  [0#, ql] |-> [0#] {- DP (Top 1) (Input 11) -}
  [1#, qr] |-> [1#] {- DP (Top 1) (Input 9) -}
  [1#, ql] |-> [1#] {- DP (Top 1) (Input 12) -}
  [m#, qr] |-> [m#] {- DP (Top 1) (Input 10) -}
  [r1#, 0] |-> [0#, r1] {- DP (Top 0) (Input 3) -}
  [r1#, 0] |-> [r1#] {- DP (Top 1) (Input 3) -}
  [r1#, 1] |-> [1#, r1] {- DP (Top 0) (Input 4) -}
  [r1#, 1] |-> [r1#] {- DP (Top 1) (Input 4) -}
  [r1#, m] |-> [m#, r1] {- DP (Top 0) (Input 5) -}
  [r1#, m] |-> [r1#] {- DP (Top 1) (Input 5) -}
  [r1#, b] |-> [1#, b] {- DP (Top 1) (Input 7) -}
  [b#, ql, 0] |-> [r0#] {- DP (Top 2) (Input 13) -}
  [b#, ql, 0] |-> [0#, b, r0] {- DP (Top 0) (Input 13) -}
  [b#, ql, 0] |-> [b#, r0] {- DP (Top 1) (Input 13) -}
  [b#, ql, 1] |-> [1#, b, r1] {- DP (Top 0) (Input 14) -}
  [b#, ql, 1] |-> [r1#] {- DP (Top 2) (Input 14) -}
  [b#, ql, 1] |-> [b#, r1] {- DP (Top 1) (Input 14) -}
reason
  (r0, 1/5)
  (m, 2/1)
  (r1, 1/5)
  (qr, 1/5)
  (ql, 1/5)
  (r0#, 6/5)
  (r1#, 6/5)
  (b#, 2/1)
   property Termination
has value Just True
for SRS
  [r0, 0] ->= [0, r0] {- DP Nontop (Input 0) -}
  [r0, 1] ->= [1, r0] {- DP Nontop (Input 1) -}
  [r0, m] ->= [m, r0] {- DP Nontop (Input 2) -}
  [r1, 0] ->= [0, r1] {- DP Nontop (Input 3) -}
  [r1, 1] ->= [1, r1] {- DP Nontop (Input 4) -}
  [r1, m] ->= [m, r1] {- DP Nontop (Input 5) -}
  [r0, b] ->= [qr, 0, b] {- DP Nontop (Input 6) -}
  [r1, b] ->= [qr, 1, b] {- DP Nontop (Input 7) -}
  [0, qr] ->= [qr, 0] {- DP Nontop (Input 8) -}
  [1, qr] ->= [qr, 1] {- DP Nontop (Input 9) -}
  [m, qr] ->= [ql, m] {- DP Nontop (Input 10) -}
  [0, ql] ->= [ql, 0] {- DP Nontop (Input 11) -}
  [1, ql] ->= [ql, 1] {- DP Nontop (Input 12) -}
  [b, ql, 0] ->= [0, b, r0] {- DP Nontop (Input 13) -}
  [b, ql, 1] ->= [1, b, r1] {- DP Nontop (Input 14) -}
  [r0#, 0] |-> [r0#] {- DP (Top 1) (Input 0) -}
  [r0#, 1] |-> [r0#] {- DP (Top 1) (Input 1) -}
  [r1#, 0] |-> [r1#] {- DP (Top 1) (Input 3) -}
  [r1#, 1] |-> [r1#] {- DP (Top 1) (Input 4) -}
  [b#, ql, 0] |-> [b#, r0] {- DP (Top 1) (Input 13) -}
  [b#, ql, 1] |-> [b#, r1] {- DP (Top 1) (Input 14) -}
reason
  EDG
   property Termination
has value Just True
for SRS
  [r0#, 0] |-> [r0#] {- DP (Top 1) (Input 0) -}
  [r0#, 1] |-> [r0#] {- DP (Top 1) (Input 1) -}
  [r0, 0] ->= [0, r0] {- DP Nontop (Input 0) -}
  [r0, 1] ->= [1, r0] {- DP Nontop (Input 1) -}
  [r0, m] ->= [m, r0] {- DP Nontop (Input 2) -}
  [r1, 0] ->= [0, r1] {- DP Nontop (Input 3) -}
  [r1, 1] ->= [1, r1] {- DP Nontop (Input 4) -}
  [r1, m] ->= [m, r1] {- DP Nontop (Input 5) -}
  [r0, b] ->= [qr, 0, b] {- DP Nontop (Input 6) -}
  [r1, b] ->= [qr, 1, b] {- DP Nontop (Input 7) -}
  [0, qr] ->= [qr, 0] {- DP Nontop (Input 8) -}
  [1, qr] ->= [qr, 1] {- DP Nontop (Input 9) -}
  [m, qr] ->= [ql, m] {- DP Nontop (Input 10) -}
  [0, ql] ->= [ql, 0] {- DP Nontop (Input 11) -}
  [1, ql] ->= [ql, 1] {- DP Nontop (Input 12) -}
  [b, ql, 0] ->= [0, b, r0] {- DP Nontop (Input 13) -}
  [b, ql, 1] ->= [1, b, r1] {- DP Nontop (Input 14) -}
reason
  ( r0
  , Wk  / 0A -  \
        \ -  0A / )
  ( 0
  , Wk  / 7A 9A \
        \ -  0A / )
  ( 1
  , Wk  / 0A 0A \
        \ -  0A / )
  ( m
  , Wk  / - 16A \
        \ - 0A  / )
  ( r1
  , Wk  / 0A -  \
        \ -  0A / )
  ( b
  , Wk  / 13A 15A \
        \ -   0A  / )
  ( qr
  , Wk  / - 8A \
        \ - 0A / )
  ( ql
  , Wk  / 0A 0A \
        \ -  0A / )
  ( r0#
  , Wk  / 24A -  \
        \ -   0A / )
   property Termination
has value Just True
for SRS
  [r0#, 1] |-> [r0#] {- DP (Top 1) (Input 1) -}
  [r0, 0] ->= [0, r0] {- DP Nontop (Input 0) -}
  [r0, 1] ->= [1, r0] {- DP Nontop (Input 1) -}
  [r0, m] ->= [m, r0] {- DP Nontop (Input 2) -}
  [r1, 0] ->= [0, r1] {- DP Nontop (Input 3) -}
  [r1, 1] ->= [1, r1] {- DP Nontop (Input 4) -}
  [r1, m] ->= [m, r1] {- DP Nontop (Input 5) -}
  [r0, b] ->= [qr, 0, b] {- DP Nontop (Input 6) -}
  [r1, b] ->= [qr, 1, b] {- DP Nontop (Input 7) -}
  [0, qr] ->= [qr, 0] {- DP Nontop (Input 8) -}
  [1, qr] ->= [qr, 1] {- DP Nontop (Input 9) -}
  [m, qr] ->= [ql, m] {- DP Nontop (Input 10) -}
  [0, ql] ->= [ql, 0] {- DP Nontop (Input 11) -}
  [1, ql] ->= [ql, 1] {- DP Nontop (Input 12) -}
  [b, ql, 0] ->= [0, b, r0] {- DP Nontop (Input 13) -}
  [b, ql, 1] ->= [1, b, r1] {- DP Nontop (Input 14) -}
reason
  EDG
   property Termination
has value Just True
for SRS
  [r0#, 1] |-> [r0#] {- DP (Top 1) (Input 1) -}
  [r0, 0] ->= [0, r0] {- DP Nontop (Input 0) -}
  [r0, 1] ->= [1, r0] {- DP Nontop (Input 1) -}
  [r0, m] ->= [m, r0] {- DP Nontop (Input 2) -}
  [r1, 0] ->= [0, r1] {- DP Nontop (Input 3) -}
  [r1, 1] ->= [1, r1] {- DP Nontop (Input 4) -}
  [r1, m] ->= [m, r1] {- DP Nontop (Input 5) -}
  [r0, b] ->= [qr, 0, b] {- DP Nontop (Input 6) -}
  [r1, b] ->= [qr, 1, b] {- DP Nontop (Input 7) -}
  [0, qr] ->= [qr, 0] {- DP Nontop (Input 8) -}
  [1, qr] ->= [qr, 1] {- DP Nontop (Input 9) -}
  [m, qr] ->= [ql, m] {- DP Nontop (Input 10) -}
  [0, ql] ->= [ql, 0] {- DP Nontop (Input 11) -}
  [1, ql] ->= [ql, 1] {- DP Nontop (Input 12) -}
  [b, ql, 0] ->= [0, b, r0] {- DP Nontop (Input 13) -}
  [b, ql, 1] ->= [1, b, r1] {- DP Nontop (Input 14) -}
reason
  ( r0
  , Wk  / 0A 1A \
        \ -  0A / )
  ( 0
  , Wk  / 10A 16A \
        \ -   0A  / )
  ( 1
  , Wk  / 1A 7A \
        \ -  0A / )
  ( m
  , Wk  / - 17A \
        \ - 0A  / )
  ( r1
  , Wk  / 0A 6A \
        \ -  0A / )
  ( b
  , Wk  / 14A 21A \
        \ -   0A  / )
  ( qr
  , Wk  / - 4A \
        \ - 0A / )
  ( ql
  , Wk  / 0A 17A \
        \ -  0A  / )
  ( r0#
  , Wk  / 14A 4A \
        \ -   0A / )
   property Termination
has value Just True
for SRS
  [r0, 0] ->= [0, r0] {- DP Nontop (Input 0) -}
  [r0, 1] ->= [1, r0] {- DP Nontop (Input 1) -}
  [r0, m] ->= [m, r0] {- DP Nontop (Input 2) -}
  [r1, 0] ->= [0, r1] {- DP Nontop (Input 3) -}
  [r1, 1] ->= [1, r1] {- DP Nontop (Input 4) -}
  [r1, m] ->= [m, r1] {- DP Nontop (Input 5) -}
  [r0, b] ->= [qr, 0, b] {- DP Nontop (Input 6) -}
  [r1, b] ->= [qr, 1, b] {- DP Nontop (Input 7) -}
  [0, qr] ->= [qr, 0] {- DP Nontop (Input 8) -}
  [1, qr] ->= [qr, 1] {- DP Nontop (Input 9) -}
  [m, qr] ->= [ql, m] {- DP Nontop (Input 10) -}
  [0, ql] ->= [ql, 0] {- DP Nontop (Input 11) -}
  [1, ql] ->= [ql, 1] {- DP Nontop (Input 12) -}
  [b, ql, 0] ->= [0, b, r0] {- DP Nontop (Input 13) -}
  [b, ql, 1] ->= [1, b, r1] {- DP Nontop (Input 14) -}
reason
  EDG

property Termination
has value Just True
for SRS
  [r1#, 0] |-> [r1#] {- DP (Top 1) (Input 3) -}
  [r1#, 1] |-> [r1#] {- DP (Top 1) (Input 4) -}
  [r0, 0] ->= [0, r0] {- DP Nontop (Input 0) -}
  [r0, 1] ->= [1, r0] {- DP Nontop (Input 1) -}
  [r0, m] ->= [m, r0] {- DP Nontop (Input 2) -}
  [r1, 0] ->= [0, r1] {- DP Nontop (Input 3) -}
  [r1, 1] ->= [1, r1] {- DP Nontop (Input 4) -}
  [r1, m] ->= [m, r1] {- DP Nontop (Input 5) -}
  [r0, b] ->= [qr, 0, b] {- DP Nontop (Input 6) -}
  [r1, b] ->= [qr, 1, b] {- DP Nontop (Input 7) -}
  [0, qr] ->= [qr, 0] {- DP Nontop (Input 8) -}
  [1, qr] ->= [qr, 1] {- DP Nontop (Input 9) -}
  [m, qr] ->= [ql, m] {- DP Nontop (Input 10) -}
  [0, ql] ->= [ql, 0] {- DP Nontop (Input 11) -}
  [1, ql] ->= [ql, 1] {- DP Nontop (Input 12) -}
  [b, ql, 0] ->= [0, b, r0] {- DP Nontop (Input 13) -}
  [b, ql, 1] ->= [1, b, r1] {- DP Nontop (Input 14) -}
reason
  ( r0
  , Wk  / 0A -  \
        \ -  0A / )
  ( 0
  , Wk  / 7A 9A \
        \ -  0A / )
  ( 1
  , Wk  / 0A 0A \
        \ -  0A / )
  ( m
  , Wk  / - 16A \
        \ - 0A  / )
  ( r1
  , Wk  / 0A -  \
        \ -  0A / )
  ( b
  , Wk  / 13A 15A \
        \ -   0A  / )
  ( qr
  , Wk  / - 8A \
        \ - 0A / )
  ( ql
  , Wk  / 0A 0A \
        \ -  0A / )
  ( r1#
  , Wk  / 24A -  \
        \ -   0A / )
   property Termination
has value Just True
for SRS
  [r1#, 1] |-> [r1#] {- DP (Top 1) (Input 4) -}
  [r0, 0] ->= [0, r0] {- DP Nontop (Input 0) -}
  [r0, 1] ->= [1, r0] {- DP Nontop (Input 1) -}
  [r0, m] ->= [m, r0] {- DP Nontop (Input 2) -}
  [r1, 0] ->= [0, r1] {- DP Nontop (Input 3) -}
  [r1, 1] ->= [1, r1] {- DP Nontop (Input 4) -}
  [r1, m] ->= [m, r1] {- DP Nontop (Input 5) -}
  [r0, b] ->= [qr, 0, b] {- DP Nontop (Input 6) -}
  [r1, b] ->= [qr, 1, b] {- DP Nontop (Input 7) -}
  [0, qr] ->= [qr, 0] {- DP Nontop (Input 8) -}
  [1, qr] ->= [qr, 1] {- DP Nontop (Input 9) -}
  [m, qr] ->= [ql, m] {- DP Nontop (Input 10) -}
  [0, ql] ->= [ql, 0] {- DP Nontop (Input 11) -}
  [1, ql] ->= [ql, 1] {- DP Nontop (Input 12) -}
  [b, ql, 0] ->= [0, b, r0] {- DP Nontop (Input 13) -}
  [b, ql, 1] ->= [1, b, r1] {- DP Nontop (Input 14) -}
reason
  EDG
   property Termination
has value Just True
for SRS
  [r1#, 1] |-> [r1#] {- DP (Top 1) (Input 4) -}
  [r0, 0] ->= [0, r0] {- DP Nontop (Input 0) -}
  [r0, 1] ->= [1, r0] {- DP Nontop (Input 1) -}
  [r0, m] ->= [m, r0] {- DP Nontop (Input 2) -}
  [r1, 0] ->= [0, r1] {- DP Nontop (Input 3) -}
  [r1, 1] ->= [1, r1] {- DP Nontop (Input 4) -}
  [r1, m] ->= [m, r1] {- DP Nontop (Input 5) -}
  [r0, b] ->= [qr, 0, b] {- DP Nontop (Input 6) -}
  [r1, b] ->= [qr, 1, b] {- DP Nontop (Input 7) -}
  [0, qr] ->= [qr, 0] {- DP Nontop (Input 8) -}
  [1, qr] ->= [qr, 1] {- DP Nontop (Input 9) -}
  [m, qr] ->= [ql, m] {- DP Nontop (Input 10) -}
  [0, ql] ->= [ql, 0] {- DP Nontop (Input 11) -}
  [1, ql] ->= [ql, 1] {- DP Nontop (Input 12) -}
  [b, ql, 0] ->= [0, b, r0] {- DP Nontop (Input 13) -}
  [b, ql, 1] ->= [1, b, r1] {- DP Nontop (Input 14) -}
reason
  ( r0
  , Wk  / 0A 1A \
        \ -  0A / )
  ( 0
  , Wk  / 10A 16A \
        \ -   0A  / )
  ( 1
  , Wk  / 1A 7A \
        \ -  0A / )
  ( m
  , Wk  / - 17A \
        \ - 0A  / )
  ( r1
  , Wk  / 0A 6A \
        \ -  0A / )
  ( b
  , Wk  / 14A 21A \
        \ -   0A  / )
  ( qr
  , Wk  / - 4A \
        \ - 0A / )
  ( ql
  , Wk  / 0A 17A \
        \ -  0A  / )
  ( r1#
  , Wk  / 14A 4A \
        \ -   0A / )
   property Termination
has value Just True
for SRS
  [r0, 0] ->= [0, r0] {- DP Nontop (Input 0) -}
  [r0, 1] ->= [1, r0] {- DP Nontop (Input 1) -}
  [r0, m] ->= [m, r0] {- DP Nontop (Input 2) -}
  [r1, 0] ->= [0, r1] {- DP Nontop (Input 3) -}
  [r1, 1] ->= [1, r1] {- DP Nontop (Input 4) -}
  [r1, m] ->= [m, r1] {- DP Nontop (Input 5) -}
  [r0, b] ->= [qr, 0, b] {- DP Nontop (Input 6) -}
  [r1, b] ->= [qr, 1, b] {- DP Nontop (Input 7) -}
  [0, qr] ->= [qr, 0] {- DP Nontop (Input 8) -}
  [1, qr] ->= [qr, 1] {- DP Nontop (Input 9) -}
  [m, qr] ->= [ql, m] {- DP Nontop (Input 10) -}
  [0, ql] ->= [ql, 0] {- DP Nontop (Input 11) -}
  [1, ql] ->= [ql, 1] {- DP Nontop (Input 12) -}
  [b, ql, 0] ->= [0, b, r0] {- DP Nontop (Input 13) -}
  [b, ql, 1] ->= [1, b, r1] {- DP Nontop (Input 14) -}
reason
  EDG

property Termination
has value Just True
for SRS
  [b#, ql, 0] |-> [b#, r0] {- DP (Top 1) (Input 13) -}
  [b#, ql, 1] |-> [b#, r1] {- DP (Top 1) (Input 14) -}
  [r0, 0] ->= [0, r0] {- DP Nontop (Input 0) -}
  [r0, 1] ->= [1, r0] {- DP Nontop (Input 1) -}
  [r0, m] ->= [m, r0] {- DP Nontop (Input 2) -}
  [r1, 0] ->= [0, r1] {- DP Nontop (Input 3) -}
  [r1, 1] ->= [1, r1] {- DP Nontop (Input 4) -}
  [r1, m] ->= [m, r1] {- DP Nontop (Input 5) -}
  [r0, b] ->= [qr, 0, b] {- DP Nontop (Input 6) -}
  [r1, b] ->= [qr, 1, b] {- DP Nontop (Input 7) -}
  [0, qr] ->= [qr, 0] {- DP Nontop (Input 8) -}
  [1, qr] ->= [qr, 1] {- DP Nontop (Input 9) -}
  [m, qr] ->= [ql, m] {- DP Nontop (Input 10) -}
  [0, ql] ->= [ql, 0] {- DP Nontop (Input 11) -}
  [1, ql] ->= [ql, 1] {- DP Nontop (Input 12) -}
  [b, ql, 0] ->= [0, b, r0] {- DP Nontop (Input 13) -}
  [b, ql, 1] ->= [1, b, r1] {- DP Nontop (Input 14) -}
reason
  ( r0
  , Wk  / 0A 16A \
        \ -  0A  / )
  ( 0
  , Wk  / 4A 23A \
        \ -  0A  / )
  ( 1
  , Wk  / 2A 19A \
        \ -  0A  / )
  ( m
  , Wk  / - 4A \
        \ - 0A / )
  ( r1
  , Wk  / 0A 16A \
        \ -  0A  / )
  ( b
  , Wk  / 0A 17A \
        \ -  0A  / )
  ( qr
  , Wk  / - 0A \
        \ - 0A / )
  ( ql
  , Wk  / 0A -  \
        \ -  0A / )
  ( b#
  , Wk  / 8A 26A \
        \ -  0A  / )
   property Termination
has value Just True
for SRS
  [r0, 0] ->= [0, r0] {- DP Nontop (Input 0) -}
  [r0, 1] ->= [1, r0] {- DP Nontop (Input 1) -}
  [r0, m] ->= [m, r0] {- DP Nontop (Input 2) -}
  [r1, 0] ->= [0, r1] {- DP Nontop (Input 3) -}
  [r1, 1] ->= [1, r1] {- DP Nontop (Input 4) -}
  [r1, m] ->= [m, r1] {- DP Nontop (Input 5) -}
  [r0, b] ->= [qr, 0, b] {- DP Nontop (Input 6) -}
  [r1, b] ->= [qr, 1, b] {- DP Nontop (Input 7) -}
  [0, qr] ->= [qr, 0] {- DP Nontop (Input 8) -}
  [1, qr] ->= [qr, 1] {- DP Nontop (Input 9) -}
  [m, qr] ->= [ql, m] {- DP Nontop (Input 10) -}
  [0, ql] ->= [ql, 0] {- DP Nontop (Input 11) -}
  [1, ql] ->= [ql, 1] {- DP Nontop (Input 12) -}
  [b, ql, 0] ->= [0, b, r0] {- DP Nontop (Input 13) -}
  [b, ql, 1] ->= [1, b, r1] {- DP Nontop (Input 14) -}
reason
  EDG

**************************************************
skeleton: (15,8)\Deepee(25/15,14)\Weight(6/15,11)\EDG[(2/15,9)\Matrix{\Arctic}{2}\EDG(1/15,9)\Matrix{\Arctic}{2}(0/15,8)\EDG[],(2/15,9)\Matrix{\Arctic}{2}\EDG(1/15,9)\Matrix{\Arctic}{2}(0/15,8)\EDG[],(2/15,9)\Matrix{\Arctic}{2}(0/15,8)\EDG[]]
**************************************************
let {}
in let {trac = False;done = Worker No_Strict_Rules;mo = Pre (Or_Else Count (IfSizeLeq 10000 GLPK Fail));wop = Or_Else (Worker (Weight {modus = mo})) Pass;weighted = \ m -> And_Then m wop;tiling = \ m w -> weighted (And_Then (Worker (Tiling {method = m,width = w,unlabel = False})) (Worker Remap));when_small = \ m -> And_Then (Worker (SizeAtmost 1000)) m;when_medium = \ m -> And_Then (Worker (SizeAtmost 10000)) m;solver = Minisatapi;qpi = \ dim bits -> weighted (when_small (Worker (QPI {tracing = trac,dim = dim,bits = bits,solver = solver})));matrix = \ dom dim bits -> weighted (when_small (Worker (Matrix {monotone = Weak,domain = dom,dim = dim,bits = bits,tracing = trac,solver = solver})));kbo = \ b -> weighted (when_small (Worker (KBO {bits = b,solver = solver})));mb = Worker (Matchbound {method = RFC,max_size = 100000});remove = First_Of ([ Worker (Weight {modus = mo})] <> ([ Seq [ qpi 2 4, qpi 3 4, qpi 4 4], Seq [ qpi 5 4, qpi 6 3, qpi 7 3]] <> ([ Seq [ matrix Arctic 2 5, matrix Arctic 3 4, matrix Arctic 4 3], Seq [ matrix Natural 2 5, matrix Natural 3 4, matrix Natural 4 3]] <> [ kbo 1, And_Then (Worker Mirror) (And_Then (kbo 1) (Worker Mirror))])));dp = As_Transformer (Apply (And_Then (Worker (DP {tracing = True})) (Worker Remap)) (Apply wop (Branch (Worker (EDG {tracing = True})) remove)));noh = [ Worker (Enumerate {closure = Forward}), Worker (Enumerate {closure = Backward})];yeah = Tree_Search_Preemptive 0 done ([ Worker (Weight {modus = mo}), mb, And_Then (Worker Mirror) mb, dp, And_Then (Worker Mirror) dp, tiling Forward 2, And_Then (Worker Mirror) (tiling Forward 2)] <> [ Worker (Unlabel {verbose = True})])}
  in Apply (Worker Remap) (Seq [ Worker KKST01, First_Of ([ yeah] <> noh)])