/export/starexec/sandbox/solver/bin/starexec_run_standard /export/starexec/sandbox/benchmark/theBenchmark.xml /export/starexec/sandbox/output/output_files


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YES
proof of /export/starexec/sandbox/benchmark/theBenchmark.xml
# AProVE Commit ID: 794c25de1cacf0d048858bcd21c9a779e1221865 marcel 20200619 unpublished dirty


Termination w.r.t. Q of the given QTRS could be proven:

(0) QTRS
(1) QTRS Reverse [EQUIVALENT, 0 ms]
(2) QTRS
(3) RFCMatchBoundsTRSProof [EQUIVALENT, 0 ms]
(4) YES


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(0)
Obligation:
Q restricted rewrite system:
The TRS R consists of the following rules:

   half(0) -> 0
   half(s(0)) -> 0
   half(s(s(x))) -> s(half(x))
   bits(0) -> 0
   bits(s(x)) -> s(bits(half(s(x))))

The set Q consists of the following terms:

   half(0)
   half(s(0))
   half(s(s(x0)))
   bits(0)
   bits(s(x0))


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(1) QTRS Reverse (EQUIVALENT)
We applied the QTRS Reverse Processor [REVERSE].
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(2)
Obligation:
Q restricted rewrite system:
The TRS R consists of the following rules:

   0'(half(x)) -> 0'(x)
   0'(s(half(x))) -> 0'(x)
   s(s(half(x))) -> half(s(x))
   0'(bits(x)) -> 0'(x)
   s(bits(x)) -> s(half(bits(s(x))))

Q is empty.

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(3) RFCMatchBoundsTRSProof (EQUIVALENT)
Termination of the TRS R could be shown with a Match Bound [MATCHBOUNDS1,MATCHBOUNDS2] of 1. This implies Q-termination of R.
The following rules were used to construct the certificate:

   0'(half(x)) -> 0'(x)
   0'(s(half(x))) -> 0'(x)
   s(s(half(x))) -> half(s(x))
   0'(bits(x)) -> 0'(x)
   s(bits(x)) -> s(half(bits(s(x))))

The certificate found is represented by the following graph.
The certificate consists of the following enumerated nodes:
7, 8, 9, 10, 11, 12, 14, 15, 16, 17

Node 7 is start node and node 8 is final node.

Those nodes are connected through the following edges:

* 7 to 8 labelled 0'_1(0), 0'_1(1)* 7 to 9 labelled half_1(0)* 7 to 10 labelled s_1(0)* 8 to 8 labelled #_1(0)* 9 to 8 labelled s_1(0)* 9 to 14 labelled half_1(1)* 9 to 15 labelled s_1(1)* 10 to 11 labelled half_1(0)* 11 to 12 labelled bits_1(0)* 12 to 8 labelled s_1(0)* 12 to 14 labelled half_1(1)* 12 to 15 labelled s_1(1)* 14 to 8 labelled s_1(1)* 14 to 14 labelled half_1(1)* 14 to 15 labelled s_1(1)* 15 to 16 labelled half_1(1)* 16 to 17 labelled bits_1(1)* 17 to 8 labelled s_1(1)* 17 to 14 labelled half_1(1)* 17 to 15 labelled s_1(1)


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(4)
YES