details

property	value
status	complete
benchmark	size-11-alpha-3-num-18.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n038.star.cs.uiowa.edu
space	Waldmann_07_size11

run statistics

property	value
solver	AProVE
configuration	standard
runtime (wallclock)	2.2119 seconds
cpu usage	5.50534
user time	5.24638
system time	0.258957
max virtual memory	1.9008992E7
max residence set size	549904.0

stage attributes

key	value
starexec-result	NO

output

4.79/2.02 NO 5.36/2.16 proof of /export/starexec/sandbox2/benchmark/theBenchmark.xml 5.36/2.16 # AProVE Commit ID: 48fb2092695e11cc9f56e44b17a92a5f88ffb256 marcel 20180622 unpublished dirty 5.36/2.16 5.36/2.16 5.36/2.16 Termination w.r.t. Q of the given QTRS could be disproven: 5.36/2.16 5.36/2.16 (0) QTRS 5.36/2.16 (1) NonTerminationProof [COMPLETE, 174 ms] 5.36/2.16 (2) NO 5.36/2.16 5.36/2.16 5.36/2.16 ---------------------------------------- 5.36/2.16 5.36/2.16 (0) 5.36/2.16 Obligation: 5.36/2.16 Q restricted rewrite system: 5.36/2.16 The TRS R consists of the following rules: 5.36/2.16 5.36/2.16 a(x1) -> x1 5.36/2.16 a(b(x1)) -> b(a(c(b(a(x1))))) 5.36/2.16 b(x1) -> x1 5.36/2.16 c(c(x1)) -> x1 5.36/2.16 5.36/2.16 Q is empty. 5.36/2.16 5.36/2.16 ---------------------------------------- 5.36/2.16 5.36/2.16 (1) NonTerminationProof (COMPLETE) 5.36/2.16 We used the non-termination processor [OPPELT08] to show that the SRS problem is infinite. 5.36/2.16 5.36/2.16 Found the self-embedding DerivationStructure: 5.36/2.16 "a b b b c b -> a b b b c b" 5.36/2.16 a b b b c b -> a b b b c b 5.36/2.16 by OverlapClosure OC 3"a b b b c b -> a b b b a c b 5.36/2.16 by OverlapClosure OC 2"a b b b c -> a b b a 5.36/2.16 by OverlapClosure OC 3"a b b b c -> b a b b a 5.36/2.16 by OverlapClosure OC 2"a b b b -> b a b b a c 5.36/2.16 by OverlapClosure OC 2"a b b b -> b a b b a c b 5.36/2.16 by OverlapClosure OC 2"a b b -> b a b a 5.36/2.16 by OverlapClosure OC 3"a b b -> b a c c b a 5.36/2.16 by OverlapClosure OC 3"a b b -> b a c b c b a 5.36/2.16 by OverlapClosure OC 2"a b -> b a c a 5.36/2.16 by OverlapClosure OC 3"a b -> b a c b a 5.36/2.16 by original rule (OC 1)""b -> 5.36/2.16 by original rule (OC 1)"""a b -> b c b a 5.36/2.16 by OverlapClosure OC 3"a b -> b a c b a 5.36/2.16 by original rule (OC 1)""a -> 5.36/2.16 by original rule (OC 1)""""b -> 5.36/2.16 by original rule (OC 1)"""c c -> 5.36/2.16 by original rule (OC 1)"""a b -> b a c b 5.36/2.16 by OverlapClosure OC 2"a b -> b a c b a 5.36/2.16 by original rule (OC 1)""a -> 5.36/2.16 by original rule (OC 1)""""b -> 5.36/2.16 by original rule (OC 1)"""c c -> 5.36/2.16 by original rule (OC 1)"""b -> 5.36/2.16 by original rule (OC 1)"""a b -> b a c b 5.36/2.16 by OverlapClosure OC 2"a b -> b a c b a 5.36/2.16 by original rule (OC 1)""a -> 5.36/2.16 by original rule (OC 1)""""a -> 5.36/2.16 by original rule (OC 1)" 5.36/2.16 5.36/2.16 ---------------------------------------- 5.36/2.16 5.36/2.16 (2) 5.36/2.16 NO 5.36/2.21 EOF popout

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all output return to SRS_Standard 2019-03-29 03.29