details

property	value
status	complete
benchmark	#3.13.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n186.star.cs.uiowa.edu
space	AG01

run statistics

property	value
solver	NaTT v.1.6c
configuration	Default
runtime (wallclock)	0.0601311 seconds
cpu usage	0.031795
user time	0.013777
system time	0.018018
max virtual memory	113188.0
max residence set size	6416.0

stage attributes

key	value
starexec-result	YES

output

YES Input TRS: 1: eq(0(),0()) -> true() 2: eq(0(),s(x)) -> false() 3: eq(s(x),0()) -> false() 4: eq(s(x),s(y)) -> eq(x,y) 5: or(true(),y) -> true() 6: or(false(),y) -> y 7: union(empty(),h) -> h 8: union(edge(x,y,i),h) -> edge(x,y,union(i,h)) 9: reach(x,y,empty(),h) -> false() 10: reach(x,y,edge(u,v,i),h) -> if_reach_1(eq(x,u),x,y,edge(u,v,i),h) 11: if_reach_1(true(),x,y,edge(u,v,i),h) -> if_reach_2(eq(y,v),x,y,edge(u,v,i),h) 12: if_reach_2(true(),x,y,edge(u,v,i),h) -> true() 13: if_reach_2(false(),x,y,edge(u,v,i),h) -> or(reach(x,y,i,h),reach(v,y,union(i,h),empty())) 14: if_reach_1(false(),x,y,edge(u,v,i),h) -> reach(x,y,i,edge(u,v,h)) Number of strict rules: 14 Direct POLO(bPol) ... failed. Uncurrying ... failed. Dependency Pairs: #1: #if_reach_2(false(),x,y,edge(u,v,i),h) -> #or(reach(x,y,i,h),reach(v,y,union(i,h),empty())) #2: #if_reach_2(false(),x,y,edge(u,v,i),h) -> #reach(x,y,i,h) #3: #if_reach_2(false(),x,y,edge(u,v,i),h) -> #reach(v,y,union(i,h),empty()) #4: #if_reach_2(false(),x,y,edge(u,v,i),h) -> #union(i,h) #5: #if_reach_1(true(),x,y,edge(u,v,i),h) -> #if_reach_2(eq(y,v),x,y,edge(u,v,i),h) #6: #if_reach_1(true(),x,y,edge(u,v,i),h) -> #eq(y,v) #7: #if_reach_1(false(),x,y,edge(u,v,i),h) -> #reach(x,y,i,edge(u,v,h)) #8: #reach(x,y,edge(u,v,i),h) -> #if_reach_1(eq(x,u),x,y,edge(u,v,i),h) #9: #reach(x,y,edge(u,v,i),h) -> #eq(x,u) #10: #union(edge(x,y,i),h) -> #union(i,h) #11: #eq(s(x),s(y)) -> #eq(x,y) Number of SCCs: 3, DPs: 7 SCC { #11 } POLO(Sum)... succeeded. s w: x1 + 1 #if_reach_1 w: 0 edge w: 0 #if_reach_2 w: 0 eq w: 0 false w: 0 reach w: 0 if_reach_2 w: 0 true w: 0 #reach w: 0 #eq w: x2 0 w: 0 union w: 0 or w: 0 empty w: 0 if_reach_1 w: 0 #or w: 0 #union w: 0 USABLE RULES: { } Removed DPs: #11 Number of SCCs: 2, DPs: 6 SCC { #10 } POLO(Sum)... succeeded. s w: 1 #if_reach_1 w: 0 edge w: x3 + 1 #if_reach_2 w: 0 eq w: 0 false w: 0 reach w: 0 if_reach_2 w: 0 true w: 0 #reach w: 0 #eq w: 0 0 w: 0 union w: 0 or w: 0 empty w: 0 if_reach_1 w: 0 #or w: 0 #union w: x1 USABLE RULES: { } Removed DPs: #10 Number of SCCs: 1, DPs: 5 SCC { #2 #3 #5 #7 #8 } POLO(Sum)... succeeded. s w: 1 #if_reach_1 w: x2 + x3 + x4 + x5 + 1 edge w: x2 + x3 + 61306 #if_reach_2 w: x2 + x3 + x4 + x5 eq w: x1 + x2 + 1 false w: 4 reach w: 0 if_reach_2 w: 0 true w: 4 #reach w: x1 + x2 + x3 + x4 + 1 #eq w: 0 0 w: 1 union w: x1 + x2 + 17221 or w: 0 empty w: 44083 if_reach_1 w: 0 #or w: 0 #union w: 0 USABLE RULES: { 7 8 } Removed DPs: #2 #3 #5 popout

output may be truncated. 'popout' for the full output.

job log

popout

actions

all output return to TRS Standard