SRS Standard pair #487085969

details

property	value
status	complete
benchmark	3995.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n141.star.cs.uiowa.edu
space	ICFP_2010

run statistics

property	value
solver	MultumNonMulta 20 June 2020 20G sparse
configuration	default
runtime (wallclock)	4.11095 seconds
cpu usage	13.8271
user time	12.2304
system time	1.59668
max virtual memory	2.6507812E7
max residence set size	1280464.0

stage attributes

key	value
starexec-result	YES

output

YES

After renaming modulo { 0->0, 1->1, 2->2, 3->3, 4->4, 5->5 }, 
it remains to prove termination of the 48-rule system
{ 0 1 2 -> 0 0 3 4 0 3 0 3 0 2 ,
  0 5 1 4 4 -> 0 5 1 5 0 0 1 0 3 2 ,
  1 2 5 5 2 -> 1 0 5 0 3 5 4 0 3 2 ,
  2 5 5 1 3 -> 2 5 0 1 1 5 5 1 5 5 ,
  3 5 2 5 2 -> 3 5 5 3 0 0 3 0 4 3 ,
  4 3 1 2 5 -> 4 3 0 2 5 0 3 4 3 1 ,
  4 5 1 1 2 -> 1 0 1 5 5 0 5 2 0 3 ,
  5 1 1 0 2 -> 5 5 3 1 1 0 0 4 2 2 ,
  0 1 2 4 2 4 -> 0 5 3 4 1 0 0 3 2 0 ,
  0 1 2 5 1 3 -> 0 4 0 3 0 2 1 5 5 0 ,
  0 5 2 0 1 1 -> 0 5 5 5 1 0 3 0 1 1 ,
  1 4 1 0 1 2 -> 2 5 2 0 2 0 0 0 3 3 ,
  2 1 1 4 1 3 -> 4 1 1 5 5 1 5 2 1 5 ,
  2 3 1 2 1 2 -> 1 3 3 3 0 2 0 0 3 4 ,
  2 3 5 1 1 2 -> 2 3 4 3 2 2 0 4 0 3 ,
  2 3 5 1 1 3 -> 1 0 3 4 0 4 0 1 0 1 ,
  2 3 5 1 2 4 -> 1 2 1 5 5 0 3 3 0 0 ,
  3 2 5 2 1 2 -> 4 3 1 0 0 4 2 0 4 3 ,
  3 3 1 2 5 3 -> 0 4 2 2 2 2 3 3 1 3 ,
  4 5 1 2 0 5 -> 1 3 4 0 3 5 5 3 0 3 ,
  5 2 4 4 1 2 -> 5 2 3 3 0 0 3 2 2 3 ,
  0 4 1 1 4 2 3 -> 0 1 0 0 0 1 2 0 4 3 ,
  0 5 2 5 2 3 1 -> 0 0 1 0 2 5 5 1 2 1 ,
  1 0 1 2 5 1 2 -> 1 5 2 3 5 1 1 0 0 3 ,
  1 1 4 1 2 1 4 -> 1 0 2 3 0 5 0 4 3 0 ,
  1 1 4 2 1 4 1 -> 1 3 0 0 5 4 1 5 3 1 ,
  1 1 4 2 4 3 4 -> 5 5 4 3 0 0 4 0 0 2 ,
  1 2 1 2 2 1 5 -> 5 4 1 0 3 4 3 3 1 3 ,
  1 2 3 2 4 2 4 -> 5 5 0 0 3 3 5 0 4 4 ,
  1 2 3 5 3 4 5 -> 1 0 5 3 5 1 5 2 0 1 ,
  1 3 0 5 2 3 5 -> 1 0 0 4 2 3 5 3 2 5 ,
  1 3 4 1 1 2 5 -> 1 5 3 4 2 2 2 0 3 1 ,
  1 4 1 1 1 2 0 -> 1 5 0 5 1 5 2 5 2 0 ,
  2 0 1 1 1 2 5 -> 5 2 0 3 4 0 0 4 2 5 ,
  2 0 1 4 1 1 3 -> 2 0 2 0 0 4 5 0 4 5 ,
  2 1 2 5 2 5 1 -> 2 4 5 3 3 5 3 1 0 1 ,
  2 1 5 0 2 4 0 -> 2 5 3 2 5 0 3 1 5 0 ,
  2 3 1 1 1 1 4 -> 2 0 3 3 1 4 3 5 0 5 ,
  2 3 2 0 5 1 0 -> 4 3 5 0 3 3 0 3 5 0 ,
  2 3 2 4 0 2 4 -> 4 4 5 4 3 0 3 3 5 4 ,
  2 3 3 5 2 5 2 -> 1 0 0 4 2 2 0 5 1 2 ,
  3 1 4 2 1 1 2 -> 0 1 2 2 3 2 4 0 0 4 ,
  3 2 3 1 1 3 2 -> 0 3 1 2 0 0 2 0 0 3 ,
  3 2 3 5 1 3 1 -> 3 1 4 3 0 5 5 5 5 1 ,
  3 4 0 2 2 4 0 -> 0 4 5 3 0 3 0 5 3 0 ,
  5 2 0 1 4 1 3 -> 5 4 0 0 4 1 4 5 5 4 ,
  5 2 0 2 1 1 4 -> 5 1 3 3 3 5 3 0 3 0 ,
  5 2 0 5 4 1 5 -> 1 1 5 2 1 5 5 1 1 5 }


The system was reversed.

After renaming modulo { 2->0, 1->1, 0->2, 3->3, 4->4, 5->5 }, 
it remains to prove termination of the 48-rule system
{ 0 1 2 -> 0 2 3 2 3 2 4 3 2 2 ,
  4 4 1 5 2 -> 0 3 2 1 2 2 5 1 5 2 ,
  0 5 5 0 1 -> 0 3 2 4 5 3 2 5 2 1 ,
  3 1 5 5 0 -> 5 5 1 5 5 1 1 2 5 0 ,
  0 5 0 5 3 -> 3 4 2 3 2 2 3 5 5 3 ,
  5 0 1 3 4 -> 1 3 4 3 2 5 0 2 3 4 ,
  0 1 1 5 4 -> 3 2 0 5 2 5 5 1 2 1 ,
  0 2 1 1 5 -> 0 0 4 2 2 1 1 3 5 5 ,
  4 0 4 0 1 2 -> 2 0 3 2 2 1 4 3 5 2 ,
  3 1 5 0 1 2 -> 2 5 5 1 0 2 3 2 4 2 ,
  1 1 2 0 5 2 -> 1 1 2 3 2 1 5 5 5 2 ,
  0 1 2 1 4 1 -> 3 3 2 2 2 0 2 0 5 0 ,
  3 1 4 1 1 0 -> 5 1 0 5 1 5 5 1 1 4 ,
  0 1 0 1 3 0 -> 4 3 2 2 0 2 3 3 3 1 ,
  0 1 1 5 3 0 -> 3 2 4 2 0 0 3 4 3 0 ,
  3 1 1 5 3 0 -> 1 2 1 2 4 2 4 3 2 1 ,
  4 0 1 5 3 0 -> 2 2 3 3 2 5 5 1 0 1 ,
  0 1 0 5 0 3 -> 3 4 2 0 4 2 2 1 3 4 ,
  3 5 0 1 3 3 -> 3 1 3 3 0 0 0 0 4 2 ,
  5 2 0 1 5 4 -> 3 2 3 5 5 3 2 4 3 1 ,
  0 1 4 4 0 5 -> 3 0 0 3 2 2 3 3 0 5 ,
  3 0 4 1 1 4 2 -> 3 4 2 0 1 2 2 2 1 2 ,
  1 3 0 5 0 5 2 -> 1 0 1 5 5 0 2 1 2 2 ,
  0 1 5 0 1 2 1 -> 3 2 2 1 1 5 3 0 5 1 ,
  4 1 0 1 4 1 1 -> 2 3 4 2 5 2 3 0 2 1 ,
  1 4 1 0 4 1 1 -> 1 3 5 1 4 5 2 2 3 1 ,
  4 3 4 0 4 1 1 -> 0 2 2 4 2 2 3 4 5 5 ,
  5 1 0 0 1 0 1 -> 3 1 3 3 4 3 2 1 4 5 ,
  4 0 4 0 3 0 1 -> 4 4 2 5 3 3 2 2 5 5 ,
  5 4 3 5 3 0 1 -> 1 2 0 5 1 5 3 5 2 1 ,
  5 3 0 5 2 3 1 -> 5 0 3 5 3 0 4 2 2 1 ,
  5 0 1 1 4 3 1 -> 1 3 2 0 0 0 4 3 5 1 ,
  2 0 1 1 1 4 1 -> 2 0 5 0 5 1 5 2 5 1 ,
  5 0 1 1 1 2 0 -> 5 0 4 2 2 4 3 2 0 5 ,
  3 1 1 4 1 2 0 -> 5 4 2 5 4 2 2 0 2 0 ,
  1 5 0 5 0 1 0 -> 1 2 1 3 5 3 3 5 4 0 ,
  2 4 0 2 5 1 0 -> 2 5 1 3 2 5 0 3 5 0 ,
  4 1 1 1 1 3 0 -> 5 2 5 3 4 1 3 3 2 0 ,
  2 1 5 2 0 3 0 -> 2 5 3 2 3 3 2 5 3 4 ,
  4 0 2 4 0 3 0 -> 4 5 3 3 2 3 4 5 4 4 ,
  0 5 0 5 3 3 0 -> 0 1 5 2 0 0 4 2 2 1 ,
  0 1 1 0 4 1 3 -> 4 2 2 4 0 3 0 0 1 2 ,

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job log

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