details

property	value
status	complete
benchmark	88156.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n150.star.cs.uiowa.edu
space	ICFP_2010

run statistics

property	value
solver	MultumNonMulta 20 June 2020 20G sparse
configuration	default
runtime (wallclock)	1.87213 seconds
cpu usage	6.04258
user time	5.43856
system time	0.604026
max virtual memory	2.5725252E7
max residence set size	927184.0

stage attributes

key	value
starexec-result	YES

output

YES After renaming modulo { 0->0, 1->1, 2->2, 3->3 }, it remains to prove termination of the 30-rule system { 0 0 1 1 2 0 3 0 1 2 0 1 1 -> 0 0 3 0 0 2 0 2 2 0 0 1 0 0 0 1 0 , 0 1 0 3 1 0 2 2 1 1 0 2 1 -> 0 0 2 2 3 0 0 0 0 1 0 1 0 3 0 1 2 , 0 1 1 0 0 1 3 1 2 0 3 1 2 -> 0 2 0 2 0 1 3 0 2 0 0 0 0 1 2 2 0 , 0 1 3 2 1 0 3 0 0 1 1 1 1 -> 0 3 1 3 1 0 0 3 2 0 3 0 3 0 0 1 0 , 0 2 0 2 0 2 3 2 3 1 1 3 1 -> 0 0 1 3 0 0 3 0 3 2 3 0 0 2 2 1 0 , 0 2 2 3 2 2 1 2 0 3 2 0 3 -> 0 3 2 1 0 2 3 0 0 1 0 2 1 0 0 3 0 , 0 2 3 0 2 2 3 2 2 1 1 2 3 -> 1 0 0 2 3 2 0 2 0 1 3 0 2 0 1 1 2 , 0 2 3 1 1 0 2 0 0 2 1 3 2 -> 0 2 2 0 0 3 2 2 0 1 2 2 0 0 2 2 0 , 0 2 3 2 2 3 1 0 2 0 3 1 3 -> 0 0 3 0 2 1 1 0 0 2 2 0 2 0 2 2 3 , 1 0 0 3 2 0 1 0 1 2 2 1 1 -> 0 0 3 3 1 0 0 0 2 0 2 0 1 0 0 1 2 , 1 0 3 0 2 1 1 0 1 1 1 2 2 -> 0 3 2 0 0 2 0 0 3 0 0 0 3 3 3 3 3 , 1 1 2 0 2 2 0 0 1 3 2 3 2 -> 2 0 0 0 0 1 2 3 0 1 0 0 3 2 0 0 1 , 1 2 2 1 2 2 0 0 1 2 2 0 1 -> 0 0 3 0 0 1 2 2 0 3 2 0 2 0 1 0 3 , 1 2 3 1 0 2 1 0 0 1 1 1 0 -> 0 3 0 1 0 1 2 0 3 0 0 0 1 0 1 3 0 , 1 3 0 0 3 2 2 2 2 1 0 2 3 -> 3 0 0 2 2 0 3 2 0 3 0 2 3 1 2 0 0 , 1 3 1 0 1 3 1 2 0 1 3 1 0 -> 1 2 0 3 1 3 0 0 3 3 1 0 3 0 0 0 0 , 1 3 1 1 3 0 0 1 0 0 2 3 0 -> 2 1 0 2 0 3 2 0 0 0 0 2 0 1 1 3 0 , 1 3 1 3 1 0 2 0 1 3 0 0 1 -> 2 2 0 0 0 1 0 0 2 0 0 1 3 3 3 0 1 , 1 3 2 1 0 1 0 3 0 1 3 0 0 -> 0 3 1 0 0 0 3 0 0 2 3 2 1 0 1 0 0 , 1 3 3 0 2 3 0 3 2 0 0 1 1 -> 3 2 0 3 0 3 0 0 2 0 0 0 1 0 2 3 1 , 1 3 3 2 2 2 3 2 2 0 2 3 0 -> 3 0 3 2 2 0 2 2 1 0 2 2 3 1 2 0 0 , 2 0 2 1 2 2 3 2 2 2 2 1 0 -> 1 0 0 0 0 1 0 0 2 0 3 1 0 0 2 3 0 , 2 0 2 2 1 2 2 3 2 0 1 1 2 -> 0 2 3 1 3 1 0 0 0 0 0 0 1 2 2 1 0 , 2 0 3 3 1 2 2 0 0 2 1 0 1 -> 3 2 0 1 0 0 2 0 3 1 0 0 0 2 1 0 2 , 2 1 1 0 3 2 1 2 0 0 3 1 3 -> 2 2 0 1 0 0 0 0 2 2 0 0 2 2 1 3 3 , 2 2 0 1 0 1 0 3 3 2 1 2 3 -> 0 3 0 1 2 0 1 2 0 2 2 1 2 1 0 0 0 , 2 3 0 0 0 2 3 3 2 0 3 0 3 -> 2 2 0 0 0 1 2 0 0 0 3 0 2 0 3 2 0 , 2 3 0 2 2 0 2 0 3 2 3 2 3 -> 1 0 0 3 2 0 3 3 0 0 3 0 0 2 0 0 2 , 3 0 0 1 3 1 2 0 2 0 3 3 3 -> 0 0 1 0 1 2 0 0 3 0 2 2 2 0 0 1 3 , 3 2 2 2 0 1 3 0 2 2 3 3 0 -> 1 1 0 1 0 0 3 0 1 2 1 1 0 0 1 0 0 } The system was reversed. After renaming modulo { 1->0, 0->1, 2->2, 3->3 }, it remains to prove termination of the 30-rule system { 0 0 1 2 0 1 3 1 2 0 0 1 1 -> 1 0 1 1 1 0 1 1 2 2 1 2 1 1 3 1 1 , 0 2 1 0 0 2 2 1 0 3 1 0 1 -> 2 0 1 3 1 0 1 0 1 1 1 1 3 2 2 1 1 , 2 0 3 1 2 0 3 0 1 1 0 0 1 -> 1 2 2 0 1 1 1 1 2 1 3 0 1 2 1 2 1 , 0 0 0 0 1 1 3 1 0 2 3 0 1 -> 1 0 1 1 3 1 3 1 2 3 1 1 0 3 0 3 1 , 0 3 0 0 3 2 3 2 1 2 1 2 1 -> 1 0 2 2 1 1 3 2 3 1 3 1 1 3 0 1 1 , 3 1 2 3 1 2 0 2 2 3 2 2 1 -> 1 3 1 1 0 2 1 0 1 1 3 2 1 0 2 3 1 , 3 2 0 0 2 2 3 2 2 1 3 2 1 -> 2 0 0 1 2 1 3 0 1 2 1 2 3 2 1 1 0 , 2 3 0 2 1 1 2 1 0 0 3 2 1 -> 1 2 2 1 1 2 2 0 1 2 2 3 1 1 2 2 1 , 3 0 3 1 2 1 0 3 2 2 3 2 1 -> 3 2 2 1 2 1 2 2 1 1 0 0 2 1 3 1 1 , 0 0 2 2 0 1 0 1 2 3 1 1 0 -> 2 0 1 1 0 1 2 1 2 1 1 1 0 3 3 1 1 , 2 2 0 0 0 1 0 0 2 1 3 1 0 -> 3 3 3 3 3 1 1 1 3 1 1 2 1 1 2 3 1 , 2 3 2 3 0 1 1 2 2 1 2 0 0 -> 0 1 1 2 3 1 1 0 1 3 2 0 1 1 1 1 2 , 0 1 2 2 0 1 1 2 2 0 2 2 0 -> 3 1 0 1 2 1 2 3 1 2 2 0 1 1 3 1 1 , 1 0 0 0 1 1 0 2 1 0 3 2 0 -> 1 3 0 1 0 1 1 1 3 1 2 0 1 0 1 3 1 , 3 2 1 0 2 2 2 2 3 1 1 3 0 -> 1 1 2 0 3 2 1 3 1 2 3 1 2 2 1 1 3 , 1 0 3 0 1 2 0 3 0 1 0 3 0 -> 1 1 1 1 3 1 0 3 3 1 1 3 0 3 1 2 0 , 1 3 2 1 1 0 1 1 3 0 0 3 0 -> 1 3 0 0 1 2 1 1 1 1 2 3 1 2 1 0 2 , 0 1 1 3 0 1 2 1 0 3 0 3 0 -> 0 1 3 3 3 0 1 1 2 1 1 0 1 1 1 2 2 , 1 1 3 0 1 3 1 0 1 0 2 3 0 -> 1 1 0 1 0 2 3 2 1 1 3 1 1 1 0 3 1 , 0 0 1 1 2 3 1 3 2 1 3 3 0 -> 0 3 2 1 0 1 1 1 2 1 1 3 1 3 1 2 3 , 1 3 2 1 2 2 3 2 2 2 3 3 0 -> 1 1 2 0 3 2 2 1 0 2 2 1 2 2 3 1 3 , 1 0 2 2 2 2 3 2 2 0 2 1 2 -> 1 3 2 1 1 0 3 1 2 1 1 0 1 1 1 1 0 , 2 0 0 1 2 3 2 2 0 2 2 1 2 -> 1 0 2 2 0 1 1 1 1 1 1 0 3 0 3 2 1 , 0 1 0 2 1 1 2 2 0 3 3 1 2 -> 2 1 0 2 1 1 1 0 3 1 2 1 1 0 1 2 3 , 3 0 3 1 1 2 0 2 3 1 0 0 2 -> 3 3 0 2 2 1 1 2 2 1 1 1 1 0 1 2 2 , 3 2 0 2 3 3 1 0 1 0 1 2 2 -> 1 1 1 0 2 0 2 2 1 2 0 1 2 0 1 3 1 , 3 1 3 1 2 3 3 2 1 1 1 3 2 -> 1 2 3 1 2 1 3 1 1 1 2 0 1 1 1 2 2 , 3 2 3 2 3 1 2 1 2 2 1 3 2 -> 2 1 1 2 1 1 3 1 1 3 3 1 2 3 1 1 0 , 3 3 3 1 2 1 2 0 3 0 1 1 3 -> 3 0 1 1 2 2 2 1 3 1 1 2 0 1 0 1 1 , 1 3 3 2 2 1 3 0 1 2 2 2 3 -> 1 1 0 1 1 0 0 2 0 1 3 1 1 0 1 0 0 } Applying sparse 2-tiling [Hofbauer/Geser/Waldmann, FSCD 2019]. After renaming modulo { (0,0)->0, (0,1)->1, (1,2)->2, (2,0)->3, (1,3)->4, (3,1)->5, (1,1)->6, (1,0)->7, (2,2)->8, (2,1)->9, (1,5)->10, (3,0)->11, (4,0)->12, (4,1)->13, (0,2)->14, (0,3)->15, (3,2)->16, (4,2)->17, (2,3)->18, (3,3)->19, (4,3)->20, (0,5)->21, (2,5)->22, (3,5)->23 }, it remains to prove termination of the 750-rule system { 0 0 1 2 3 1 4 5 2 3 0 1 6 7 -> 1 7 1 6 6 7 1 6 2 8 9 2 9 6 4 5 6 7 , 0 0 1 2 3 1 4 5 2 3 0 1 6 6 -> 1 7 1 6 6 7 1 6 2 8 9 2 9 6 4 5 6 6 , 0 0 1 2 3 1 4 5 2 3 0 1 6 2 -> 1 7 1 6 6 7 1 6 2 8 9 2 9 6 4 5 6 2 , 0 0 1 2 3 1 4 5 2 3 0 1 6 4 -> 1 7 1 6 6 7 1 6 2 8 9 2 9 6 4 5 6 4 , 0 0 1 2 3 1 4 5 2 3 0 1 6 10 -> 1 7 1 6 6 7 1 6 2 8 9 2 9 6 4 5 6 10 , 7 0 1 2 3 1 4 5 2 3 0 1 6 7 -> 6 7 1 6 6 7 1 6 2 8 9 2 9 6 4 5 6 7 , 7 0 1 2 3 1 4 5 2 3 0 1 6 6 -> 6 7 1 6 6 7 1 6 2 8 9 2 9 6 4 5 6 6 , 7 0 1 2 3 1 4 5 2 3 0 1 6 2 -> 6 7 1 6 6 7 1 6 2 8 9 2 9 6 4 5 6 2 , 7 0 1 2 3 1 4 5 2 3 0 1 6 4 -> 6 7 1 6 6 7 1 6 2 8 9 2 9 6 4 5 6 4 , 7 0 1 2 3 1 4 5 2 3 0 1 6 10 -> 6 7 1 6 6 7 1 6 2 8 9 2 9 6 4 5 6 10 , 3 0 1 2 3 1 4 5 2 3 0 1 6 7 -> 9 7 1 6 6 7 1 6 2 8 9 2 9 6 4 5 6 7 , 3 0 1 2 3 1 4 5 2 3 0 1 6 6 -> 9 7 1 6 6 7 1 6 2 8 9 2 9 6 4 5 6 6 , 3 0 1 2 3 1 4 5 2 3 0 1 6 2 -> 9 7 1 6 6 7 1 6 2 8 9 2 9 6 4 5 6 2 , 3 0 1 2 3 1 4 5 2 3 0 1 6 4 -> 9 7 1 6 6 7 1 6 2 8 9 2 9 6 4 5 6 4 , 3 0 1 2 3 1 4 5 2 3 0 1 6 10 -> 9 7 1 6 6 7 1 6 2 8 9 2 9 6 4 5 6 10 , 11 0 1 2 3 1 4 5 2 3 0 1 6 7 -> 5 7 1 6 6 7 1 6 2 8 9 2 9 6 4 5 6 7 , 11 0 1 2 3 1 4 5 2 3 0 1 6 6 -> 5 7 1 6 6 7 1 6 2 8 9 2 9 6 4 5 6 6 , 11 0 1 2 3 1 4 5 2 3 0 1 6 2 -> 5 7 1 6 6 7 1 6 2 8 9 2 9 6 4 5 6 2 , 11 0 1 2 3 1 4 5 2 3 0 1 6 4 -> 5 7 1 6 6 7 1 6 2 8 9 2 9 6 4 5 6 4 , 11 0 1 2 3 1 4 5 2 3 0 1 6 10 -> 5 7 1 6 6 7 1 6 2 8 9 2 9 6 4 5 6 10 , 12 0 1 2 3 1 4 5 2 3 0 1 6 7 -> 13 7 1 6 6 7 1 6 2 8 9 2 9 6 4 5 6 7 , 12 0 1 2 3 1 4 5 2 3 0 1 6 6 -> 13 7 1 6 6 7 1 6 2 8 9 2 9 6 4 5 6 6 , 12 0 1 2 3 1 4 5 2 3 0 1 6 2 -> 13 7 1 6 6 7 1 6 2 8 9 2 9 6 4 5 6 2 , 12 0 1 2 3 1 4 5 2 3 0 1 6 4 -> 13 7 1 6 6 7 1 6 2 8 9 2 9 6 4 5 6 4 , popout

output may be truncated. 'popout' for the full output.

job log

popout

actions

all output return to SRS Standard