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SRS Standard pair #487511670
details
property
value
status
complete
benchmark
1.xml
ran by
Akihisa Yamada
cpu timeout
1200 seconds
wallclock timeout
300 seconds
memory limit
137438953472 bytes
execution host
n095.star.cs.uiowa.edu
space
Mixed_SRS
run statistics
property
value
solver
MultumNonMulta 3.16 29 June 2020 60G
configuration
default
runtime (wallclock)
0.496403932571 seconds
cpu usage
0.724091755
max memory
3.57384192E8
stage attributes
key
value
output-size
1097
starexec-result
NO
output
/export/starexec/sandbox2/solver/bin/starexec_run_default /export/starexec/sandbox2/benchmark/theBenchmark.xml /export/starexec/sandbox2/output/output_files -------------------------------------------------------------------------------- NO After renaming modulo { b->0, c->1, a->2 }, it remains to prove termination of the 2-rule system { 0 1 -> 2 0 0 , 0 2 -> 2 1 0 } The system was reversed. After renaming modulo { 1->0, 0->1, 2->2 }, it remains to prove termination of the 2-rule system { 0 1 -> 1 1 2 , 2 1 -> 1 0 2 } Loop of length 10 starting with a string of length 6 using right expansion and the encoding { 0->a, 1->b, ... }: .ab.bbbb rule ab-> bbc at position 0 .bbc.bbbb rule cb-> bac at position 2 .bbbac.bbb rule cb-> bac at position 4 .bbbabac.bb rule cb-> bac at position 6 .bbbababac.b rule ab-> bbc at position 5 .bbbabbbcac.b rule cb-> bac at position 9 .bbbabbbcabac. rule ab-> bbc at position 8 .bbbabbbcbbcac. rule cb-> bac at position 7 .bbbabbbbacbcac. rule cb-> bac at position 9 .bbbabbbbabaccac. rule ab-> bbc at position 8 .bbbabbbbbbcaccac.
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