SRS Standard pair #487516698

details

property	value
status	complete
benchmark	5076.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n187.star.cs.uiowa.edu
space	ICFP_2010

run statistics

property	value
solver	MultumNonMulta 3.16 29 June 2020 60G
configuration	default
runtime (wallclock)	2.71887087822 seconds
cpu usage	8.824134144
max memory	1.404592128E9

stage attributes

key	value
output-size	271709
starexec-result	YES

output

/export/starexec/sandbox2/solver/bin/starexec_run_default /export/starexec/sandbox2/benchmark/theBenchmark.xml /export/starexec/sandbox2/output/output_files


--------------------------------------------------------------------------------


YES

After renaming modulo { 3->0, 4->1, 5->2, 2->3, 1->4, 0->5 }, 
it remains to prove termination of the 33-rule system
{ 0 1 2 -> 0 3 0 3 4 2 0 2 3 3 ,
  5 1 2 0 -> 1 5 0 3 0 4 4 2 5 2 ,
  5 2 1 4 -> 5 4 1 4 2 4 3 3 5 4 ,
  0 1 2 0 -> 0 3 0 3 4 1 4 5 0 3 ,
  0 2 5 2 -> 0 3 4 1 0 0 3 5 4 2 ,
  1 5 2 2 -> 0 0 3 3 3 5 0 2 0 2 ,
  2 2 0 1 -> 4 4 1 1 4 1 0 1 3 3 ,
  5 2 2 4 5 -> 5 3 1 2 0 4 2 4 1 5 ,
  3 0 2 4 5 -> 3 4 3 2 4 4 2 1 3 5 ,
  0 1 2 5 5 -> 1 0 0 4 3 2 5 1 0 5 ,
  2 3 0 2 3 -> 2 3 3 4 3 5 2 3 3 3 ,
  2 1 2 1 4 -> 4 2 0 1 4 5 1 3 5 4 ,
  5 5 2 5 2 2 -> 4 4 0 1 0 5 3 1 2 3 ,
  5 2 1 0 1 2 -> 4 2 5 3 3 0 1 0 3 2 ,
  5 2 1 2 3 5 -> 5 3 3 2 0 0 3 3 3 5 ,
  5 2 2 4 5 2 -> 4 3 5 3 2 1 0 4 4 2 ,
  5 2 2 4 4 0 -> 5 2 5 0 3 4 1 4 1 3 ,
  4 3 0 2 1 1 -> 1 5 3 5 1 5 0 3 3 1 ,
  0 5 1 2 0 0 -> 1 3 5 2 1 3 4 5 5 0 ,
  0 1 5 2 5 4 -> 0 3 4 0 4 5 5 1 5 4 ,
  1 5 1 2 1 4 -> 1 1 0 4 4 4 1 5 4 4 ,
  1 0 2 5 2 2 -> 1 0 3 2 3 2 3 4 0 2 ,
  2 2 5 4 5 5 -> 2 5 1 3 1 1 3 3 1 5 ,
  5 5 2 5 1 5 4 -> 2 4 1 1 3 5 0 0 1 4 ,
  5 5 2 0 2 0 5 -> 5 3 2 5 3 1 0 4 5 5 ,
  5 4 3 2 3 0 2 -> 1 1 0 4 1 5 2 4 2 2 ,
  5 2 2 2 3 0 0 -> 4 5 4 0 5 2 1 3 1 3 ,
  4 5 5 2 3 0 1 -> 3 1 4 1 2 0 3 4 5 1 ,
  4 2 2 3 3 2 2 -> 4 5 1 3 2 0 4 2 4 2 ,
  3 0 1 0 1 2 0 -> 5 4 2 3 0 2 5 4 3 3 ,
  1 5 2 5 2 1 2 -> 4 3 4 0 3 3 2 0 2 2 ,
  2 0 2 2 2 1 4 -> 5 4 3 5 1 0 3 2 1 4 ,
  2 1 2 2 0 0 1 -> 4 2 5 3 0 1 4 0 5 5 }


Applying sparse tiling TRFC(2) [Geser/Hofbauer/Waldmann, FSCD 2019].

After renaming modulo { (0,0)->0, (0,1)->1, (1,2)->2, (2,0)->3, (0,3)->4, (3,0)->5, (3,4)->6, (4,2)->7, (0,2)->8, (2,3)->9, (3,3)->10, (2,1)->11, (3,1)->12, (2,2)->13, (3,2)->14, (2,4)->15, (2,5)->16, (3,5)->17, (2,7)->18, (3,7)->19, (1,0)->20, (4,0)->21, (5,0)->22, (6,0)->23, (0,5)->24, (5,1)->25, (1,5)->26, (0,4)->27, (4,4)->28, (5,2)->29, (0,7)->30, (1,1)->31, (4,5)->32, (4,1)->33, (5,5)->34, (6,5)->35, (6,1)->36, (1,4)->37, (5,4)->38, (4,3)->39, (4,7)->40, (1,3)->41, (1,7)->42, (6,2)->43, (6,4)->44, (5,3)->45, (5,7)->46, (6,3)->47 },
it remains to prove termination of the 1617-rule system
{ 0 1 2 3 -> 0 4 5 4 6 7 3 8 9 10 5 ,
  0 1 2 11 -> 0 4 5 4 6 7 3 8 9 10 12 ,
  0 1 2 13 -> 0 4 5 4 6 7 3 8 9 10 14 ,
  0 1 2 9 -> 0 4 5 4 6 7 3 8 9 10 10 ,
  0 1 2 15 -> 0 4 5 4 6 7 3 8 9 10 6 ,
  0 1 2 16 -> 0 4 5 4 6 7 3 8 9 10 17 ,
  0 1 2 18 -> 0 4 5 4 6 7 3 8 9 10 19 ,
  20 1 2 3 -> 20 4 5 4 6 7 3 8 9 10 5 ,
  20 1 2 11 -> 20 4 5 4 6 7 3 8 9 10 12 ,
  20 1 2 13 -> 20 4 5 4 6 7 3 8 9 10 14 ,
  20 1 2 9 -> 20 4 5 4 6 7 3 8 9 10 10 ,
  20 1 2 15 -> 20 4 5 4 6 7 3 8 9 10 6 ,
  20 1 2 16 -> 20 4 5 4 6 7 3 8 9 10 17 ,
  20 1 2 18 -> 20 4 5 4 6 7 3 8 9 10 19 ,
  3 1 2 3 -> 3 4 5 4 6 7 3 8 9 10 5 ,
  3 1 2 11 -> 3 4 5 4 6 7 3 8 9 10 12 ,
  3 1 2 13 -> 3 4 5 4 6 7 3 8 9 10 14 ,
  3 1 2 9 -> 3 4 5 4 6 7 3 8 9 10 10 ,
  3 1 2 15 -> 3 4 5 4 6 7 3 8 9 10 6 ,
  3 1 2 16 -> 3 4 5 4 6 7 3 8 9 10 17 ,
  3 1 2 18 -> 3 4 5 4 6 7 3 8 9 10 19 ,
  5 1 2 3 -> 5 4 5 4 6 7 3 8 9 10 5 ,
  5 1 2 11 -> 5 4 5 4 6 7 3 8 9 10 12 ,
  5 1 2 13 -> 5 4 5 4 6 7 3 8 9 10 14 ,
  5 1 2 9 -> 5 4 5 4 6 7 3 8 9 10 10 ,
  5 1 2 15 -> 5 4 5 4 6 7 3 8 9 10 6 ,
  5 1 2 16 -> 5 4 5 4 6 7 3 8 9 10 17 ,
  5 1 2 18 -> 5 4 5 4 6 7 3 8 9 10 19 ,
  21 1 2 3 -> 21 4 5 4 6 7 3 8 9 10 5 ,
  21 1 2 11 -> 21 4 5 4 6 7 3 8 9 10 12 ,
  21 1 2 13 -> 21 4 5 4 6 7 3 8 9 10 14 ,
  21 1 2 9 -> 21 4 5 4 6 7 3 8 9 10 10 ,
  21 1 2 15 -> 21 4 5 4 6 7 3 8 9 10 6 ,
  21 1 2 16 -> 21 4 5 4 6 7 3 8 9 10 17 ,
  21 1 2 18 -> 21 4 5 4 6 7 3 8 9 10 19 ,
  22 1 2 3 -> 22 4 5 4 6 7 3 8 9 10 5 ,
  22 1 2 11 -> 22 4 5 4 6 7 3 8 9 10 12 ,
  22 1 2 13 -> 22 4 5 4 6 7 3 8 9 10 14 ,
  22 1 2 9 -> 22 4 5 4 6 7 3 8 9 10 10 ,
  22 1 2 15 -> 22 4 5 4 6 7 3 8 9 10 6 ,
  22 1 2 16 -> 22 4 5 4 6 7 3 8 9 10 17 ,
  22 1 2 18 -> 22 4 5 4 6 7 3 8 9 10 19 ,
  23 1 2 3 -> 23 4 5 4 6 7 3 8 9 10 5 ,
  23 1 2 11 -> 23 4 5 4 6 7 3 8 9 10 12 ,
  23 1 2 13 -> 23 4 5 4 6 7 3 8 9 10 14 ,
  23 1 2 9 -> 23 4 5 4 6 7 3 8 9 10 10 ,
  23 1 2 15 -> 23 4 5 4 6 7 3 8 9 10 6 ,
  23 1 2 16 -> 23 4 5 4 6 7 3 8 9 10 17 ,
  23 1 2 18 -> 23 4 5 4 6 7 3 8 9 10 19 ,
  24 25 2 3 0 -> 1 26 22 4 5 27 28 7 16 29 3 ,
  24 25 2 3 1 -> 1 26 22 4 5 27 28 7 16 29 11 ,

popout

output may be truncated. 'popout' for the full output.

job log

popout

actions all output return to SRS Standard