SRS Standard pair #487517178

details

property	value
status	complete
benchmark	4854.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n141.star.cs.uiowa.edu
space	ICFP_2010

run statistics

property	value
solver	MultumNonMulta 3.16 29 June 2020 60G
configuration	default
runtime (wallclock)	7.14009094238 seconds
cpu usage	26.464550705
max memory	4.424523776E9

stage attributes

key	value
output-size	291037
starexec-result	YES

output

/export/starexec/sandbox/solver/bin/starexec_run_default /export/starexec/sandbox/benchmark/theBenchmark.xml /export/starexec/sandbox/output/output_files


--------------------------------------------------------------------------------


YES

After renaming modulo { 0->0, 1->1, 2->2, 3->3, 4->4, 5->5 }, 
it remains to prove termination of the 52-rule system
{ 0 1 2 -> 0 3 0 0 2 4 2 2 5 1 ,
  1 0 4 2 -> 0 0 3 5 3 0 0 2 0 2 ,
  2 4 1 3 -> 4 3 5 5 1 3 1 2 4 5 ,
  4 1 2 5 -> 4 0 0 2 2 4 3 1 3 5 ,
  4 1 3 0 -> 4 3 0 5 0 0 5 0 0 4 ,
  0 1 4 1 3 -> 0 2 5 0 5 0 0 2 4 5 ,
  4 1 2 1 1 -> 4 5 5 5 1 5 2 3 1 0 ,
  5 2 4 2 0 -> 4 0 0 0 1 0 0 2 2 0 ,
  5 4 1 2 2 -> 3 1 3 3 5 5 1 3 0 2 ,
  5 4 1 2 2 -> 3 3 0 0 0 4 1 0 5 1 ,
  5 4 2 0 5 -> 5 5 5 1 0 0 2 1 4 5 ,
  0 4 4 4 5 3 -> 0 1 0 3 0 0 2 5 0 0 ,
  2 0 3 4 4 4 -> 3 5 3 0 0 3 1 2 0 4 ,
  2 0 4 0 1 4 -> 3 5 5 1 4 3 1 5 4 0 ,
  2 3 3 4 4 1 -> 2 0 0 3 1 2 2 5 5 2 ,
  2 4 1 2 1 1 -> 2 0 0 4 0 5 3 0 1 0 ,
  2 5 2 0 1 0 -> 2 1 0 0 3 0 4 0 0 0 ,
  3 1 5 4 2 0 -> 0 3 3 0 0 3 1 1 3 0 ,
  4 0 5 2 3 1 -> 0 2 1 5 0 0 0 2 5 3 ,
  4 2 4 5 2 3 -> 2 4 4 0 0 2 3 1 4 3 ,
  5 2 4 1 5 2 -> 3 0 2 4 2 0 0 3 5 1 ,
  5 2 4 4 4 1 -> 2 0 4 0 3 1 3 5 0 2 ,
  5 4 5 2 4 1 -> 3 0 0 0 2 5 2 4 1 2 ,
  0 4 3 5 4 2 0 -> 0 0 3 0 0 1 5 0 0 0 ,
  1 1 5 0 1 5 2 -> 5 5 1 0 5 5 5 5 5 2 ,
  1 2 2 3 1 0 1 -> 1 4 0 0 2 2 2 5 0 4 ,
  1 3 0 4 3 4 4 -> 1 3 0 0 2 5 5 5 1 1 ,
  2 0 1 1 1 5 2 -> 2 5 0 0 1 0 4 3 5 1 ,
  2 0 1 5 0 2 1 -> 2 3 0 0 3 4 0 0 4 0 ,
  2 2 0 4 4 2 1 -> 3 1 0 3 3 0 1 4 0 0 ,
  2 5 3 4 1 3 4 -> 0 0 0 4 3 1 0 0 3 4 ,
  2 5 5 4 2 0 4 -> 2 1 2 2 4 5 5 2 3 0 ,
  2 5 5 4 5 3 4 -> 2 4 5 0 0 3 5 1 1 1 ,
  3 0 1 1 4 0 5 -> 4 0 2 3 5 3 0 0 2 3 ,
  3 2 4 5 4 5 3 -> 0 2 5 3 3 0 5 0 0 5 ,
  3 4 0 2 0 4 4 -> 0 5 0 3 0 0 1 4 4 0 ,
  3 5 2 0 4 1 1 -> 5 4 5 5 5 5 5 1 4 4 ,
  3 5 5 4 1 1 4 -> 3 4 2 2 5 0 0 3 1 4 ,
  4 1 0 4 0 1 1 -> 2 4 2 2 3 5 3 2 3 1 ,
  4 1 3 4 2 5 4 -> 4 1 3 0 4 0 0 2 5 4 ,
  4 2 4 1 1 1 2 -> 0 3 0 2 5 1 4 2 2 2 ,
  4 4 2 1 1 1 1 -> 4 3 5 0 0 5 0 1 3 4 ,
  4 5 3 5 2 1 1 -> 4 5 3 5 5 1 1 0 5 3 ,
  5 2 2 0 5 5 3 -> 2 0 0 2 3 5 1 1 5 3 ,
  5 2 2 3 4 4 0 -> 2 5 5 0 4 0 4 0 1 0 ,
  5 2 4 1 4 1 2 -> 2 3 0 3 1 1 4 2 2 2 ,
  5 2 5 2 4 1 3 -> 0 0 1 2 1 2 2 4 1 3 ,
  5 4 2 3 2 0 5 -> 3 0 4 0 1 0 3 3 1 5 ,
  5 4 2 4 1 2 0 -> 2 5 5 5 1 5 3 5 1 0 ,
  5 4 5 2 2 3 0 -> 2 1 2 5 0 3 3 0 4 4 ,
  5 4 5 5 3 1 2 -> 5 0 3 0 2 2 4 5 0 2 ,
  5 5 4 5 2 1 5 -> 0 0 2 1 3 2 0 2 2 5 }


Applying sparse tiling TRFC(2) [Geser/Hofbauer/Waldmann, FSCD 2019].

After renaming modulo { (0,0)->0, (0,1)->1, (1,2)->2, (2,0)->3, (0,3)->4, (3,0)->5, (0,2)->6, (2,4)->7, (4,2)->8, (2,2)->9, (2,5)->10, (5,1)->11, (1,0)->12, (2,1)->13, (1,1)->14, (2,3)->15, (1,3)->16, (1,4)->17, (1,5)->18, (2,7)->19, (1,7)->20, (4,0)->21, (5,0)->22, (6,0)->23, (0,4)->24, (3,5)->25, (5,3)->26, (3,1)->27, (4,1)->28, (6,1)->29, (4,3)->30, (5,5)->31, (4,5)->32, (3,2)->33, (5,2)->34, (3,3)->35, (3,4)->36, (5,4)->37, (3,7)->38, (5,7)->39, (4,4)->40, (6,2)->41, (6,4)->42, (0,5)->43, (0,7)->44, (4,7)->45, (6,5)->46, (6,3)->47 },
it remains to prove termination of the 2548-rule system
{ 0 1 2 3 -> 0 4 5 0 6 7 8 9 10 11 12 ,
  0 1 2 13 -> 0 4 5 0 6 7 8 9 10 11 14 ,
  0 1 2 9 -> 0 4 5 0 6 7 8 9 10 11 2 ,
  0 1 2 15 -> 0 4 5 0 6 7 8 9 10 11 16 ,
  0 1 2 7 -> 0 4 5 0 6 7 8 9 10 11 17 ,
  0 1 2 10 -> 0 4 5 0 6 7 8 9 10 11 18 ,
  0 1 2 19 -> 0 4 5 0 6 7 8 9 10 11 20 ,
  12 1 2 3 -> 12 4 5 0 6 7 8 9 10 11 12 ,
  12 1 2 13 -> 12 4 5 0 6 7 8 9 10 11 14 ,
  12 1 2 9 -> 12 4 5 0 6 7 8 9 10 11 2 ,
  12 1 2 15 -> 12 4 5 0 6 7 8 9 10 11 16 ,
  12 1 2 7 -> 12 4 5 0 6 7 8 9 10 11 17 ,
  12 1 2 10 -> 12 4 5 0 6 7 8 9 10 11 18 ,
  12 1 2 19 -> 12 4 5 0 6 7 8 9 10 11 20 ,
  3 1 2 3 -> 3 4 5 0 6 7 8 9 10 11 12 ,
  3 1 2 13 -> 3 4 5 0 6 7 8 9 10 11 14 ,
  3 1 2 9 -> 3 4 5 0 6 7 8 9 10 11 2 ,
  3 1 2 15 -> 3 4 5 0 6 7 8 9 10 11 16 ,
  3 1 2 7 -> 3 4 5 0 6 7 8 9 10 11 17 ,
  3 1 2 10 -> 3 4 5 0 6 7 8 9 10 11 18 ,
  3 1 2 19 -> 3 4 5 0 6 7 8 9 10 11 20 ,
  5 1 2 3 -> 5 4 5 0 6 7 8 9 10 11 12 ,
  5 1 2 13 -> 5 4 5 0 6 7 8 9 10 11 14 ,
  5 1 2 9 -> 5 4 5 0 6 7 8 9 10 11 2 ,
  5 1 2 15 -> 5 4 5 0 6 7 8 9 10 11 16 ,
  5 1 2 7 -> 5 4 5 0 6 7 8 9 10 11 17 ,
  5 1 2 10 -> 5 4 5 0 6 7 8 9 10 11 18 ,
  5 1 2 19 -> 5 4 5 0 6 7 8 9 10 11 20 ,
  21 1 2 3 -> 21 4 5 0 6 7 8 9 10 11 12 ,
  21 1 2 13 -> 21 4 5 0 6 7 8 9 10 11 14 ,
  21 1 2 9 -> 21 4 5 0 6 7 8 9 10 11 2 ,
  21 1 2 15 -> 21 4 5 0 6 7 8 9 10 11 16 ,

popout

output may be truncated. 'popout' for the full output.

job log

popout

actions all output return to SRS Standard