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SRS Standard pair #487519650
details
property
value
status
complete
benchmark
z128.xml
ran by
Akihisa Yamada
cpu timeout
1200 seconds
wallclock timeout
300 seconds
memory limit
137438953472 bytes
execution host
n189.star.cs.uiowa.edu
space
Zantema_04
run statistics
property
value
solver
MultumNonMulta 3.16 29 June 2020 60G
configuration
default
runtime (wallclock)
0.525832891464 seconds
cpu usage
0.682093161
max memory
3.53181696E8
stage attributes
key
value
output-size
888
starexec-result
NO
output
/export/starexec/sandbox/solver/bin/starexec_run_default /export/starexec/sandbox/benchmark/theBenchmark.xml /export/starexec/sandbox/output/output_files -------------------------------------------------------------------------------- NO After renaming modulo { a->0, b->1 }, it remains to prove termination of the 2-rule system { 0 0 0 -> 1 0 1 , 1 0 1 -> 0 1 0 } The system was reversed. After renaming modulo { 0->0, 1->1 }, it remains to prove termination of the 2-rule system { 0 0 0 -> 1 0 1 , 1 0 1 -> 0 1 0 } Loop of length 6 starting with a string of length 6 using right expansion and the encoding { 0->a, 1->b, ... }: .aaa.baa rule aaa-> bab at position 0 .bab.baa rule bab-> aba at position 0 .aba.baa rule bab-> aba at position 1 .aaba.aa rule aaa-> bab at position 3 .aabbab. rule bab-> aba at position 3 .aababa. rule bab-> aba at position 2 .aaabaa.
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